JPS61174677A - Manufacture of diode - Google Patents
Manufacture of diodeInfo
- Publication number
- JPS61174677A JPS61174677A JP1473485A JP1473485A JPS61174677A JP S61174677 A JPS61174677 A JP S61174677A JP 1473485 A JP1473485 A JP 1473485A JP 1473485 A JP1473485 A JP 1473485A JP S61174677 A JPS61174677 A JP S61174677A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- active layer
- substrate
- wafer
- mesa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 235000012431 wafers Nutrition 0.000 abstract description 14
- 239000010453 quartz Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000005520 cutting process Methods 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 2
- 238000002955 isolation Methods 0.000 abstract 1
- 238000009826 distribution Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- 101100492811 Drosophila melanogaster tefu gene Proteins 0.000 description 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発Ｆ！Ａは、ダイオード、特にマイクロ波帯において
、高効率、高出力を有する固体発振源としてのリード型
インバットダイオードの製造方法に関する。[Detailed description of the invention] [Industrial application field] The original F! A relates to a method for manufacturing a diode, particularly a leaded invat diode as a solid-state oscillation source having high efficiency and high output in the microwave band.
リード型インバットダイオードの不純物濃度分布は接合
部で不純物濃度が急碌にかわる蔑階段分布をしておシ、
第５図に示すように、Ｎ型低抵抗基板９にＮ型紙濃度層
３．Ｎ型高濃度層２及びＰ型高濃度層１０を順次エピタ
キシャル成長し、然る後基板９を数１０μｍの厚さにし
、表裏の１極５．６を形成した後、基板９（！！ｌ（Ｎ
側）よシエッチングを行ない、＠６図に示すチップを得
ていた。The impurity concentration distribution of a leaded invat diode has a stepwise distribution where the impurity concentration rapidly changes at the junction.
As shown in FIG. 5, an N-type paper concentration layer 3. The N-type high concentration layer 2 and the P-type high concentration layer 10 are epitaxially grown in sequence, and then the substrate 9 is made to have a thickness of several tens of μm, and one pole 5.6 is formed on the front and back sides, and then the substrate 9 (!!l( N
After etching, the chip shown in Figure @6 was obtained.
上述の従来の製造法において、基板９側からメサエッチ
ングする理由は接合部側面への電界集中を避けるためで
、このようくしないで、もしＰ型高濃度層１０側からメ
サエッチングを行なうと接合部側面への電界集中が起こ
シ特性が著しくそこなわれる。しかしながらこのメサエ
ッチングによシ接合径が決ま少、またチップの分離が行
なわｎる為、ウェハーの厚さを先述のように前もって非
常に薄くしなければならず、その後の工程におけるウェ
ハーの取扱いが困難であるという欠点がある。またウェ
ハー厚の少しのばらつきによって、接合径が大きくばら
つくという欠点もある。In the conventional manufacturing method described above, the reason why mesa etching is performed from the substrate 9 side is to avoid concentration of electric field on the side surface of the junction.If mesa etching is performed from the P-type high concentration layer 10 side without doing this, the junction Electric field concentration on the side surfaces of the parts occurs and the characteristics are significantly impaired. However, since the mesa etching method only determines the junction diameter and separates the chips, the wafer must be made very thin in advance as mentioned above, and the handling of the wafer in the subsequent process is difficult. The disadvantage is that it is difficult. Another drawback is that small variations in wafer thickness can cause large variations in bonding diameter.
本発明によれば、活性層と逆導電型の基板を用い、活性
層上に電極を形成した後、この電極をマスクとして活性
層をメサエッチングするダイオ−の製造方法を得る。According to the present invention, a method for manufacturing a diode is obtained in which a substrate of conductivity type opposite to that of the active layer is used, an electrode is formed on the active layer, and then the active layer is mesa-etched using the electrode as a mask.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例における、不純物濃度分布を
示した図である。この不純物濃度分布をしたリード型イ
ンバットダイオードは、まず第２図に示されているよう
に、Ｐ型低抵抗基板１に活性層がＮ型高濃度層２、Ｎ型
低濃度層３の順に従来とは逆の順で底長さｎ、最後にコ
ンタクト用のＮ型高濃度層４が形成さｎる。こｎらの層
２，３゜４の厚さの合計は１０（Ｅｚのリードインノミ
ットダイオードにおいても高々数μｍである。Ｎ型高濃
度層４の表面に例えばＡｕＧｅ−ＡｕＮ１−ＴニーＰｔ
−Ａｕのオーミック電極５を形成した後、これをマスク
として活性層をメサエッチングする。第２図に示さｎる
ように、接合部側面の形状については従来と同じであう
、電界集中は起こらない０また活性層のメサエッチング
の量は活性層の厚さ程度でよく、このためｔｌぼ電極径
＝接合径となシ接合径のウェハー内におけるばらつきは
非常に小さくなる。次に第３図に示すようにウェハーを
基板１側を表にしてフォトレジスト７で石英板８に貼シ
付け、研磨、エツチングによシ基板１を充分薄くした後
、例えばＴｉ−Ｐｔ−Ａｕのもう一方の電極６を形成す
る。続いて石英板８に貼シ付けた状態のまま、エッチカ
ットによりチップ分離を行ない、第４図に示すチップを
得る。FIG. 1 is a diagram showing impurity concentration distribution in one embodiment of the present invention. A lead-type invat diode with this impurity concentration distribution is first constructed of a P-type low-resistance substrate 1, an N-type high-concentration layer 2, an N-type low-concentration layer 3, and an active layer, as shown in FIG. In the reverse order from the conventional method, a base length n is formed, and finally an N-type high concentration layer 4 for contact is formed n. The total thickness of these layers 2, 3° 4 is 10 μm (even in an Ez lead-in-nomite diode, at most several μm. For example, AuGe-AuN1-T knee Pt is formed on the surface of the N-type high concentration layer 4.
After forming the -Au ohmic electrode 5, the active layer is mesa-etched using this as a mask. As shown in Fig. 2, the shape of the side surface of the junction is the same as the conventional one, no electric field concentration occurs, and the amount of mesa etching of the active layer can be approximately the same as the thickness of the active layer. When electrode diameter=junction diameter, variations in junction diameter within a wafer become extremely small. Next, as shown in FIG. 3, the wafer is pasted on a quartz plate 8 with a photoresist 7 with the substrate 1 side facing up, and after the substrate 1 is sufficiently thinned by polishing and etching, for example, Ti-Pt-Au is used. The other electrode 6 is formed. Subsequently, the chips are separated by etch cutting while still attached to the quartz plate 8 to obtain the chips shown in FIG. 4.
以上の工程において、電極形成等すべての工程はウェハ
ーが厚い状態あるいは石英板に貼シ付けらｎた状態で行
なわれるので従来のようにウェハー割ｎ等、薄いウェハ
ー取り扱い上の問題は発生しない。また、前述のように
メサエッチは薄い活性層に施されるので、接合径のバラ
ツキはきわめ□て少く、所定の特性を容易に得ることが
できる。In the above steps, all steps such as electrode formation are performed with the wafer thick or attached to a quartz plate, so that problems associated with handling thin wafers, such as wafer splitting, do not occur as in the prior art. Further, as mentioned above, since the mesa etch is performed on a thin active layer, the variation in the bonding diameter is extremely small, and predetermined characteristics can be easily obtained.
以上説明したように、本発明によｎば、活性層とは逆の
導電型の基板を用いる事により、その後の工程において
ウェハーが厚い状態で取シ扱えて取り扱いが容易であシ
、シかも接合径のばらつきが非常に小さくなるという利
点を有する。As explained above, according to the present invention, by using a substrate of a conductivity type opposite to that of the active layer, the wafer can be handled in a thick state in subsequent steps, making it easier to handle. This has the advantage that the variation in bond diameter is extremely small.
第１図は本発明の一実施例におけるダイオードの不純物
濃度分布を示した図で、ｌｒＺ図、第３図および第４図
は本発明の一実施例によるメサエッチング後、石英板貼
付後、チップ分離後のそｎぞｎのチップ断面図であるｏ
第５図は従来のダイオードの不純物濃度分布を表わす図
で、第６図はそのチップ断面図である。
１・・・・・・Ｐ型低抵抗基板、２・・・・・・Ｎ型高
濃度層、３・・・・・・Ｎ型低濃度層、４・・・・・・
Ｎ型コ／タクト用高濃度層、５・・・・・・表面電極、
６・・・・・・裏面電極、７・・・・・・フォトレジス
ト、８・・・・・・石英板、９・旧・・Ｎ型低抵抗基板
、１０・・・・・・Ｐ型高濃度層。
第１図
ノザユ１．テ復／）新面
Ｍ５ Ｚ 図FIG. 1 is a diagram showing the impurity concentration distribution of the diode in one embodiment of the present invention, and the lrZ diagram, FIG. 3, and FIG. This is a cross-sectional view of the chip after separation.
FIG. 5 is a diagram showing the impurity concentration distribution of a conventional diode, and FIG. 6 is a cross-sectional view of its chip. 1... P-type low resistance substrate, 2... N-type high concentration layer, 3... N-type low concentration layer, 4...
N-type co/tact high concentration layer, 5... surface electrode,
6... Back electrode, 7... Photoresist, 8... Quartz plate, 9... Old... N type low resistance substrate, 10... P type High concentration layer. Figure 1 Nozayu 1. Tefu/) New side M5 Z diagram
Claims (1)
シャル成長する工程と、該活性層上に電極を形成する工
程と、該電極をマスクとし所定の接合径に前記活性層を
メサエッチングする工程とを含むことを特徴とするダイ
オードの製造方法。A process of epitaxially growing an active layer of one conductivity type on a low resistance substrate of another conductivity type, a process of forming an electrode on the active layer, and a process of mesa-etching the active layer to a predetermined junction diameter using the electrode as a mask. A method for manufacturing a diode, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1473485A JPS61174677A (en) | 1985-01-29 | 1985-01-29 | Manufacture of diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1473485A JPS61174677A (en) | 1985-01-29 | 1985-01-29 | Manufacture of diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61174677A true JPS61174677A (en) | 1986-08-06 |
Family
ID=11869352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1473485A Pending JPS61174677A (en) | 1985-01-29 | 1985-01-29 | Manufacture of diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174677A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009158697A (en) * | 2007-12-26 | 2009-07-16 | Sharp Corp | Bypass diode for solar cell and method of manufacturing the same |
-
1985
- 1985-01-29 JP JP1473485A patent/JPS61174677A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009158697A (en) * | 2007-12-26 | 2009-07-16 | Sharp Corp | Bypass diode for solar cell and method of manufacturing the same |
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