JP2606664B2 - Method for manufacturing mesa-type bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a mesa bipolar transistor, and more particularly to a method of forming an emitter mesa with an insulating spacer having an overhanging cross section.

[0002]

2. Description of the Related Art In recent years, research and development of an integrated circuit using a heterojunction bipolar transistor (HBT) using a compound semiconductor have been promoted.

In the manufacturing process of such a compound semiconductor integrated circuit, it is necessary to miniaturize the element in order to realize high integration and high speed. For this purpose, it is important to develop a self-aligned process technology for arranging each electrode of the element in a self-aligned manner. FIG. 8 shows a conventional first bipolar in which a base electrode is arranged in a self-aligned manner with respect to an emitter electrode. FIG. 3 is a cross-sectional view illustrating a main part of a transistor.

First, on a semi-insulating GaAs substrate 1, for example, an n-type GaAs collector layer 2, a p-type GaAs base layer 3, an n-type Al _0.3 Ga _0.7 As emitter layer 4 and n
After forming a first emitter electrode 9a on a semiconductor substrate on which a ⁺ -type In _y Ga _1-y As emitter cap layer 5 is sequentially epitaxially grown, an insulating region 12 for element isolation is formed by ion implantation.

Next, using the first emitter electrode 9a as a mask, the In _y Ga _1-y As emitter cap layer 5 and the Al _0.3 Ga _0.7 As emitter layer 4 are formed by an anisotropic etching technique typified by wet etching. Etching is performed to expose the GaAs base layer 3. At this time, the emitter mesas (4, 5) are slightly recessed with respect to the first emitter electrode 9a to form an overhang shape, and then a conductive film for the base electrode 13B is formed on the entire surface, so that the emitter electrode ( The first emitter electrode 9a and the second emitter electrode 13Ea are stacked) and GaAs
The base electrode 13B is self-aligned with the s emitter layer 4.
Can be realized.

However, in this conventional example, when the GaAs base layer 3 is exposed by wet etching using the first emitter electrode 9a as a mask to form an emitter mesa, the first emitter electrode 9a and the In _y Ga _{1− y} A
If the adhesion to the s emitter cap layer 5 is poor, the first emitter electrode 9a may be peeled off by the etching solution, and this problem becomes more serious as the width of the first emitter electrode 9a becomes smaller.

Further, since the emitter mesa is formed by isotropic etching, the cross-sectional shape of the emitter mesa becomes trapezoidal, so that the contact area between the first emitter electrode 9a and the emitter mesa is reduced, the emitter contact resistance is increased, and the fineness of the element is reduced. However, it has a disadvantage that it is disadvantageous for the production.

A second conventional bipolar transistor proposed to solve such a disadvantage will be described with reference to FIG.

First, on a semi-insulating GaAs substrate 1, an n-type GaAs collector layer 2, a p-type GaAs base layer 3,
First emitter electrode 9b on the type of Al _0.3 Ga _0.7 As emitter layer 4 and the n ⁺ -type In _y Ga _1-y As are epitaxially grown semiconductor substrate an emitter cap layer 5
Is formed, anisotropic dry etching is performed using the first emitter electrode 9b as a mask to expose the GaAs base layer 3 to form an emitter mesa, and an insulating spacer 11a made of SiO ₂ is formed on a side surface of the emitter mesa. An insulating region 12 for element isolation is formed by ion implantation. Subsequently, a base electrode 13B is formed on the exposed GaAs base layer 3. Thereafter, the GaAs collector layer 2 is exposed using a photoresist film (not shown) as a mask,
The collector electrode 14 is formed by a lift-off method.

In this conventional second bipolar transistor, the first emitter electrode 9b is directly formed by using the photoresist film as a mask, and the emitter mesa is anisotropically formed by using the photoresist film or the first emitter electrode 9b as a mask. It is formed by dry etching. Therefore, the emitter region can be miniaturized by miniaturizing the photoresist pattern. Moreover, the distance between the emitter region and the base electrode is defined by the thickness of the insulating spacer 11a surrounding the emitter region, the base resistance and the like can be reduced, and the drawback of the conventional first bipolar transistor is improved.

[0011]

In a conventional bipolar transistor in which an emitter region is separated from a base electrode by providing an insulating spacer on the side surface of the emitter mesa, a conductive film for the base electrode is formed by a vapor deposition method or the like. The conductive material 15 also adheres to the side surface of the insulating spacer on the base electrode 13.
B and the emitter electrode (the first emitter electrode 9b and the second emitter electrode 13Eb) are short-circuited. In order to avoid this, it is necessary to electrically remove the base material 13B and the emitter electrode by etching away the conductive material 15 attached to the side surface with an oblique ion beam using an Ar-ion milling device or the like. . However, sufficient etching must be performed to remove the conductive material once adhered to prevent short circuit and leakage current, so that the insulating spacer is damaged and the withstand voltage is deteriorated, and in some cases, the emitter mesa is also damaged. Therefore, there is a problem in that it is difficult to obtain a bipolar transistor having good characteristics because the leakage current increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a mesa-type bipolar transistor which can avoid a short circuit between a base and an emitter when a base electrode is formed in a self-aligned manner with respect to an emitter mesa and an emitter electrode and can miniaturize the element. Is to provide.

[0013]

According to a method of manufacturing a mesa bipolar transistor of the present invention, a first conductive type collector layer, a second conductive type base layer and a first conductive type base layer are formed on one main surface of a semiconductor substrate. Preparing a semiconductor substrate by sequentially epitaxially growing at least three of the emitter layers of
Forming a first electrode film which is in ohmic contact with the emitter layer directly or via an emitter cap layer, and patterning the first electrode film to form a first emitter electrode projecting in a direction away from the one main surface at a peripheral portion thereof; Etching the emitter layer or the emitter cap layer and the emitter layer using the first emitter electrode as a mask to expose the base layer to form an emitter mesa; Etching to form insulating spacers on the side surfaces of the first emitter electrode and the emitter mesa; forming a second electrode film in ohmic contact with the base layer and connecting to the first emitter electrode Contacting the exposed second emitter electrode and the exposed surface of the base layer with the second emitter electrode and the insulating spacer. It is that a step of forming a base electrode layer is released.

A preferred method of forming the above-mentioned first emitter electrode having projections is to irradiate an ion beam using an inert gas at an incident angle of 0 to 30 ° with respect to the substrate to utilize the re-deposition of the substance to be etched. That is. In this case, the first conductive film in ohmic contact with the first electrode film and the emitter layer or the emitter cap layer, and the second conductive film having a small etching rate with respect to a predetermined etching means for etching the first conductive layer. First, the second conductive layer is patterned by an ion beam etching method using an inert gas into a shape having protrusions, and then the first conductive layer is formed.
Preferably, the conductive layer is selectively etched.

[0015]

The insulating film is deposited after the emitter mesa is formed using the first emitter electrode having the projection as a mask, so that the insulating film can be thickly formed in the vicinity of the projection and the vicinity thereof. A composite in which insulating spacers are provided on the side surfaces of the structure can be formed in an overhang shape. Therefore, the second electrode film that makes ohmic contact with the base layer can be formed separately on the first emitter electrode and the base layer, and no short circuit occurs between the emitter and the base.

[0016]

Next, a first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1, an n-type GaAs collector layer 2 is formed on a semi-insulating GaAs substrate 1 (semiconductor substrate).
(Impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 500 nm to 1
μm), p-type GaAs base layer 3 (impurity concentration 4 × 1
0 ¹⁹ / cm ³ , thickness 20 to 200 nm), n-type Al
_0.3 Ga _0.7 As emitter layer 4 (impurity concentration 5 × 10 ¹⁷
/ Cm ³ , thickness 220 nm), n ⁺ -type In _y Ga _1-y
As cap layer 5 (y = 0.1 to 0.5, impurity concentration 2
(× 10 ¹⁹ / cm ³ , thickness 100 nm) are sequentially epitaxially grown to prepare a semiconductor substrate. Next, WSi _z layer as the first conductive layer for forming the first electrode film 6
1 (z is 0 to 0.5, thickness 200 nm), and an Au layer 6-2 (thickness 400 nm) as a second conductive layer is deposited on the entire surface. Next, a photoresist film 7 for defining an emitter electrode width is formed, and using this photoresist film 7 as a mask,
The Au layer 6-2 ion etching by an ion milling apparatus, to expose the WSi _z layer 6-2. At this time, the etching conditions of the ion milling apparatus are set such that the angle of incidence of the Ar-ion beam on the substrate (the angle between the direction perpendicular to the main surface of the substrate) and the substrate is 0 to 30 degrees.
By attaching u) again to the side surface of the photoresist film 7, a projection 8 is formed as shown in FIG.

Furthermore, the WSi _z layer 6-1 is etched by reactive ion etching using SF ₆ gas, FIG. 2
As shown in (b), a first emitter electrode 9c is formed.

Next, by reactive ion beam etching (RIBE) using chlorine gas, the photoresist film 7 or the first emitter electrode 9c is used as a mask.
GaAs emitter cap layer 5 and Al _0.3 Ga _0.7
By etching the As emitter layer 4 and exposing the base layer 3, an emitter mesa 10 is formed as shown in FIG. After removing the photoresist film 7, an SiO ₂ film 11 is deposited as an insulating film on the entire surface by a CVD method. At this time, as shown in FIG. 4, SiO ₂ film 11
Is thicker at the projection 8, especially at the tip, and thinner at the side surfaces of the emitter mesa 10 or the first emitter electrode (6-2). This is based on the fact that the step coverage of forming a SiO ₂ film by the CVD method is not good.

Next, FIG. 5 by performing anisotropic etching by reactive ion etching (RIE) method using CF ₄
As shown in FIG. 6, the surface parallel to the substrate, that is, the SiO ₂ film (11s in FIG. 4) on the top of the GaAs base layer 3 and the first emitter electrode 9c is removed to form an insulating spacer 11b. In this manner, the mesa (emitter mesa, first emitter electrode, and insulating spacer 11) having the overhang shape are formed.
b) can be formed.

Next, after an insulating region 12 for element isolation is formed by ion implantation, a second electrode film 13 (for example, T
An i layer, a Pt layer, and an Au layer are sequentially formed) on the entire surface by a film forming means having good directivity of evaporated particles represented by a vacuum evaporation method. At this time, since the above-mentioned mesa has an overhang shape, adhesion of metal to the side surface of the insulating spacer 11b is prevented, and the second contacting the first emitter electrode.
The emitter electrode 13Ec can be spatially and electrically separated from the second electrode film 13 on the base layer 3.

Finally, as shown in FIG. 7, a second electrode film 13 on the base layer 3 is formed by using a photoresist film (not shown) for defining a base electrode width for forming a base mesa as a mask.
The exposed portion and the base layer thereunder are ion-etched to expose the collector layer 2, whereby the base electrode 13B is formed.

Next, after a part of the collector layer 2 is removed by wet etching using a photoresist film (not shown) as a mask, a metal (for example, A
(uGe / Ni / Au) film formation and lift-off to form the collector electrode 14, thereby completing the mesa bipolar transistor.

It is possible to form a projection without providing the Au layer 6-2. In that case WSi _z 6-1
The ratio between the ion beam etching using an inert gas and the reactive ion etching may be appropriately determined for patterning. That is, conventionally, patterning was performed only by reactive ion etching, but only the combination of two types of etching was changed. Therefore, it was only necessary to change the etching conditions of ion milling, and the number of steps did not increase.

In the above description, a Si substrate may be used instead of the semi-insulating GaAs substrate, and GaAs or the like may be formed thereon. Also, HB with wide gap emitter structure
Although T has been described, the emitter may be formed of GaAs. In that case, the emitter cap layer is not necessarily provided. Further, the present invention is not limited to GaAs and GaAs-AlGaAs, and other compound semiconductors can be used.

Further, the method of providing the projection is the same as that of Ar-
Instead of using the re-deposition by ion beam etching, the first electrode film may be patterned into a mesa using lithography, and then the center of the top of the mesa may be etched again using lithography. .

[0027]

As described above, by providing a protrusion at the upper end of the first emitter electrode, the shape of the insulating spacer attached to the side surface of the emitter mesa can be made thicker at the protrusion.
When the second electrode film for forming the base electrode is formed, the first electrode and the base layer can be spatially separated from each other when the second electrode film is formed, so that a short circuit between the base and the emitter and a leakage current can be prevented.

Since the step of removing the conductive material attached to the side surfaces of the insulating spacer as in the prior art is not required, the insulating spacer and the like are not damaged, and the conditions for forming the second electrode film are strictly regulated. Since it is not necessary to perform the process, the number of sheets to be processed at the same time can be increased, and short-circuiting of the working process can be performed. The device can be miniaturized as in the conventional example described with reference to FIG.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1A) and a cross-sectional view (FIG. 1B) for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view in the order of steps, which is separated from FIGS.

3 is a plan view (FIG. 3A) and a cross-sectional view (FIG. 3B) shown after FIG.

FIG. 4 is a sectional view shown after FIG. 3;

5 is a plan view (FIG. 5A) and a cross-sectional view (FIG. 5B) shown after FIG.

FIG. 6 is a sectional view shown after FIG. 5;

FIG. 7 is a plan view (FIG. 7A) and a cross-sectional view (FIG. 7B) shown after FIG.

FIG. 8 is a sectional view showing a conventional first bipolar transistor.

FIG. 9 is a sectional view showing a second conventional bipolar transistor.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 GaAs collector layer 3 GaAs base layer 4 Al _0.3 Ga _0.7 As emitter layer 5 In _y Ga _1-y As emitter cap layer 6-1 WSi _z layer (first conductive layer) 6-2 Au Layer (second conductive layer) 8 Projections 9a, 9b, 9c First emitter electrode 10 Emitter mesa 11, 11s SiO ₂ film 11a, 11b Insulating spacer 12 Insulating region 13 Second electrode film 13B Base electrode 13E Second Emitter electrode

Claims (6)

(57) [Claims] 1. A semiconductor substrate comprising: a first conductive type collector layer, a second conductive type base layer, and a first conductive type emitter layer, which are sequentially epitaxially grown on one main surface of a semiconductor substrate to form a semiconductor substrate. Preparing a first electrode film which is in ohmic contact with the emitter layer directly or via an emitter cap layer, and is patterned to form a first emitter film which projects in a direction away from the one main surface at a peripheral portion thereof; Forming an electrode, etching the emitter layer or the emitter cap layer and the emitter layer using the first emitter electrode as a mask to expose the base layer, and forming an emitter mesa; Depositing and performing anisotropic etching to form insulating spacers on the side surfaces of the first emitter electrode and the emitter mesa; Forming a second electrode film in ohmic contact with the base layer, and contacting the second emitter electrode connected to the first emitter electrode and the exposed surface of the base layer with the second emitter electrode; Forming a base electrode layer separated by the insulating spacer. 2. A first electrode film is formed by depositing a first conductive layer and depositing a second conductive layer having a low etching rate with respect to a predetermined etching means for etching the first conductive layer. 2. The mesa bipolar transistor according to claim 1, wherein said second conductive film is etched by a lithography method and an ion beam etching method using an inert gas, and then said first conductive film is etched by said predetermined etching means. Manufacturing method. 3. The method according to claim 1, wherein each of the collector layer, the base layer and the emitter layer is made of a compound semiconductor. 4. The semiconductor device according to claim 1, wherein the emitter layer is a compound semiconductor layer having a larger band gap than the base layer.
A method for manufacturing the mesa-type bipolar transistor described in the above. 5. A GaAs collector layer of a first conductivity type and GaAs of a second conductivity type on one main surface of a semi-insulating GaAs substrate.
A base layer, a first conductivity type Al _x Ga _1-x As emitter layer (0 <x <1), and a first conductivity type In _y Ga _1-y As emitter cap layer (0 <y <1) are sequentially formed. Preparing a compound semiconductor substrate by epitaxial growth;
Depositing a first conductive layer in ohmic contact with the As emitter collector layer and depositing a second conductive layer having a low etching rate with respect to a predetermined etching means for etching the first conductive layer; An electrode film is formed, the second conductive film is selectively etched by lithography by an ion beam etching method using an inert gas, and the first conductive film is selectively etched by a reactive ion etching method. Forming a first emitter electrode protruding in a direction away from the one main surface at a peripheral portion thereof, and using the first emitter electrode as a mask to form the In _y Ga _1-y As emitter cap layer and The Al _x Ga _{1 -x} As emitter layer is etched to form the G
forming an emitter mesa by exposing the aAs base layer; forming an insulating spacer on the entire surface and performing anisotropic etching to form insulating spacers on side surfaces of the first emitter electrode and the emitter mesa; Forming a second electrode film in ohmic contact with the GaAs base layer to contact the second emitter electrode connected to the first emitter electrode and the exposed surface of the GaAs base layer;
Forming a base electrode layer separated by the above-mentioned emitter electrode and the insulating spacer. 6. WSi _z layer as the first conductive layer (0 <z
<1) is formed, a gold film is formed as a second conductive layer, and S
The reactive ion etching using F ₆ gas is used for the W
6. The method for manufacturing a mesa bipolar transistor according to claim 5, wherein the Si _z layer is etched.