JPS61174659A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61174659A
JPS61174659A JP60014736A JP1473685A JPS61174659A JP S61174659 A JPS61174659 A JP S61174659A JP 60014736 A JP60014736 A JP 60014736A JP 1473685 A JP1473685 A JP 1473685A JP S61174659 A JPS61174659 A JP S61174659A
Authority
JP
Japan
Prior art keywords
recognition
pattern
patterns
distance
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60014736A
Other languages
Japanese (ja)
Inventor
Hideo Sakauchi
坂内　英雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60014736A priority Critical patent/JPS61174659A/en
Publication of JPS61174659A publication Critical patent/JPS61174659A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To ensure accuracy of positioning in a bonding process, to enhance fabrication yield, and to improve product quality by a method wherein patterns are provided exclusively for the purpose of recognition. CONSTITUTION:The semiconductor device of this design is provided on its semiconductor substrate with patterns, in addition to an element electrode pattern, to be employed exclusively for the recognition of a bonding pad section to be used in an automatic wire-bonding process. That is to say, a pattern exclusively for such recognition is designed, not related with any element electrode pattern, with its shape, dimensions, arrangement, and the distance from element sections appropriately chosen. A pattern as simple as possible is preferred, preferably a square or cross with each of its sides not shorter than 50mums. Though there are not specifications on the distance between a recognition pattern and a nearby element, it is desired that it be as large as possible. A distance of 50mums or more ensures that there be virtually no ill effect on pattern recognition. As for the number of recognition patterns, a single-pattern setup does ensure excellent recognition and the use of two or more patterns ensures the best results.

Description

【発明の詳細な説明】 〔虚業上の利用分野〕 本発明に半導体装置に関し、特にその製造に於ける組立
工程での自動ワイヤ・ボンディングを行う上で有用とな
る構造を具備する半導体装置に関するものである。[Detailed description of the invention] [Field of practical application] The present invention relates to a semiconductor device, and in particular to a semiconductor device having a structure useful for automatic wire bonding in the assembly process of manufacturing the same. It is.

〔従来の技術〕[Conventional technology]

半導体装置の組立に於て、一般に量産性を考慮し、自動
化技術が必須のものとなり、ている、従来特にワイヤ・
ボンディングの工程では、＠３図に示すＬ５な半導体チ
ップ上の電極引出レボンディングパッド部４．５ｔ−直
接パターン認識しチップとパッケージの電極リード部と
の間を金又はアルミニウム等の細線を用＾て、ワイヤ・
ボンディングを行って込た。In the assembly of semiconductor devices, automation technology has generally become essential in consideration of mass production.
In the bonding process, a thin wire of gold or aluminum is used between the electrode lead part of the chip and the package by direct pattern recognition of the electrode lead rebonding pad part 4.5t on the L5 semiconductor chip shown in Figure 3. The wire
I went through the bonding.

〔発明が解決しょうとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置に於ける自動ワイヤ・ボンデ
ィング方式であるエミッタ及びベースの電極引出しボン
デイングパッド部４．５の直接認識では、ボンディング
位置精度の精密な制御が非常に困難であっ九、即ち、組
立工程に於ける歩留及び品質の面で多いに不具合な点が
あり九、これまでにかかる電極引出しボンデイングパッ
ド部４゜５の認識精度を上げるためには、ボンディング
バット部以外からのノイズを出来るだけ少なくする九め
に電極以外のメタル部分を全て除去するか又は、最小限
に小さくしてより認識積置向上に努力して来た。しかし
特に超高速用半導体素子について框、チップのパターン
そのものが・超微細パターンになって２９、且つ、ボン
ディングバット部４゜５０面積も、その電気的特性の制
約から非常に小さくなっている。一方、従来方式の自動
ワイヤ・ボンディング方式でに、位置精度が悪く、少し
の位置ずれが配線パターン下の５ｉＯｚにもとづ（ＭＯ
８容量バラツキの原因となり、特に超高周波では、その
バラツキは利得のバラツキになり、バラツキを少さくす
るためにもボンディング位置の位置精度の向上に大いに
望まれている。In the above-mentioned automatic wire bonding method in the conventional semiconductor device, in which the emitter and base electrode lead-out bonding pad portions 4.5 are directly recognized, precise control of bonding position accuracy is extremely difficult. There are many problems in terms of yield and quality in the assembly process9, so in order to improve the recognition accuracy of the electrode lead bonding pad part 4.5, it is necessary to eliminate noise from other than the bonding butt part. Ninth, efforts have been made to remove all metal parts other than the electrodes or to minimize their size to improve the recognition space. However, particularly for ultra-high-speed semiconductor devices, the frame and chip patterns themselves have become ultra-fine patterns29, and the area of the bonding butt portion has also become extremely small due to restrictions on its electrical characteristics. On the other hand, in the conventional automatic wire bonding method, the position accuracy is poor, and even a small positional deviation is caused by 5iOz under the wiring pattern (MO
Particularly at ultra-high frequencies, this variation causes variation in the gain, and in order to reduce the variation, it is highly desirable to improve the positional accuracy of the bonding position.

〔問題点ｋｓ決するための手段〕[Means for resolving problems]

本発明による半導体装置は半導体基板上に自動ワイヤ・
ボンディングに於けるボンデイングパッド部のパターン
認識のため認識専用のパターンを素子電極パターンの他
に有している。即ち、認識専用パターンは素子電極パタ
ーンに関係なく、最もパターン認識が′ａ度よく出来る
形状１寸法、配置等全考慮し素子部とは適当に間隔をも
って、設計されるものである。特に超高速用の超微細パ
ターンの場合には一般に素子寸法は極限に近い寸法で設
計されその為にパターンの認識性は電気的特性が優先さ
れるので無視されていた。専用の認識パターンとしては
、出来るだけ簡単なパターン、例えば正方形、十字形等
が良く、寸法的には一辺が５０μｍ以上が好ましい。又
配置としては、特に制限框ないが、素子との間隔は出来
るだけ離し友方が好ましい、検討の結果５０μｍ以上あ
ればパターン認識にはほとんど影響はなかつ九。又、認
識パターンの個数は、１個では認識性が悪く、少なくと
も２個以上で、３個の方が最も良好であった。The semiconductor device according to the present invention automatically wires and
In order to recognize the pattern of the bonding pad portion during bonding, a recognition-only pattern is provided in addition to the element electrode pattern. That is, the recognition-dedicated pattern is designed with an appropriate spacing from the element portion, taking into consideration all aspects such as shape, dimensions, arrangement, etc., which allow for the best pattern recognition, regardless of the element electrode pattern. Particularly in the case of ultra-fine patterns for ultra-high speed applications, the device dimensions are generally designed to be close to the limit, and therefore, pattern recognition has been ignored as electrical characteristics take precedence. The dedicated recognition pattern is preferably a pattern as simple as possible, such as a square or a cross, and preferably has a side of 50 μm or more. There are no particular restrictions on the arrangement, but it is preferable to keep the distance between the elements as far as possible; studies have shown that if the distance is 50 μm or more, it will have little effect on pattern recognition. In addition, when the number of recognition patterns is 1, the recognition performance is poor, and when the number of recognition patterns is at least 2, the recognition performance is best when there are 3 or more.

〔実施例〕〔Example〕

次に本発明について、図ｔＪを参照して実施例を説明す
る。Next, an embodiment of the present invention will be described with reference to FIG. tJ.

＠１図は本発明の第１の実施例を示す半導体チップの表
面を示す構造図であり、１はエミッタ電極、２にベース
電極、３は正方形の専用認識パターンである。第２図に
本発明の第２の実施例を示す半導体チップの表面を示す
構造図で、専用認識パターン３′が十文字形の形状で形
成されていることが特徴である。１′はエミッタ電極、
２′はベース電極である。半導体チップに於ける素子の
電極及び専用認識パターンの形成材料として、アルミニ
ウム又はその合金全使用し九場合、すでにエミッタ及び
ベース領域が形成され友半導体基板上にスパッタ又は蒸
着にＬＤ積層し友後、写真食刻法に＝９、半導体層との
電気的接点及び電極引出しボンディング・バッドを形成
する。又は、別の金属材料として、金を使用する場合メ
ッキ又は蒸着等にＬＤ、電極を形成し、前記と同様にＬ
Ｄ、写真食刻ｆ＆に工って、電極引出しボンディング・
バッドを形成する。Figure @1 is a structural diagram showing the surface of a semiconductor chip showing a first embodiment of the present invention, in which 1 is an emitter electrode, 2 is a base electrode, and 3 is a square dedicated recognition pattern. FIG. 2 is a structural diagram showing the surface of a semiconductor chip showing a second embodiment of the present invention, which is characterized in that a dedicated recognition pattern 3' is formed in the shape of a cross. 1' is the emitter electrode,
2' is a base electrode. When aluminum or its alloys are used as the material for forming the electrodes and special recognition patterns of the elements in the semiconductor chip, the emitter and base regions are already formed and the LD is laminated by sputtering or vapor deposition on the semiconductor substrate. Photolithography=9 to form electrical contacts with the semiconductor layer and electrode lead-out bonding pads. Alternatively, if gold is used as another metal material, the LD and electrode are formed by plating or vapor deposition, and the L
D. Photo-engraved f&, electrode drawer bonding.
Form a bad.

〔発明の効果〕〔Effect of the invention〕

以上説明し几工うに本発明は、専用の認識パターンを新
ら九に設けることはエリ、先ず認識パターンで正確に位
置を求め、ついで、その位置工りあらかじめボンティン
グバット部の距離をプログラムされた記憶装置１９出力
され比信号が演算装置により精密なボンディング位置を
導出し、実行に移されるものである。従来に、上述した
様にボンディング・バッド部を直接認識してい友為にパ
ターン形状の不適性９寸法の不適性及びノイズ等にエフ
ボンディング位置精度が不正確であり九が、本発明に工
りその位置精度は飛躍的に向上し、組立歩留及び品質向
上に大いに効果全発揮することが可能になった。As explained above, the present invention is advantageous in that a dedicated recognition pattern is provided in the new nine. The ratio signal outputted from the storage device 19 is used to derive a precise bonding position by an arithmetic unit and then executed. Conventionally, as mentioned above, the bonding pad part was directly recognized, resulting in inaccurate f-bonding position accuracy due to unsuitable pattern shape, unsuitable dimensions, noise, etc., but the present invention has been improved. Its positional accuracy has been dramatically improved, making it possible to fully demonstrate its effectiveness in improving assembly yield and quality.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明のＩｇｌの実施例に於ける半導体チップ
の表面を示す平面図、第２図に本発明の第２の実施例に
於ける半導体チップの表Ｗを示す平面図、第３図は従来
構造の半導体チップの表面を示す平面図である。 １．１′・・・・・・エミッタ電極、２．２’・・・・
・・ベース電極、３．３’・・・・・・専用認識パター
ン、４．５・・・・・・ボンデイングパッド部。FIG. 1 is a plan view showing the surface of a semiconductor chip in an Igl embodiment of the present invention, FIG. 2 is a plan view showing the front surface W of a semiconductor chip in a second embodiment of the present invention, and FIG. The figure is a plan view showing the surface of a semiconductor chip with a conventional structure. 1.1'...Emitter electrode, 2.2'...
... Base electrode, 3.3' ... Dedicated recognition pattern, 4.5 ... Bonding pad section.

Claims (1)

【特許請求の範囲】[Claims] 　半導体基板表面上に電極配線とは分離してボンデイン
グパッドの位置認識のための専用認識パターンを少なく
とも２ケ以上具備したことを特徴とする半導体装置。1. A semiconductor device comprising at least two dedicated recognition patterns for recognizing the position of a bonding pad, separate from electrode wiring, on a surface of a semiconductor substrate.
JP60014736A 1985-01-29 1985-01-29 Semiconductor device Pending JPS61174659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60014736A JPS61174659A (en) 1985-01-29 1985-01-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60014736A JPS61174659A (en) 1985-01-29 1985-01-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61174659A true JPS61174659A (en) 1986-08-06

Family

ID=11869406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60014736A Pending JPS61174659A (en) 1985-01-29 1985-01-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61174659A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0212847A (en) * 1988-06-30 1990-01-17 Nec Corp Integrated circuit device
US5053850A (en) * 1988-03-14 1991-10-01 Motorola, Inc. Bonding pad for semiconductor devices
US6555922B1 (en) * 1999-03-18 2003-04-29 Fujitsu Limited IC bonding pad combined with mark or monitor
JP2006308335A (en) * 2005-04-26 2006-11-09 Chiba Univ Differential scanning calorimeter capable of performing high-pressure measurement and differential scanning calorimeter apparatus using same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053850A (en) * 1988-03-14 1991-10-01 Motorola, Inc. Bonding pad for semiconductor devices
JPH0212847A (en) * 1988-06-30 1990-01-17 Nec Corp Integrated circuit device
US6555922B1 (en) * 1999-03-18 2003-04-29 Fujitsu Limited IC bonding pad combined with mark or monitor
JP2006308335A (en) * 2005-04-26 2006-11-09 Chiba Univ Differential scanning calorimeter capable of performing high-pressure measurement and differential scanning calorimeter apparatus using same

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