JPS6117371B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase shift circuit suitable for use in, for example, an NTC encoder.

According to the circuit shown in Figure 1, the input signal is connected between the base and emitter of the transistor Qa and the capacitor Ca.
Since the transistor is supplied to the series circuit with
At the emitter of Qa, it is possible to obtain a phase-shifted output with a phase determined by the emitter resistor r _e and the capacitor Ca. In that case, the emitter resistance r _e has a relationship with the emitter current I _E as r _e [Ω] 〓26/I _E [mA], so the current I _E can be changed by changing the constant current source Qb. , the resistance r _e changes and the circuit therefore works as a variable phase shift circuit.

However, in this phase shift circuit, the emitter current I
Since _E also changes depending on the input signal, when the signal level is large, the resistance r
_e changes, resulting in harmonic distortion. Therefore, the output level of this phase shift circuit becomes small.

Also, since the phase-shifted output is an unbalanced output, for example
In an NTSC encoder, when using this phase shift circuit to obtain a subcarrier signal for a red color difference signal and a subcarrier signal for a blue color difference signal, the phase shift output of this phase shift circuit is The DC component must be taken out of the IC, cut off with a capacitor, and then brought back into the IC to be supplied to the balanced modulation circuit, which increases the number of pins on the IC and makes it unsuitable for integration into an IC.

In view of these points, it is an object of the present invention to provide a phase shift circuit that has little harmonic distortion, can obtain a phase shift output with a large output level, and is suitable for IC implementation.

Let's explain one example below.

Now, in the circuit shown in Fig. 2, if the angular frequency of the voltages V and -V is ω, then the voltages V ₁ and V ₂ are as follows: V ₁ =-V/1+j2ωCR V ₂ =V/1+j2ω
It becomes CR. Therefore, when calculating the voltages V ₁ +V/2 and V ₂ -V/2, V ₁ +V/2=-1/2・1-j2ωCR/1+j2ω
CRV……(i) V ₂ −V/2=1/2・1−j2ωCR/1+j2ωC
RV...(ii) The vector diagram becomes as shown in Figure 3. In other words, the voltages V ₁ +V/2 and V ₂ -V/2 have a constant level regardless of the time constant CR, and a phase of -
It can be seen that 2tan ^-1 2ωCR. Moreover, both voltages are in opposite phases to each other.

This invention constructs a phase shift circuit by utilizing the relationship of equations (i) and (ii).

In FIG. 4, the emitters of transistors Q ₁ and Q ₂ are connected to the collectors of constant current transistor Q ₁₂ , and the collectors of transistors Q ₁ and Q ₂ are connected to resistors R ₁ and R ₃ and R ₂ and R ₄ . are connected to constitute a differential amplifier, and subcarrier signals (voltages) V having mutually opposite phases are supplied from a signal source 10 to the bases of transistors Q ₁ and Q ₂ . Also, transistor
The emitters of Q ₃ and Q ₄ are constant current source transistors.
Transistors connected to the collectors of Q ₁₃ and Q ₁₄
Q ₃ and Q ₄ are used as emitter followers, and their bases are connected to the collectors of transistors Q ₁ and Q ₂ , and a capacitor C ₁ is connected between their emitters. In this case, the emitter resistances r _e of the transistors Q ₃ and Q ₄ correspond to the resistor R in FIG. 2, and the capacitor C ₁ corresponds to the capacitor C.

Furthermore, resistors R ₅ and R ₆ are connected to the emitters of transistors Q ₅ and Q ₆ , making transistors Q ₅ and Q ₆ emitter followers, and their bases are connected to the connection point of resistors R ₁ and R ₃ and the resistor. The resistors R 5 and R 6 are connected to the connection point of the transistors R ₂ and R ₄ , and the resistors R ₅ and R ₆ are
Connected to the collectors of Q ₇ and Q ₈ . The emitters of these transistors Q ₇ and Q ₈ are connected to a constant current source transistor Q ₁₁ through resistors R ₇ and R ₈ .
Output terminals T 11 and T 12 are connected to the emitters of transistors Q ₅ and Q ₆ , and output terminals T ₁₁ and T ₁₂ are connected to the emitters of transistors Q ₅ and Q _6.
Output terminals T ₂₁ and T ₂₂ are connected to the collector of.

In addition, transistors Q ₁₁ and Q ₁₂ are
Q ₁₀ is connected to form a current mirror circuit, and a constant collector current is passed through transistors Q ₁₁ and Q ₁₂ . Furthermore, transistors Q ₁₃ , Q ₁₄
A current mirror circuit is configured by Q15 and _Q15 , and the transistor _Q15 is connected to the control terminal _T1 . In addition, _R1 : _R3 = _R7 : _R5 R1= _{R2 , R3} = _R4 , _R5 = _R6 , _R7 = _R8 , for example, resistors _R1 to _R4 , _R5 ~ _R8
are each made equal to each other.

According to such a configuration, the subcarrier signal V from the signal source 10 is supplied to the transistors Q ₁ and Q ₂ , and the signal voltages −V,
V is obtained and supplied to the bases of transistors Q ₃ and Q ₄ . Since the emitter resistance r _e of _the transistors Q ₃ and Q ₄ corresponds to the resistor R in FIG. 2, and _the capacitor C ₁ corresponds to the capacitor C, the voltage V ₁ , _V2
is obtained, which is supplied to the bases of transistors Q ₇ and Q ₈ , and voltages -V ₁ and -V ₂ are obtained at their collectors.

Furthermore, since the signal V is supplied to the transistors Q ₁ and Q ₂ , the voltages −V/2 and V/ ₂ are applied to the connection point of the resistors R ₁ and R ₃ and the connection point of the resistors R 2 and R ₄ . is obtained, which connects the resistor through transistors Q ₅ and Q ₆
Supplied to R ₅ and R ₆ .

Therefore, in resistor R ₅ the voltages −V ₁ and −
V/2 is added, so the voltage −( _{V 1}
+V/2) is taken out. Further, since the voltages _-V2 and V/2 are added at the resistor _R6 , the voltage -( _V2 -V/2) is taken out at the terminal _T22 .

Furthermore, the voltages −V/2 and V/2 are applied to the transistor Q ₅ ,
It is taken out to terminals T ₁₁ and T ₁₂ through Q ₆ .

In this case, when a control voltage is supplied to terminal _T1 , the transistor
Since the collector currents of Q ₁₃ and Q ₁₄ change, the emitter currents of transistors Q ₃ and Q ₄ change, and their emitter resistances r _e change. Therefore, the voltages at terminals T ₂₁ and T ₂₂ -(V ₁ +V/2), -(V ₂ -V
/2) are voltages that are in opposite phases to each other and have a phase corresponding to the level of the control voltage.

Thus, according to the present invention, a balanced phase-shifted output can be obtained. And in that case,
When the emitter resistances r _e of the transistors Q ₃ and Q ₄ vary, distortion components, especially second harmonics _, are generated in the voltages V ₁ and V ₂ obtained at the emitters of the transistors Q 3 and Q ₄ . Since the voltages V ₁ and V ₂ occur in opposite phases to each other, even if they occur, they are differentially amplified by the transistors Q ₇ and Q ₈ and do not appear at the collectors of the transistors Q ₇ and Q ₈ . Therefore, since the output voltages -(V ₁ +V/2) and -(V ₂ -V/2) contain almost no distortion, the phase-shifted output can be obtained at a large level.

In addition, since it is a balanced phase-shifted output, signal processing to the next stage balanced modulation circuit is easy, and the IC
It is also suitable for Furthermore, since it is a differential configuration, the dynamic range can be increased.

In the above example, the phase-shifted output is obtained by voltage synthesis, but it is also possible to obtain the phase-shifted output by current synthesis.

Figure 5 shows an example of this.
The collector current of Q ₅ and the collector current of transistor Q ₈ are current-combined by resistor R ₅ and are converted into a voltage to provide a phase-shifted output voltage - to terminal T ₂₁ .
(V ₁ +V/2) is taken out, and similarly, a phase-shifted output voltage -(V ₂ -V/2) is taken out to the terminal T ₂₂ . Further, the voltage -V is taken out to the terminals _T11 and _T12 by the transistors _Q25 and _Q26 .

Note that in the above description, emitter resistors may be connected to the transistors Q ₁ and Q ₂ .

[Brief explanation of the drawing]

1 to 3 are diagrams for explaining this invention, and FIGS. 4 and 5 are connection diagrams of an example of this invention. 10 is a signal source, _T1 is a control terminal, and _T11 to _T22 are output terminals.

Claims (1)

[Claims] 1 A first variable resistance element, a capacitor, and a second
are connected in series with a variable resistance element, and input signals of mutually opposite phases are supplied to both ends of this series circuit, and a pair of input terminals of a differential amplifier are connected to both ends of the capacitor, respectively. 1 at the output end of
Each of the pair of resistors is connected, and the pair of output signals of the differential amplifier and a level signal of 1/2 of the input signal are added by the pair of resistors, and the output terminal of the pair of differential amplifiers is A phase shift circuit configured to obtain a pair of phase outputs having phases corresponding to the values of the first and second variable resistance elements.