JPS6117360B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an induction heating cooker.

Induction heating cookers rectify commercial alternating current power to create a pulsating current, or further smooth the pulsating current and convert it into direct current, and use this direct current to run an inverter circuit.
It oscillates at a high frequency of approximately 20 to 40 KHz, and the resulting high-frequency alternating current is applied to a work coil to generate a magnetic field. This magnetic field is then applied to a cooking pot made of ferrous metal placed close to the work coil. This is heated by induction.

Since this type of induction heating cooker does not use flame for heating, it is impossible to tell from the outside whether the cooking pot is in operation or not, and the cooking pot may be heated without being placed on the top plate, which is the pot-mounting base. Or, a problem arises in which a small load made of ferrous metal, such as a knife or fork, is placed on the top plate and heated without realizing that the heating operation is in progress.

In the former case, there is a risk of damage to electrical parts, as well as a waste of power consumption, and in the latter case, there is a risk of the user getting burnt by touching the heated knife, etc., which is a safety issue. Undesirable. To address this problem, a device has been proposed in which a magnet is placed on the underside of the top plate and the magnet detects when the pot is placed. has the disadvantage that it cannot be applied.

The present invention was made in view of these circumstances, and is intended to be used when an appropriate load is not placed, including a stainless steel pot that does not attract magnets, or when a knife,
When an unsuitable small load such as a fork is placed on the top plate, this is detected and the heating operation is stopped to protect the circuit components inside the device and make cooking safer.

Embodiments of the present invention will be described below with reference to the drawings. In Figure 1, 1 is a commercial AC power supply, Spw is a power switch, 2 is a rectifier circuit consisting of four diodes (not shown) connected in a bridge, CH is a chiyoke coil, and _C0 is rectified via a chiyoke coil CH. The capacitor connected to circuit 2 is a high-frequency bypass capacitor with a small capacity of about 10 μF, which has high impedance for commercial AC frequencies (50/60 Hz) and low impedance for high frequencies. Therefore, a pulsating current signal Vcc ₁ (FIG. 3) which oscillates between 0 and 140V is obtained at the connection point between the capacitor C ₀ and the choke coil CH. L is a work coil whose one end is connected to the positive side of the rectifier circuit 2 via a choke coil CH, CTR is a switching element such as a switching transistor, the collector is connected to the other end of the work coil L, and the emitter is connected to the load side of the rectifier circuit 2. In addition, a drive circuit 3 whose base will be described later
It is connected to the. As the switching transistor GTR, a large capacity giant transistor or a gate turn-off thyristor GTO used in this embodiment can be used. Further, the work coil L is wound in a spiral shape, and an insulating top plate 4 made of a ceramic plate or the like is arranged close to the work coil L. Further, an adjustment pan 5 made of ferrous metal is mounted on the top plate 4. placed. Therefore, the high frequency alternating magnetic field generated by the work coil L passes through the top plate 4 and is applied to the pot 5. _C1 is a resonant capacitor connected in parallel with the switching transistor GTR, and _D1 is a diode connected in antiparallel with the switching transistor GTR. Each of these parts constitutes an inverter circuit.

CT is a current transformer that is wound around the line between the work coil L and the diode _D1 and serves as a detection circuit for detecting damped vibration, and outputs x proportional to the input voltage to the output terminal X. Reference numeral 6 denotes a control power source to which AC power 1 is supplied via a power switch Spw, and outputs DC voltages Vcc ₂ , V _DD and pulsating current signal Vcc ₃ having predetermined values, respectively.

Here, the DC voltage Vcc ₂ is approximately 24V and is used as a power source for driving the drive circuit 3. In addition, the DC voltage V _DD is controlled by the constant voltage circuit 7 in the control power supply 6
It is a stable DC voltage with a value of 13V, and is used as a driving power source for the circuit described later. Furthermore, the pulsating current signal Vcc ₃ has an amplitude width of 0 to 40V, and the starting circuit 8
added to.

The starting circuit 8 receives the voltage V _DD as a driving power source and the pulsating current signal Vcc ₃ as a signal, and outputs a starting signal for starting the inverter circuit.

To explain the circuit 8, VR ₁ is a variable resistor whose one end is connected to a power supply V _DD and the other end is connected to one end of a capacitor C ₂ , and Q ₁ is a variable resistor whose anode is connected to a power supply V _DD and a variable resistor VR ₁ and a capacitor C An SCR in which _{a two-} junction potential is applied to the gate, and its cathode is grounded. R ₁ and C ₃ are a resistor and a capacitor inserted in parallel between the anode and cathode of SCR and Q ₁ to absorb inrush current and other nozzle that may occur when the power is turned on. NAND ₁ is SCR,
This is a NAND gate to which a signal A obtained from the anode potential of Q ₁ is obtained via a resistor R ₂ is applied to one end, and becomes conductive when the gate open signal A exceeds the threshold voltage Vth of this gate. Q ₂ is NAND gate NAND ₁
The output of the transistor is applied to its base via a capacitor C ₄ and a resistor R _3. Its collector is connected to the power supply V _DD via a resistor R ₄ , and its emitter is connected to a resistor.
Grounded via _R5 . _C5 is a capacitor connected to the collector side of transistor _Q2 ,
A pulse signal B is obtained as its output.

INV ₁ is connected to the collector of transistor Q ₂ and is an inverter that inverts the collector potential. D ₂ is a backflow prevention diode provided at the output end of inverter INV ₁ and outputs a starting pulse C.

Output signal D is a signal output from the collector of transistor Q ₂ and has substantially the same waveform as signal B.

9 is the output control circuit and _Q3 is the current transformer CT
A transistor to which _the signal _x from _the terminal
Connected to the input end of INV ₂ , its emitter is grounded. D ₃ is the base of transistor Q ₃
The diode INV ₃ connected _between the emitters and for half _- wave rectification of _the input signal D ₂
The activation signal C is applied to the cathode of the circuit.
C ₆ is a capacitor installed between the connection point between resistors R ₉ and R ₁₀ (hereinafter referred to as point Y) and the ground, INV ₄ is an inverter to which the output of inverter INV ₃ is input,
Together with the inverter INV ₃ , it constitutes a Schmitt circuit. _R11 is a resistor inserted between the input end of the inverter _INV3 and the output end of the inverter _INV4 , and is used to increase the switching speed of the inverter. C ₇ , R ₁₂ , D ₄ are capacitors, resistors,
and a diode connected between the output terminal of inverter INV ₄ and earth. The potential at the connection point of the capacitor C ₇ and the resistor R ₁₂ (hereinafter referred to as Z ₀ ) is input to the inverter INV ₅ via the resistor R ₁₃ , and the output of this inverter INV ₅ is input to the other inverter.
Added to INV ₆ . These two inverters
INV ₅ and INV ₆ constitute a Miyumitsu circuit.
_R14 is a resistor inserted between the input end of _INV5 and the output end of inverter _INV6 . The output of inverter INV ₆ is applied to drive circuit 3 via resistor R ₁₅ . Note that this drive circuit 3 includes the above-mentioned inverter.
The output signal from INV ₆ is amplified by a transistor or transformer (not shown) and applied to the base of the switching transistor GTR. When this startup signal is a positive signal, the switching transistor GTR is turned on. On the other hand, it is configured to turn off when there is a negative signal. The drive circuit 3 made up of such an amplifier circuit can be realized with a well-known circuit configuration as described above, so its details will be omitted.

10 is an output delay circuit, and _C7 is connected to the power supply V _DD at one end.
When a capacitor, Q ₄ is added, its base is connected to the other end of this capacitor C ₇ through a resistor R ₁₆ , and the collector of the transistor Q ₄ is connected to the Z ₀ point of a resistor R ₁₃ through a resistor R ₁₇ . , and the emitter is grounded. _D5 is a diode connected between the base and emitter of transistor _Q4 , and capacitor _C7
This is to discharge the charged charge. The significance and operation of this output delay circuit 10 will be described later.

Reference numeral 11 denotes an overload detection circuit that protects the device from damage to electrical components due to excessive input due to differences in the material of the pot 5 or accidental generation of rush current.

In the figure, INV ₇ is an inverter FF ₁ that inputs the signal x from the current transformer CT output end via resistor R ₁₆ .
is a flip-flop consisting of two NAND gates NAND ₂ and NAND _3. The output of the inverter INV ₇ is applied to one input of the NAND gate NAND ₂ , and one input of the other NAND gate NAND ₃ is connected to the collector of the transistor Q ₂ of the starting circuit 8. A potential signal is applied and reset. Q ₅ is flip-flop FF ₁
A transistor in which the output of the NAND gate NAND ₂ is input to its base through the resistor R ₁₉ , the collector is connected to the Z ₀ point of the resistor R ₁₃ through the resistor R ₂₀ , and the emitter is grounded through the resistor R ₂₁ . ing.

R ₂₂ and D ₉ are a resistor and a diode inserted in parallel between the input terminal of the inverter INV ₇ and the ground, which divide the current transformer CT output signal x together with the resistor R ₁₆ and perform half-wave rectification. .

12 is a no-load detection circuit that detects when the pot 5 placed on the top plate 4 is removed. One input terminal of the NAND gate NAND ₄ receives the signal A from the output terminal of the resistor R ₂ , and the other input terminal receives the detection output signal X of the current transformer CT, which is voltage-divided via the resistors R ₂₃ and R ₂₄ . be done. This divided voltage signal of the signal x is simultaneously connected to the clock input terminal CK of the counter CNT as a counting circuit.

ZD ₁ is a Zener diode connected in parallel with resistor R ₂₄ to protect NAND gate NAND ₄ .

13 is a load detection circuit that detects when the pot 5 is placed on the top plate 4;
Contains CNT. This counter CNT is known as a Johnson counter that has 10 output terminals and counts clock pulses and outputs a signal from each corresponding output terminal.

In this embodiment, the sixth output terminal _q6 of the above output terminals, that is, the terminal that outputs a signal when six clock pulses are counted, is used. Therefore, this counter CNT counts the pulses having a value equal to or greater than a certain value among the pulses of the signal x, and generates an output q ₆ when the number of pulses reaches six. This numerical value "6" serves as a criterion for the presence of a load, no load, or the presence of a load of small objects; when there are six or more, it is determined that there is no load, and when there are five or less, it is determined that there is a load. Note that the terminal CL of the counter CNT above
is a clear signal input terminal, to which a signal is applied from the starting circuit 8 and is cleared every half cycle of the AC signal. FF ₂ is a flip-flop consisting of NAND gates NAND _{5 and NAND 6 .}
A signal B is applied from the starting circuit 8 to one input terminal, and an output signal of the counter CNT is applied to one input terminal of the NAND gate NAND ₆ via an inverter INV ₈ . NAND gate NAND ₇ is SCR, Q ₁
The output J is obtained by using the signal A from the NAND gate NAND 5 and the output signal I of the NAND gate NAND ₅ as two inputs. FF ₃ is a flip-flop as an oscillation stop circuit consisting of NAND gates NAND ₈ and NAND ₉ .
The output signal K of NAND ₄ is input to one input terminal of NAND gate NAND ₃ , and the output signal J of NAND gate NAND ₇ is input to one input terminal of NAND gate NAND ₉ , and the signal L is input from the output of NAND gate NAND ₉ .
get. This signal L is a backflow prevention diode.
It is input to the input side Y point of inverter INV ₃ via D ₇ . R ₂₅ and D ₆ are the resistor and diode inserted between the output terminal of NAND gate NAND ₅ and the input terminal of NAND gate NAND _{7 .}
When the output K becomes L level, the NAND gate
The input side of NAND ₉ is set to L level to prevent both inputs of flip-flop FF ₃ from becoming L level. 14 is the aforementioned no-load detection circuit 1
2 and the load detection circuit 13, which includes a normally open switch _S0 and a resistor _R26 inserted between one input terminal of the NAND gate _NAND9 and the ground.

By operating this switch _S0 , the flip-flop
The output of FF ₃ is fixed at H (high) level, and the heating operation is performed regardless of the presence or absence of a load. This deactivation circuit 14 is used when it is desired to heat a small adjustable pan having a load comparable to that of small items.

Reference numeral 15 denotes a temperature output adjustment circuit, which has a temperature adjustment function to control the heating temperature of the cooking pot while the output is constant, and adjusts the output within a predetermined range (in this example, about 500W to about 500W).
It has an output adjustment function that can be adjusted within a range of 1350W). In this example, temperature control is divided into a low temperature range from 60°C to 100°C and a high temperature range from 160°C to 200°C, but this may be just one temperature range or three or more temperature ranges. You can also do that. Such a temperature adjustment function is effective when used for foods that have an optimal cooking temperature, such as tempura dishes. On the other hand, the output adjustment function adjusts the amount of energy supplied to the cooking pot, which is equivalent to the heat power in other cookers, by switching the output between 500W and 1350W. It is used when it is better to change the force, for example, when it is better to make the initial output "strong" and the later output "weak".
Also, when boiling water, you can boil it fastest by setting the output to "High".

The display of temperature adjustment or output adjustment is done by the output display circuit described later. When the temperature adjustment function is working, light emitting diodes LED ₁ to _{LED 5} are lit until the set temperature is reached. When reached, the light goes out. This tells you whether the set temperature has been reached. Also, if the output adjustment function is working, the desired light emitting diode will be adjusted according to the output.
LED ₁ to LED ₅ will light up.

Continuing the explanation of the configuration by returning to the figure, Th is a thermal element inserted between the repower source _VDD and the ground together with a capacitor _C9 , and for example, a negative characteristic thermistor is used. S ₁ to _{S 4} are three-point changeover switches whose sliding contact pieces move over the terminals, and each switch is configured to interlock with each other.

Here, switches S ₁ S ₂ are used for temperature adjustment and are used for switching heating temperature ranges, switch S ₃ is used for switching from temperature adjustment to output adjustment, and switch S ₄ is used for setting a reference level. Here, the terminals of switch _S1 are connected to the power supply V via resistors _R27 and _R28 , respectively.
The terminal is connected to _DD and grounded via resistor _R32 . The common terminal of the switch _S1 is connected to one end of the thermistor Th and the negative potential input end of the differential amplifier OP. The terminals of the switch _S2 are connected to the negative potential input terminal of the differential amplifier OP and one end of the thermistor Th via resistors _R29 and _R30 , respectively, and the terminals are at a vacant level. The common terminal of this switch _S2 is grounded via a variable resistor _VR2 , and is also connected to the terminal of the switch _S3 . The terminals of the switch _S3 are grounded through a common resistor _R31 , and the common terminal is connected to the _Z0 point through a resistor _R20 . The terminals of switch S ₄ are grounded through resistor R ₃₅ , both terminals are vacant,
The common terminal is also connected to the differential amplifier OP via resistor _R34 .
Connected to the positive potential input terminal of

A DC voltage V _DD is connected to this positive potential input terminal.
The voltage is divided by R ₃₅ and R ₃₆ and input as a reference voltage. Further, a capacitor C ₁₀ is inserted in parallel with the resistor R ₃₆ . OP is the above-mentioned differential amplifier, which outputs an H level signal when the signal input to the positive potential input terminal is larger than the signal input to the negative potential input terminal,
Conversely, when the negative potential input signal is greater than the positive potential input signal, an L level signal is output. This differential amplifier
The output of OP is applied to one input of NAND gate _NAND1 . Here, the specific configuration of each of the switches _S1 to _S4 will be explained based on FIG. 2. 1
Reference numeral 8 denotes a regulator operating surface, and 16 indicates a switching knob provided on this operating surface 18. By switching the switching knob 16 from the top to the bottom in three stages (indicated by arrows in the figure), the temperature can be adjusted in the upper two stages. , the output can be adjusted at the bottom. That is, in the upper row, switches S ₁ to _{S 4}
A terminal is set in the middle row, a terminal is set in the middle row, and a frost is set in the lower row. In this case, the terminal setting state is set to a low temperature heating range of 60°C to 100°C, the terminal setting state is set to a high temperature heating range of 160°C to 200°C, and the terminal setting state is set to an output adjustment range.

LED ₁ to LED ₅ are light emitting diodes that display output. For example, if we are currently in the terminal setting state, the reference potential applied to the positive potential input terminal of the differential amplifier OP is the resistor R ₃₅ connected to the terminal of the switch S ₄ .
is at a lower level due to parallel insertion of .

On the other hand, the comparison voltage applied to the negative potential input terminal is
R ₂₇ , R ₂₉ is determined by thermistor Th and variable resistance VR ₂ , and as the temperature rises, the thermistor Th
Since the resistance value of OP decreases, the comparison voltage reaches the reference voltage, changing the output of the differential amplifier OP to L level. Therefore, temperature control in the low temperature heating region is possible. When switching to the other terminal, the terminal of switch S ₄ is vacant, so the resistor R ₃₅ mentioned above
The parallel insertion of is cut off, changing the reference potential at the positive potential input terminal of the differential amplifier OP. Hence the resistance R ₂₈ ,
The comparison voltage determined by R ₃₀ , thermistor Th, and variable resistor VR ₂ operates in the same way as in the low temperature region, making heating possible in the temperature region. In each temperature range thus set, the slide knob 17 is used to further set an arbitrary temperature. This slide knob 17 controls the variable resistor VR ₂ , allowing linear temperature control. The setting state of the terminal is such that output adjustment is possible, and the details thereof will be described later, but it can be variably adjusted by controlling the variable resistor VR ₂ as described above.

Here, the following conditions are attached to the temperature adjustment switch _S1 and the output adjustment switch _S3 in terms of their functions. First, when switching between the terminals of switch _S1 , a configuration must be adopted in which the switching piece contacts the terminal after being separated from the terminal.
This is because if both terminals were to be connected when switching between them, the resistors R ₂₇ and R ₂₈ connected to each terminal would be connected in parallel, and the combined resistance with the thermistor Th would instantly decrease. This is because the negative potential input signal of the differential amplifier OP eventually rises and exceeds the reference voltage, changing its output to L level and stopping the heating operation. As such a switch, a well-known non-shorting switch is used.

Next, when switching the terminals of switch _S3 , a shorting type switch must be used, in which there is a period in which all three terminals are in contact during switching. This is because, for example, if a cut-off state occurs when switching from a terminal _to It is.

19 is an output display circuit, which is a current transformer.
The output signal X of the CT is rectified via a diode _D8 , and further smoothed by a capacitor _C11 before being input. ZD ₂ is a Zener diode to which this DC-exchanged current transformer CT signal is applied, and becomes conductive when the signal exceeds the Zener voltage. LED ₁ is a light emitting diode connected to the cathode of the Zener diode ZD ₂ via a resistor R ₃₇ ; LED ₂ , LED ₃ , LED ₄ , and LED ₅ are resistors R ₃₈ , R ₃₉ , R ₄₀ , R ₄₁ and Zener diodes, respectively.
These are light emitting diodes connected in parallel to the cathode side of the Zener diode ZD ₂ via ZD ₃ , ZD ₄ , ZD ₅ , and ZD _6, respectively. Here, the Zener voltages and resistance values of the Zener diodes ZD ₃ to _{ZD 6} and the resistors R ₃₈ to _{R 41} increase as they move toward the right in the figure. As a result, for example, when the current transformer CT output voltage signal X increases, the light emitting diode LED ₁ at the left end in the figure lights up sequentially in the right direction, and the level of the output is displayed. these,
Light emitting diodes LED ₁ to _{LED 5} are arranged on the operation surface 18 .

Next, the operation of the induction heating cooker having such a configuration will be explained.

(1) When normal heating operation is performed A pot 5 with an appropriate load is placed on the top plate 4. Also, the temperature output adjustment circuit 15
Assume that the switches S ₁ to _{S 4} are set to terminals by the switching knob 16. In addition, in this setting state, the temperature is in the low temperature heating range of 60 to 100°C, and the slide knob 17 further determines an arbitrary temperature, for example, 80°C, as described above. In this state, if the power switch SPW is turned on during the period T ₀ shown in _FIG .

During period T ₁ starting from 0V of this power supply Vcc ₃ , SCR, Q ₁ is turned on after 0V or a predetermined time t ₁ . The above time t ₁ is determined by the time constant of variable resistor VR ₁ and capacitor C ₂ and is approximately 1 msec.
Out. FIG. 3 shows the anode-cathode voltage signal A of this SCR, _Q1 .

Continuity of this SCR, Q ₁ occurs when the pulsating power supply Vcc ₃ is 0V.
This continues from ₁ hour after rising from t until t ₂ , when the voltage approaches 0V again. Such turning on and off of SCR and _Q1 is repeated according to the cycle of the pulsating current power supply _Vcc3 . The period of this power supply Vcc ₃ is 1/2 of the commercial AC signal, which is 10 msec (in the case of 50 Hz). When the above SCR, Q ₁ becomes conductive, the NAND gate
One input terminal of NAND ₁ changes from H level to L level. At this time, the other input of the NAND gate NAND ₁ is at the H level, so the output of the NAND gate NAND ₁ changes from the L level to the H level.

As mentioned above, the output signal of the differential amplifier OP of the temperature output adjustment circuit 15 is applied to the other inputs of the NAND gate NAND ₁ , and since the thermistor Th is at room temperature in the initial state of heating, its output becomes H level. There is.

Now, the output signal of the NAND gate NAND _1, which has changed to H level, is applied to the transistor Q ₂ via the capacitor C ₄ and the resistor R ₃ , and is connected to the above capacitor.
C ₄ is conductive for a period determined by the time constant of resistor R ₃ , and a signal D is obtained at the collector of transistor Q ₂ .
This signal D becomes the starting signal C which is inverted by the inverter INV ₁ , and the inverter of the output control circuit 9
Added to INV ₃ .

Due to this start signal C, the input of inverter INV ₃ becomes H level, and therefore the input of the next stage inverter
Output E of INV ₄ changes to H level. In addition, signal E
The waveform from signal G to signal G is a high frequency oscillation of 20 to 40 KHz, and since the time scale is much smaller than the waveform shown in FIG. 3, it is shown separately in FIG. 4.

Now, the signal E falls for a time determined by the time constant of the combined resistance between the capacitor _C7 and the grounding point _Z0 , and its output, ie, the input signal of the inverter _INV5 , becomes a pulse that gradually decreases from the rise as shown by waveform F. When this signal F is higher than the threshold voltage Vth of the inverter INV ₅ , the output G of the inverter INV ₆ becomes H level. This signal G is applied to the drive circuit 3 via the resistor _R15 , where it is amplified and turns on the switching transistor GTR. Due to the conduction of this transistor GTR, a load current iL begins to flow through the work coil L, and this current iL is detected by the current transformer CT, and a voltage signal x proportional to the input voltage to the load is obtained at its output terminal X. When this signal x rises to a certain value, this signal turns on transistor _Q3 and changes the input of inverter _INV2 to L level. Therefore the inverter
The output of INV ₂ becomes H level and the next stage inverter
Added to INV ₃ . Here, since the capacitor C ₆ and the inverters INV ₃ and INV ₄ form a delay circuit, the output of the inverter INV ₄ is generated with a slight time delay with respect to the input of the inverter INV ₃ . Note that the significance of the delay circuit will be described later. When the output of the inverter INV ₄ becomes H level, the input of the inverter INV ₅ becomes H level, and the output of the inverter INV ₆ also becomes H level. Also with capacitor C ₇
The charging time of _the capacitor _C7 is determined by the time constant determined by the combined resistance between the Z0 point and the ground, and when charging is completed, the voltage between the _Z0 point and the ground decreases. When this voltage becomes lower than the threshold voltage Vth of inverter INV ₅ , the inverter INV ₆ output G changes to L level, and the drive circuit 3
and turns off the switching transistor GTR.

This period is now shown as Ta in Figure 4. Thereafter, the energy charged in the work coil L during the period Ta begins to be discharged (period Tb), and this energy is charged into the resonant capacitor _C1 . After the charging of the capacitor C ₁ is completed, the charge of the capacitor C ₁ is discharged from the capacitor C ₁ through the work coil L, the capacitor C ₀ and back to the capacitor C ₁ during the period Tc that follows. At the same time, the work coil L is charged.

Subsequently, the charge charged in the work coil L is discharged to the work coil L, the capacitor _C0, and the diode.
D ₁ and the work coil L. (period Td).

Thus, one cycle of vibration caused by the activation signal C is completed. After that, when the current iL rises from zero in the positive direction, the current transformer CT signal x
is added to transistor _Q3 , turning it on. As a result, the input of the inverter INV ₂ changes to L level and the output changes to H level.

On the other hand, if the output of NAND gate NAND ₉ of flip-flop FF ₃ is at L level at this time, then
The input to the resistor _R10 is held at the L level by this L level signal. Therefore, even if the output of the inverter INV ₂ becomes H level as described above, the input of the next stage inverter INV ₃ remains at the L level and does not change, so the signal to the drive circuit 3 is not output and the transistor GTR remains off. Therefore, after the period Td, damped vibration occurs due to the work coil L and the resonant capacitor _C1 . This is shown in period T ₁ in FIGS. 4 and 5. This damped vibration rapidly weakens because a normal pot 5 is placed on the top plate 4. This damped oscillation is detected by the current transformer CT, and its output signal x is voltage-divided by resistors R ₂₃ and R ₂₄ and applied to the NAND gate NAND ₄ , and simultaneously input to the clock terminal CK of the counter CNT. Here, only pulses having a threshold voltage Vth or higher included in the signal x are counted, and in this case, the number of pulses is about two.

Therefore, the output _q6 remains at the L level, and the output H of the inverter _INV8 remains at the H level.
In addition, the NAND gate of flip-flop FF ₂
The input of NAND ₅ is a pulse signal B obtained from the collector of transistor Q ₂ through capacitor C ₅ .
is applied at the beginning of the period _T1 , so the output signal I of the NAND gate _NAND5 is at H level.

When the starting pulse C is generated at the subsequent machine interval _T2 , this starting signal C is sent to the output control circuit 9 as described above.
The signal is then applied to the drive circuit 3, and the transistor GTR is turned on to start oscillation. On the other hand, the output J of the NAND gate NAND ₇ changes to the L level when the activation pulse C is detected, and this signal J is input to the next stage NAND gate NAND ₉ , inverts this flip-flop FF ₃ , and outputs the L level of the NAND gate NAND ₉ . Change to H level. Therefore, when one cycle of oscillation ends with the above starting pulse C and the load current iL rises from zero, when a signal x appears at the current transformer CT terminal X,
This signal x turns on the transistor _Q3 , and sets the input of the inverter _INV2 to L level. As a result, the output of inverter INV ₂ becomes H level, and furthermore, the output of inverter INV ₃ , INV ₄ and INV ₅ ,
The H level signal G outputted via INV ₆ is applied to the drive circuit 3, turns on the switching transistor GTR, and the load current iL starts flowing. In this case, since the output L of the NAND gate NAND ₉ is at the H level, the input side of the inverter INV ₃ is held at the H level, and the signal x from the current transformer CT is not cut off here. In this way, self-excited oscillation continues, and this oscillation is caused by the pulsating current power supply.
This state continues until time t ₂ when Vcc ₁ decreases to near 0 V, the width gain decreases, and transistor GTR is turned on, as shown in periods T ₂ and T ₃ in FIGS. 4 and 5. Such oscillation is repeated every half cycle of the AC frequency, and within each cycle, high frequency oscillation of approximately 20 to 40 KHz is performed, and a high frequency alternating current of 20 to 40 KHz flows through the work coil L. As a result, a high frequency alternating magnetic field is applied to the pot 5 disposed close to the work coil L, and induction heating is performed. When heating is started in this way, the temperature of the pot 5 is detected by the thermistor Th provided on the back side of the top plate 4, and when the temperature reaches the predetermined temperature of 80°C by adjusting the slide knob 17, the differential amplifier OP is turned on. The negative potential input terminal input signal becomes larger than the positive potential input terminal input signal, therefore the output of the differential amplifier OP is H
The level changes from the level to the L level, the NAND gate NAND ₁ in the starting circuit 8 is closed, and the generation of the starting pulse C is stopped. As a result, the starting pulse is no longer sent to the output control circuit 9, so the inverter circuit stops oscillating and the heating operation is stopped. After that, when the temperature of the pot 5 decreases and the resistance value of thermistor Th increases,
The negative potential signal input terminal signal of the differential amplifier OP falls and becomes smaller than the positive potential input terminal signal again, and the output of the differential amplifier OP changes to H level and opens the NAND gate NAND ₁ and starts sending out the starting pulse C again. Then, inverter oscillation starts and heating operation resumes. In this way, the heating temperature of the pot is set at 80.
kept at ℃.

Next, the significance of the aforementioned delay circuit will be explained.

This delay circuit consists of a capacitor _C6 , an inverter
The output E of the inverter INV ₄ composed of INV ₃ and INV ₄ is delayed by a short time (approximately 2 μsec) with respect to the input of the inverter INV ₃ . When adjusting the output by normal frequency control, for example, if the resonance frequency is adjusted on the low frequency side (strong output), the resistance R (= 2πfoL + 1/2πfoC) on the circuit will increase as the frequency increases (weak output). The charging capacity of capacitor _C1 becomes smaller and the discharge ends earlier. Therefore, the transistor GTR turns on before the voltage between the collector and emitter of the switching transistor GTR falls to 0V, causing heat generation and even more.

Waveform M in Figure 6 shows the operating state when the resonant frequency is adjusted to the low frequency side and in the low frequency region, that is, when the output is large, and shows the load current iL and the collector-emitter voltage VcE of the switching transistor GTR.
indicates a normal relationship. On the other hand, the same waveform N
As mentioned above, indicates the case where the adjustment is made on the low frequency side and operation is performed in the high frequency region, that is, in a state where the output is small. The transistor GTR becomes conductive before the collector-emitter voltage VcE of the switching transistor GTR falls to 0V. I understand.

To prevent this, the output E of inverter INV ₄ is slightly delayed and the switching transistor
The on-time of GTR is delayed slightly, and the transistor GTR is turned on after the collector-emitter voltage VcE completely reaches 0V.

Next, the output control operation will be explained. When controlling the output, switch the switches S ₁ to _{S 4} of the temperature/output adjustment circuit 15 to the terminals, and then
Adjust VR ₂ . In this way, the combined resistance between Z ₀ point and ground (this combined resistance consists of variable resistance VR ₂ , resistance R ₁₂ ,
(composed of R ₂₀ ) changes, the time constant with capacitor C ₇ changes, and the time required for the input signal F of inverter INV ₅ to fall from its rise to the threshold voltage Vth
Ta can be changed. Therefore, the conduction time of the switching transistor GTR can be changed, and the amount of electromagnetic energy charged in the work coil L can be changed in accordance with this change. In other words, if this time Ta is set short,
The electromagnetic energy supplied to the work coil L decreases, and the output decreases. At this time, the oscillation frequency increases. On the other hand, if the above-mentioned time Ta is set longer, the electromagnetic energy supplied to the work coil L increases and the output increases. At this time, the oscillation frequency decreases. This output level is displayed by the output display circuit 19. That is, as the output gradually increases, the output signal X of the current transformer CT also increases in proportion to this. Since this voltage signal X is an alternating current signal, it is rectified and smoothed by the diode _D8 and the capacitor _C1 , and is applied to the Zener diode _ZD2 at the next stage. When the rectified and smoothed signal exceeds the Zener voltage of the Zener diode ZD ₂ , current first flows through the Zener diode ZD ₂ to the resistor ₃₇ and the light emitting diode LED ₁ , lighting the light emitting diode LED ₁ .
When the output voltage further increases, it exceeds the Zener voltage of the Zener diode ZD ₃ in the next stage, energizing the resistor R ₃₈ and the light emitting diode LED ₂ , and the second light emitting diode LED ₂ lights up. In this way, as the output increases, the third light emitting diode LED ₃ , 4
The _4th light emitting diode LED lights up,
In the state of maximum output "strong", all the light emitting diodes LED ₁ , LED ₂ ...LED ₅ light up.

When the temperature/output adjustment circuit 15 is in the output control state, the switches S ₁ to _{S 4} are set as terminals, so the negative potential input terminal of the differential amplifier OP is connected via the switch S ₁ and the resistor R ₃₂ . Grounded.

Therefore, the output of the differential amplifier OP is always at the H level, and it is considered that the heating temperature will rise indefinitely if this continues. However, in this state, the pot 5
As the temperature of the heated thermistor Th increases, its resistance value decreases, and the voltage at the common terminal point of the switch _S1 divided by the thermistor Th, the switch _S1 , and the resistor _R32 increases. Therefore, if this voltage becomes larger than the input signal to the positive potential input terminal of the differential amplifier OP, the differential amplifier OP
Since the output changes to L level and closes the NAND gate NAND ₁ , the generation of the starting pulse C is stopped and the inverter oscillation is stopped. Therefore, the heating temperature does not rise indefinitely, and if the upper heating temperature limit is appropriately set by appropriately selecting the resistor _R32 , it can serve as a safety device.

(2) When an overloaded pot is placed In induction heating cookers, the material and size of the overloaded pot is generally limited, such as an iron-based magnetic pot, but in actual use. Sometimes, a pot unsuitable for heating is placed on the top plate 4.

For example, when a pot made of 18-8 stainless steel (contains 18% chromium and 8% nickel) labeled SUS304 is heated, an excessive amount of current flows due to its low resistance. There is a risk that this excessive current will trip the breaker or destroy the circuit elements. In the present invention, the safety of the apparatus is improved by detecting the occurrence of such an excessive current that causes inappropriate load heating, or the occurrence of a sudden current due to other accidental causes. That is,
If an excessive current exceeding the normal load current flows through the work coil L, this excessive current is converted to a voltage x across the current transformer CT, and this voltage x is applied to the voltage dividing resistor in the overload detection circuit 11.
The voltage divided by R ₁₈ and R ₂₂ and applied to the resistor R ₂₂ is input to the inverter INV ₇ . Normally, this divided voltage does not exceed the threshold of inverter INV ₇ , but when an excessive current occurs,
Since the current transformer CT detection voltage x increases in proportion to this, it becomes equal to or higher than the threshold voltage of the inverter _INV7 . This allows the inverter to
The INV ₇ output changes to L level, and the output of NAND gate NAND ₂ of flip-flop FF ₁ changes from L level to H level. Therefore, this H level signal makes the transistor _Q5 conductive, and a new resistor _R21 is added in parallel to the combined resistance between the _Z0 point and the ground, and the combined resistance value decreases. As a result, the time constant of this combined resistance and capacitor _C7 becomes small, and the switching transistor
The conduction time Ta of GTR becomes shorter and the output decreases. Figure 7 shows the waveform of the voltage x across the current transformer CT, and the AC frequency signal is 20 to 40K.
The waveform includes a Hz alternating voltage signal. Here, the waveform x indicates the case where the overload detection circuit 11 is not added, and the waveform x' indicates the case where the overload detection circuit 11 is operated. ~40KHz
It oscillates repeatedly at the frequency of

At time ta shown in waveform x', overload detection circuit 1
1 is activated, raising the oscillation frequency and lowering the output, it can be seen that the voltage x' suddenly drops.

This prevents the input current to the load from becoming excessive and protects each circuit element. In particular, this voltage x′ and the switching transistor
Since the collector-emitter voltage VcE of GTR has a proportional relationship, it is significant to be able to protect this transistor GTR. Note that since the collector potential signal D of the transistor Q ₂ of the starting circuit 8 is input to the input terminal of the NAND gate NAND ₃ of the flip-flop FF ₁ , the initial half wave of the AC frequency signal (time tb of waveform x' in FIG. 7) At this point, flip-flop _FF1 is reset and transistor _Q5 is turned off. Therefore,
Thereafter, the overload detection circuit 11 stops again and normal oscillation drive is performed, and if the pot 5 is overloaded, the current transformer CT detects an excessive current, and the overload detection circuit 11 works and reduces the output. This operation is performed every half wave of the AC frequency, and when the pot is replaced and the load changes to an appropriate value, the overload detection circuit 11 does not operate and normal heating operation continues.

(3) If the pot is removed from the top plate during the heating operation, if the proper pot 5 is placed on the top plate 4 and the heating operation is in progress, removing the pot 5 will cause the inverter circuit to oscillate. will continue as is, and power will be wasted. Therefore, when such a situation occurs, it is desirable to stop the oscillation of the inverter circuit. In this example, such a treatment was applied. In other words, if the pot 5 is removed during the heating operation, the damped oscillation due to resonance between the work coil L and the resonant capacitor _C1 that constitute the inverter circuit becomes longer, and the oscillation continues even around 0V, which is a half wave of the commercial frequency signal. Become. This is shown in waveform x in FIG. In the figure, P ₁ is when a normal load is applied.
P ₂ indicates each oscillation state in a no-load state; oscillation stops when there is a load, and oscillation continues when the load is removed. These differences are detected by the no-load detection circuit 12. To explain this operation based on FIGS. 4 and 5, when the pot 5 is removed during the period Ti, P ₂ of the waveform x
As shown in the dot, the oscillation of the inverter circuit continues. Therefore, in the following period Ti+1, the output K of the NAND gate NAND ₄ changes to the L level during the period in which the signal A exceeds the threshold voltage Vth of this gate, as the oscillation passes through. This L level signal causes flip-flop _FF3 to be inverted, and the output L of NAND gate _NAND9 changes to L level. Since the L level of this signal L is added to the Y point and holds the inverter INV ₃ input at the L level,
The self-oscillation signal X applied via the transistor _Q3 and the inverter _INV2 is cut off here, and no self-oscillation occurs. Therefore period
At Ti+1, damped oscillations occur only due to the first starting pulse. This damped vibration is relatively large since there is no load, and the number of pulses input to the counter CNT is six or more.
When the number of input pulses reaches six, the counter CNT emits an H level signal at the output _q6 , and this signal is inverted by the inverter _INV8 to become a signal H.
Input to NAND gate NAND ₆ . As a result, the output signal I of the NAND gate NAND ₅ becomes H level only during the period when six pulses are emitted.
On the other hand, since the above-mentioned signal I and signal A are applied to the input of the NAND gate NAND ₇ , its output waveform remains at the H level as shown at J, and the output L of the next stage NAND gate NAND ₉ does not change. Therefore, self-oscillation is not performed and no heating operation is performed. In this manner, when the pot 5 is removed from the top plate 4, the oscillation automatically stops and the heating operation is no longer performed.

Next, a case will be described in which a suitable pot 5 is placed in the apparatus in such a state. Period shown in Figure 5
When the pot 5 is placed at Tj, only the damped vibration due to the starting pulse C still occurs during the period Tj+1. However, since this damped vibration is reduced by the presence of the pot, the number of pulses counted by the counter CNT is only about two. hence the counter
No H level signal is output from the CNT, and the output I of the NAND gate NAND ₅ is held in the state of being changed to H level by the signal B. and the following period Tj
When pulse signal A is generated at the beginning of +2, the output of NAND gate NAND ₇ changes to L level, inverts flip-flop FF ₃ , and outputs the NAND gate.
Change the output L of NAND ₉ to H level.

As a result, the inhibition of self-excited oscillation of the output control circuit 9 is canceled, and normal oscillation operation is performed.

Now, when the cooker is in the heating operation state and the object placed on the top plate 4 is an inappropriate small load such as a knife or fork, it is necessary to detect this and detect the heating operation. It is.

In the present invention, this is the load detection circuit 13 described above.
This has been achieved by In other words, when the above-mentioned small load is placed, the number of pulses exceeding a certain value generated by damped vibration is 6 or more, so the oscillation operation stops in the same manner as when the pot is removed as described above. . Therefore, even if the above-mentioned small load is placed on the top plate 4 with the power turned on, it will not be heated, and there is a risk of getting burned by accidentally touching a heated knife, etc. do not have.

Next, the output delay circuit 10 will be explained. When the power switch Spw is turned on, the flip-flop
The output L of the NAND gate NAND ₉ of FF ₃ is at either H level or L level. Signal L is H
level, the inverter circuit starts in an oscillating state, and if the load is suitable, it will oscillate normally, and if there is no load or a small load, the no-load detection circuit 12 will operate and the input of the NAND gate NAND ₈ will be low.
Level signal added hence NAND gate NAND ₉
The output changes to L level, inhibiting the oscillation of the inverter circuit. On the other hand, when the NAND gate NAND ₉ output signal L is at the L level, the state starts from the same state as when no load or a small load is detected, and if an appropriate load is placed, the load detection circuit 13 operates and the NAND gate NAND ₉ An L level signal is input, its output becomes H level, and the inverter circuit starts oscillating.

However, in the embodiment of the present invention in which the output is controlled by frequency, when the output is set to the "strong" position, oscillation does not occur near 0V of the commercial AC frequency signal when a small load is placed, and the It was confirmed that the condition was as if an appropriate load had been applied. Therefore, in this state, the oscillation does not stop and there is a risk that the small load will be heated. The output delay circuit 10 described above solves this problem. In other words, in the cooker of this embodiment, since the resonant frequency is matched when the output is "strong", the capacitance due to the work coil L and the load and the resistance of the resonance capacitor _C1 are small even when the output is "strong"; It is maximum when it is "weak". In other words, when the output is "strong" the load is heavy, and when the output is "weak" the load is the lightest. Then, when the load becomes lighter, the oscillation continues at around 0V of the AC frequency signal, similar to the oscillation state when there is no load, and if this oscillation is detected by the no-load detection circuit 12, it is possible to determine whether a small object is loaded. .

Next, its operation will be explained. Power switch now
Capacitor C ₇ that turns on Spw is charged by the time constant of resistor R ₁₆ and the base-emitter resistance of transistor Q ₄ , and _a voltage higher than a predetermined value is applied between the base and emitter of transistor Q ₄ . Transistor _Q4 becomes conductive only for an initial fixed period of time (approximately 1 sec). Due to the conduction of this transistor Q ₄ , a resistance R ₁₆ is created between the Z ₀ point and the ground.
are newly connected in parallel, and the combined resistance during this time decreases. In other words, the oscillation frequency of the inverter circuit increases, and the output becomes "weak". In this state of output "weak", oscillation will continue around 0V of the AC frequency signal, or the output will be "strong".
The small object load that was not detected in the above case will be reliably detected.

In the induction heating cooker of the present invention, as described above, when the pot is removed while the pot is heating, the no-load detection circuit is activated and immediately stops the oscillation of the inverter circuit and stops the heating operation. Wasteful consumption of is prevented. In addition, after this no-load detection circuit operates, the load status is checked every half cycle of the commercial AC frequency, so when a suitable pot is placed, it automatically returns to normal heating and maintains an efficient cooker. realizable. Furthermore, after no-load detection is performed, if the object placed on the top plate is an inappropriate small load such as a knife or fork, the load detection circuit detects this small load and suppresses the oscillation of the inverter circuit. Since it is held in a stopped state, there is no risk that these small items will be heated, and therefore, there is no danger of getting burned by touching a heated knife, etc., and the stability of the cooking device can be improved.

Similar to no-load detection, this small object load detection is performed periodically every half cycle of the commercial AC frequency, so if it is removed and a suitable pot is placed, the heating operation will immediately begin, and during this time no external switch operation is required. It is not necessary at all and has the effect of being easy to operate.

Furthermore, the present invention is characterized in that the damped vibration that occurs when a starting signal is supplied to the inverter circuit changes depending on the load condition, that is, it is quickly damped when the load is appropriate, while it is slowly damped when there is a small load or no load. Focusing on damping, damped vibration signals that are above a preset constant voltage value are detected and counted within a certain period of time, and this counted value is greater than or equal to a reference value or less than that. Since it detects whether the load is appropriate or not, it is possible to accurately and quickly judge whether the load is small or not, and the ability to follow changes in load is extremely good. The safety of the cooker and the effect of contributing to the protection of electrical components within the cooker are improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the induction heating cooker of the present invention, Fig. 2 is a perspective view of the cooker of the embodiment, and Figs. 3 to 7 are signal waveform diagrams for explaining the operation of the embodiment. be. 3... Drive circuit, 8... Starting circuit, 9... Output control circuit, 10... Output delay circuit, 11... Overload detection circuit, 12... No load detection circuit, 13...
Load detection circuit, 15...Temperature/output adjustment circuit, 1
9...Output display circuit.

Claims (1)

[Claims] 1. In an induction heating cooker including an inverter circuit formed by connecting a parallel circuit consisting of a switching element, a resonant capacitor, and a diode in series with an induction heating coil, a starting signal is applied to the switching element to cause damped vibration in the inverter circuit. a starting circuit, a detection circuit that detects the damped vibration, a counting circuit that counts the number of pulses of the damped vibration detected by the detection circuit that are equal to or higher than a certain voltage value, and a count value of the counting circuit that exceeds a reference value. an oscillation stop circuit that sends out a signal to stop oscillation of the inverter circuit when the inverter circuit stops oscillating.