JPS6113354B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an induction heating cooker.

Induction heating cookers rectify commercial alternating current power into pulsating current, or further smooth the pulsating current and convert it into direct current, and use this direct current to run an inverter circuit.
It oscillates at a high frequency of about 20 to 40 KHz, and the resulting high-frequency alternating current is applied to a work coil to generate a magnetic field. This magnetic field is applied to a cooking pot made of ferrous metal placed close to the work coil. This is heated by induction.

Since this type of induction heating cooker does not use flame for heating, it is impossible to tell from the outside whether the cooking pot is in operation or not, and the cooking pot may be heated without being placed on the top plate, which is the pot-mounting base. Or, a small load made of ferrous metal such as a knife or fork may be placed on the top plate and heated without realizing that the heating operation is in progress.

In the former case, there is a risk of damage to electrical parts, as well as a waste of power consumption, and in the latter case, there is a risk of the user getting burnt by touching the heated knife, etc., which is a safety issue. Undesirable. To address this problem, a device has been proposed in which a magnet is placed on the underside of the top plate and the magnet detects when the pot is placed. has the disadvantage that it cannot be applied.

As another input detection method, it is also known to detect a small object load or no load by detecting an input current and determining its magnitude. This method oscillates the inverter at appropriate intervals and detects the input current flowing at this time, but the inverter must oscillate for at least one cycle, so the detection timing is set at about 2 to 5 seconds. There must be a relatively long time interval between the two. This is because, for example, if detection is performed at a short timing of seconds or less, the interval between oscillation cycles for detection becomes short, and there is a risk that the small object load may be heated. On the other hand, depending on the type of cooking, the pot may be frequently raised and lowered from the top plate, and in such a case, the above-mentioned detection method would cause the heating operation to stop for approximately 2 to 5 seconds each time it is raised or lowered. Therefore, such cooking is virtually impossible.

The present invention was made in view of these circumstances, and is intended to be used when an appropriate load is not placed, including a stainless steel pot that does not attract magnets, or when a knife,
When an unsuitable small load such as a fork is placed on the top plate, this is detected and the heating operation is stopped to protect the circuit components inside the device and make cooking safer.

Furthermore, the present invention includes a load detection circuit that detects when a cooking pot serving as a load is placed on the top plate and enables oscillation of the high frequency inverter, and a load detection circuit that detects when the cooking pot is removed from the top plate. The system is equipped with a no-load detection circuit that inhibits oscillation of the high-frequency inverter, and operates at a timing of approximately 10 msec to improve load detection response.

Embodiments of the present invention will be described below with reference to the drawings. In Figure 1, 1 is a commercial AC power supply, SPW is a power switch, 2 is a rectifier circuit formed by connecting four diodes (not shown) in a bridge, CH is a chiyoke coil, and CO is a rectification circuit via a chiyoke coil CH. A 10μ capacitor connected to 2, which has high impedance for commercial AC frequencies (50/60Hz) and low impedance for high frequencies.
A high frequency bypass capacitor with a small capacitance of about F is used. Therefore, a pulsating current signal V _CC1 (FIG. 3) which oscillates between 0 and 140 V is obtained at the connection point between the capacitor CO and the choke coil CH. L is a work coil whose one end is connected to the positive electrode side of the rectifier circuit 2 via a choke coil CH, and GTR is a switching element such as a switching transistor.
The collector is connected to the other end of the work coil L, the emitter is connected to the negative electrode side of the rectifier circuit 2, and the base is connected to a drive circuit 3, which will be described later. As the switching transistor GTR, a large capacity giant transistor or a gate turn-off thyristor GTO used in this embodiment can be used. Further, the work coil L is spirally wound,
An insulating top plate 4 such as a ceramic plate is arranged close to this, and this top plate 4
A cooking pot 5 made of ferrous metal is placed on top.
Therefore, the high frequency alternating magnetic field generated by the work coil L passes through the top plate 4 and is applied to the pot 5. C1 is switching transistor GTR
D1 is a diode connected in anti-parallel with the switching transistor GTR. Each of these parts constitutes an inverter circuit. CT is work coil L
A current transformer is wound on the line between the diode D1 and the output terminal X, and a voltage x proportional to the input voltage
Output. 6 is the control power supply, the power switch
An AC power supply 1 is supplied through the SPW, and outputs DC voltages V _CC2 and V _DD and a pulsating current signal V _CC3 having predetermined values, respectively. Here, the DC voltage V _CC2 is
It has approximately 24V and is used as a power source for driving the drive circuit 3. Further, the DC voltage V _DD is made into a stable DC voltage having a value of about 13V by a constant voltage circuit 7 in the control power supply 6, and is used as a power source for driving each circuit to be described later. Furthermore, the pulsating current signal V _CC3 is 0 to 40V
, and is applied to the starting circuit 8.

The starting circuit 8 receives the voltage V _DD as a driving power source and the pulsating current signal V _CC3 as a signal, and outputs a starting signal for starting the inverter circuit.

To explain the circuit 8, VR1 is a variable resistor whose one end is connected to a power supply V _{DD and} the other end is connected to one end of a capacitor C2. An SCR applied to the gate and grounded to its cathode. R1 and C3 are a resistor and a capacitor inserted in parallel between the anode and cathode of the SCR (Q1), and are used to absorb noise such as rush current that may occur when the power is turned on.
For NAND1, the anode potential of SCR (Q1) is resistance R
This is a NAND gate to which a signal A obtained through a gate 2 is applied to one end, and becomes conductive when the gate open signal A exceeds the threshold voltage Vth of this gate. For Q2, the output of the NAND gate NAND1 is the capacitor C4,
The transistor is connected to its base via a resistor R3, and its collector is connected to the power supply V _DD via a resistor R4.
Furthermore, the emitter is grounded via a resistor R5. C5 is a capacitor connected to the collector side of the transistor Q2, and obtains the pulse signal B as its output.

INV1 is an inverter connected to the collector of the transistor Q2 and inverts the collector potential, and D2 is a backflow prevention diode provided at the output end of the inverter INV1, which outputs a starting pulse C. Output signal D is a signal output from the collector of transistor Q2, and has substantially the same waveform as signal B.

9 is the output control circuit and Q3 is the current transformer.
A transistor to which the signal _x from the terminal There is. D3 is a diode connected between the base and emitter of transistor Q3 for half-wave rectification of the input signal x, and INV3 is the inverter INV.
2 is applied via resistors R9 and R10, and its input terminal is connected to the cathode of the diode D2 of the starting circuit 8, and the starting signal C is applied thereto. C6 is a capacitor provided between the connection point between resistors R9 and R10 (hereinafter referred to as point Y) and the ground, and INV4 is an inverter to which the output of the inverter INV3 is input, and together with the inverter INV3 constitutes a Schmitt circuit. R11 is a resistor inserted between the input terminal of the inverter INV3 and the output terminal of the inverter INV4, and serves to increase the switching speed of the inverter. C7, R1
2, D4 is a capacitor, a resistor, and a diode, which are connected between the output terminal of the inverter INV4 and the ground. Above capacitor C7, resistor R1
The potential of the two connection point (hereinafter referred to as Z0) is input to the inverter INV5 via the resistor R13, and the output of this inverter INV5 is input to the other inverter INV6.
added to. These two inverters INV5,
INV6 constitutes a Schmitt circuit. R14
is a resistor inserted between the input terminal of INV5 and the output terminal of inverter INV6. The output of inverter INV6 is applied to drive circuit 3 via resistor R15. Note that this drive circuit 3 includes the above-mentioned inverter.
The output signal from INV6 is amplified by a transistor or transformer (not shown), and this is applied to the base of the switching transistor GTR. When this startup signal is a positive signal, the switching transistor GTR is turned on and the other transistor is turned on. It is configured to turn off when there is a negative signal. The drive circuit 3 made up of such an amplifier circuit can be realized with a well-known circuit configuration as described above, so its details will be omitted.

10 is an output delay circuit, and C7 is connected to the power supply V _DD at one end.
The capacitor Q4 to which Q4 is added is a transistor whose base is connected to the other end of this capacitor C7 via a resistor R16.
The collector is connected to the Z0 point of the resistor R13 via the resistor R17, and the emitter is grounded. D5
is a diode connected between the base and emitter of the transistor Q4, which discharges the charge stored in the capacitor C7. The significance and operation of this output delay circuit 10 will be described later.

Reference numeral 11 denotes an overload detection circuit that protects the device from damage to electrical components due to excessive input due to differences in the material of the pot 5 or accidental generation of rush current.

In the figure, INV7 is an inverter that inputs the signal x from the current transformer CT output end via resistor R18.
FF1 has two NAND gates NAND2, NAND3
The output of the inverter INV7 is applied to one input of the NAND gate NAND2, and the collector potential signal D of the transistor Q2 of the starting circuit 8 is applied to one input of the other NAND gate NAND3 to reset it. Q5 is a transistor whose base receives the output of the NAND gate NAND2 of the flip-flop FF1 via a resistor R19. Its collector is connected to the Z0 point of the resistor R13 via a resistor R20, and its emitter is connected to the resistor R21.
is grounded through. R22 and D9 are a resistor and a diode inserted in parallel between the input terminal of the inverter INV7 and the ground, and divide the current transformer CT output signal x together with the resistor R18.
It performs half-wave rectification.

12 is a no-load detection circuit that detects when the pot 5 placed on the top plate 4 is removed. The signal A is input from the output terminal of the resistor R2 to one input terminal of the NAND gate NAND4, and the detection output signal x of the current transformer CT, which is voltage-divided via resistors R23 and R24, is input to the other input terminal. The divided voltage signal of this signal x is simultaneously
Connected to CNT clock input terminal CK.

ZD1 is a Zener diode connected in parallel with resistor R24 to protect the NAND gate NAND4.

13 is a load detection circuit that detects when the pot 5 is placed on the top plate 4;
Contains CNT. This counter CNT is known as a Johnson counter that has 10 output terminals and counts clock pulses and outputs a signal from each corresponding output terminal.

In this embodiment, the sixth output terminal q6 of the above output terminals, that is, the terminal that outputs a signal when six clock pulses are counted, is used. Therefore, this counter CNT counts pulses having a value equal to or greater than a certain value among the pulses of the signal x, and generates an output q6 when the number of pulses reaches six. This numerical value "6" serves as a criterion for the presence of a load, no load, or the presence of a load of small objects; when there are six or more, it is determined that there is no load, and when there are five or less, it is determined that there is a load. Note that the terminal CL of the counter CNT is a clear signal input terminal, and the signal A is applied from the starting circuit 8 to be cleared every half cycle of the AC signal. FF2 is NAND gate NAND5,
In a flip-flop consisting of a NAND6, a signal B from a starting circuit 8 is applied to one input terminal of the NAND gate NAND5, and an output signal of a counter CNT is applied to one input terminal of the NAND gate NAND6 via an inverter INV8. nand gate
NAND7 has two inputs, signal A from SCR (Q1) and output signal I of NAND gate NAND5, and obtains output J. FF3 is NAND Gate NAND8,
A flip-flop consisting of NAND9 converts the output signal K of the NAND gate NAND4 into a NAND gate.
At one input end of NAND3, also NAND gate NAND
The output signals J of 7 are respectively input to one input terminal of the NAND gate NAND9, and the signal L is obtained from the output of the NAND gate NAND9. This signal L is input to the input side Y point of the inverter INV3 via the backflow prevention diode D7. R25 and D6 are resistors and diodes inserted between the output terminal of the NAND gate NAND5 and the input terminal of the NAND gate NAND7. Both inputs are L
This is to prevent the level from becoming too high. 14 is an operation cancellation circuit that stops the functions of the above-mentioned no-load detection circuit 12 and load detection circuit 13;
A normally open switch SO and a resistor R26 are inserted between one input terminal of the NAND 9 and the ground.

By operating this switch SO, the output of flip-flop FF3 is fixed at H (high) level, and the heating operation is performed regardless of the presence or absence of a load.
This deactivation circuit 14 is used when it is desired to heat a small cooking pot that has a load comparable to the load of small items.

Reference numeral 15 denotes a temperature output adjustment circuit, which has a temperature adjustment function that controls the heating temperature of the cooking pot with a constant output state, and a temperature output adjustment circuit that controls the output within a predetermined range (in this example, approximately 500W to approximately 500W).
It has an output adjustment function that can be adjusted within a range of 1350W). In this example, temperature control is divided into a low temperature range from 60°C to 100°C and a high temperature range from 160°C to 200°C, but this may be just one temperature range or three or more temperature ranges. You can also do that. Such a temperature adjustment function is effective when used for foods that have an optimal cooking temperature, such as tempura dishes. On the other hand, the output adjustment function adjusts the amount of energy supplied to the cooking pot, which is equivalent to the heat power in other cookers, by switching the output between 500W and 1350W. This is used when it is better to change the output, for example, when it is better to set the initial output to "strong" and the subsequent output to "weak."
Also, if you want to boil water, you can boil it fastest by setting the output to "High". In addition, the display of temperature adjustment or output adjustment is done by the output display circuit described later, and when the temperature adjustment function is working, the light emitting diodes LED1 to LED are displayed until the set temperature is reached.
5 is lit and turns off when the set temperature is reached. This tells you whether the set temperature has been reached. Also, if the output adjustment function is working,
Depending on the output, select the desired light emitting diode LED1~
LED5 will turn on.

Continuing the explanation of the configuration by returning to the figure, Th is a thermal element inserted together with a capacitor C9 between the power supply V _DD and the ground, and for example, a negative characteristic thermistor is used. S1 to S4 are three-contact changeover switches in which sliding contact pieces move over the terminals, and each switch is configured to interlock with each other.

Here, switches S1 and S2 are used for temperature adjustment and are used to change the heating temperature range, switch S3 is used to change from temperature control to output control, and switch S4 is used to set a reference level. Here, the terminals of switch S1 are resistors R27 and R27, respectively.
It is connected to the power supply V _DD via R28, and its terminal is grounded via resistor R32. The common terminal of switch S1 is one end of thermistor Th and the differential amplifier.
Connected to the negative potential input terminal of OP. The terminals of switch S2 are resistors R29 and R3, respectively.
0 to the negative potential input terminal of the differential amplifier OP and one end of the thermistor Th, and the terminal is at an empty level. A common terminal of this switch S2 is grounded via a variable resistor VR2, and is also connected to a terminal of the switch S3. Switch S
Terminal No. 3 is grounded via a common resistor R31, and the common terminal is connected to point Z0 via a resistor R20. The terminal of the switch S4 is grounded via a resistor R33, both terminals are at an empty level, and the common terminal is connected via a resistor R34 to the positive potential input terminal of the differential amplifier OP.

The DC voltage V _DD is divided by resistors R35 and R36 and input as a reference voltage to this positive potential input terminal. Also, the capacitor C1 is connected to the resistor R36.
0 is inserted in parallel. OP is the differential amplifier mentioned above, which outputs an H level signal when the signal input to the positive potential input terminal is greater than the signal input to the negative potential input terminal, and conversely, the negative potential input signal is greater than the positive potential input signal. outputs an L level signal. The output of this differential amplifier OP is the NAND gate NAND1
is applied to one input terminal of Here, the specific configuration of each of the switches S1 to S4 will be explained based on FIG. 2. Reference numeral 18 indicates a cooking device operating surface, and 16 indicates a switching knob provided on the operating surface 18. By switching the switching knob 16 from the top to the bottom in three stages (indicated by arrows in the figure), the temperature can be adjusted in the upper two stages. , the output can be adjusted at the bottom. That is, the terminals of the switches S1 to S4 are set in the upper stage, the terminals in the middle stage, and the terminals in the lower stage. In this case, the terminal settings are in the low temperature heating range of 60℃ to 100℃, and the terminal settings are 160℃.
High temperature heating range from ℃ to 200℃, terminal setting state is set to output adjustment area.

LED1 to LED5 are light emitting diodes that display output. For example, if the terminal is currently in the terminal setting state, the reference potential applied to the positive potential input terminal of the differential amplifier OP is at a low level due to the parallel insertion of the resistor R33 connected to the terminal of the switch S4.

On the other hand, the comparison voltage applied to the negative potential input terminal is connected to resistors R27, R29, thermistor Th, and variable resistor.
Since it is determined by VR2 and the resistance value of the thermistor Th decreases as the temperature rises, the comparison voltage reaches the reference voltage and changes the output of the differential amplifier OP to L level. Therefore, temperature control in the low temperature heating region is possible. When switching to the other terminal, since the terminal of switch S4 is vacant, the above-mentioned parallel insertion of resistor R33 is interrupted, and the reference potential of the positive potential input terminal of differential amplifier OP is changed.
Therefore, the comparison voltage determined by the resistors R28, R30, thermistor Th, and variable resistor VR2 allows the device to operate in the same manner as in the low temperature region and to heat in the high temperature region. In each temperature range thus set, the slide knob 17 is used to further set an arbitrary temperature. This slide knob 17 controls the variable resistor VR2, allowing linear temperature control. The terminal setting state allows the output to be adjusted, and the details will be described later, but the output can be variably adjusted by controlling the variable resistor VR2 as described above.

Here, the following conditions are attached to the temperature adjustment switch S1 and the output adjustment switch S3 in terms of their functions. First, when switching between the terminals of the switch S1, a configuration must be adopted in which the switching piece comes into contact with the terminal after it is once separated from the terminal. This is because, if both terminals are connected when switching between terminals, each terminal,
The resistors R27 and R28 connected to the thermistor Th are connected in parallel, and the combined resistance with the thermistor Th decreases instantaneously, so that the negative potential input signal of the differential amplifier OP rises and exceeds the reference voltage. This is because the output is changed to L level and the heating operation is stopped. As such a switch, a well-known non-shorting switch is used.

Next, when switching the terminals of switch S3, a shorting type switch must be used in which there is a period in which all three terminals are in contact during switching. This is because, for example, if a cut-off state occurs when switching from a terminal to be.

19 is an output display circuit, which is a current transformer.
The output signal x of the CT is rectified via a diode D8, and further smoothed by a capacitor C11 before being input. ZD2 is a Zener diode to which this DC-exchanged current transformer CT signal is applied, and becomes conductive when the signal exceeds the Zener voltage. LED1 is a light emitting diode connected to the cathode of the Zener diode ZD2 through a resistor R37, LED2, LED3, LED
4. LED5 is resistor R38, R39, R respectively
40, R41 and Zener diode ZD3,
These are light emitting diodes connected in parallel to the cathode side of the Zener diode ZD2 via ZD4, ZD5, and ZD6. Here, the Zener voltages and resistance values of the Zener diodes ZD3 to ZD6 and the resistors R38 to R41 increase as they move toward the right in the figure. As a result, for example, if the current transformer CT output voltage signal x increases,
The light emitting diode LED1 on the left side of the figure is lit up sequentially toward the right, and its output level is displayed. These light emitting diodes LED1 to LED5 are arranged on the operation surface 18.

Next, the operation of the induction heating cooker having such a configuration will be explained.

(1) When normal heating operation is performed.

A pot 5 with an appropriate load is placed on the top plate 4.
will be installed. It is also assumed that in the temperature output adjustment circuit 15, the switches S1 to S4 are set to terminals by the switching knob 16. In addition, in this setting state, the temperature is in the low temperature heating range of 60 to 100℃, and the slide knob 17 can be used to further adjust the temperature to an arbitrary temperature, for example, 80℃.
As mentioned above, the temperature is determined at ℃. In this state, if the power switch SPW is turned on during the period T0 shown in _FIG .

During a period T1 of this voltage _Vcc3 starting from 0V, the SCR ( _Q1 ) is turned on after a predetermined time t1 from 0V. Note that the above time t ₁ is the variable resistor VR1
It is determined by the time constant of capacitor C2 and is about 1 m.
sec. FIG. 3 shows the anode-cathode voltage signal A of such SCR (Q1).

The conduction of this SCR (Q1) is caused by the pulsating power supply V _cc3 .
This continues from t ₁ hour after rising from 0V until time t ₂ when it approaches 0V again. In this way, the SCR (Q1) is turned on and off in accordance with the cycle of the pulsating power supply V _CC3 . The period of this power supply V _CC3 is 1/2 of the commercial AC signal, which is 10 msec (in the case of 50 Hz). When the SCR (Q1) becomes conductive, one input terminal of the NAND gate NAND1 changes from H level to L level. At this time, the other input of NAND gate NAND1 is at H level, so NAND gate NAND1
The output changes from L level to H level. As mentioned above, the output signal of the differential amplifier OP of the temperature output adjustment circuit 15 is applied to the other inputs of the NAND gate NAND1, and in the initial state of heating, the thermistor
Since Th is at room temperature, its output is at H level.

Now, the output signal of the NAND gate NAND1 which has changed to H level is applied to the transistor Q2 via the capacitor C4 and the resistor R3, and is conducted for a period determined by the time constant of the capacitor C4 and resistor R3.
A signal D is obtained at the collector of transistor Q2. This signal D is inverted by an inverter INV1 to become a starting signal C, which is applied to an inverter INV3 in the output control circuit 9.

Due to this start signal C, the input of inverter INV3 becomes H level, and therefore the input of the next stage inverter
The output E of INV4 changes to H level. In addition, signal E
The waveform from signal G to signal G is a high frequency oscillation of 20 to 40 KHz, and since the time scale is much smaller than the waveform shown in FIG. 3, it is shown separately in FIG. 4.

Now, the signal E falls for a time determined by the time constant of the combined resistance between the capacitor C7 and the grounding point Z0, and its output, that is, the input signal of the inverter INV5, becomes a pulse that gradually decreases from the rise as shown by waveform F. When this signal F is higher than the threshold voltage Vth of inverter INV5, the output G of inverter INV6 is high.
level. This signal G is applied to the drive circuit 3 via the resistor R15, where it is amplified and turns on the switching transistor GTR. Due to the conduction of this transistor GTR, the work coil L
A load current iL begins to flow, this current iL is detected by a current transformer CT, and a voltage signal x proportional to the input voltage to the load is obtained at its output terminal X. When this signal x rises to a certain value, this signal turns on transistor Q3 and changes the input of inverter INV2 to L level. Therefore, the output of the inverter INV2 becomes H level and is applied to the next stage inverter INV3. Here, since the capacitor C6 and the inverters INV3 and INV4 form a delay circuit, the output of the inverter INV4 is generated with a slight time delay with respect to the input of the inverter INV3. Note that the significance of the delay circuit will be described later. When the output of the inverter INV4 becomes H level, the input of the inverter INV5 becomes H level, and the output of the inverter INV6 also becomes H level. Further, the charging time of the capacitor C7 is determined by a time constant determined by the capacitor C7 and the combined resistance between the Z0 point and the ground, and when charging is completed, the voltage between the Z0 point and the ground decreases. When this voltage becomes lower than the threshold voltage Vth of inverter INV5, inverter INV6 output G
changes to L level, stopping the drive circuit 3 and turning off the switching transistor GTR. This period is now shown as Ta in Figure 4. Thereafter, the energy charged in the work coil L during the period Ta begins to be discharged (period Tb), and this energy is charged into the resonant capacitor C1. Capacitor C
1, the charge in the capacitor C1 is discharged from the capacitor C1 through the work coil L, the capacitor C0, and then back to the capacitor C1 during the period Tc, and at the same time, the work coil L is charged. be done. Subsequently, the electric charge charged in the work coil L is discharged through a path consisting of the work coil L, the capacitor C0 diode D1, and the work coil L (period Td).

Thus, one cycle of vibration caused by the activation signal C is completed. After that, when the current iL rises from zero in the positive direction, the current transformer CT signal x
is applied to transistor Q3, turning it on. As a result, the input of the inverter INV2 changes to L level and the output changes to H level.

On the other hand, if the output of the NAND gate NAND9 of the flip-flop FF3 is at the L level at this time, the input to the resistor R10 is held at the L level by this L level signal. Therefore, even if the output of the inverter INV2 becomes H level as described above, the input of the next stage inverter INV3 remains at the L level, and therefore no signal is output to the drive circuit 3 and the transistor GTR Remains off. Therefore, after the period Td, damped vibration occurs due to the work coil L and the resonant capacitor C1. This is the period T ₁ in Figures 4 and 5.
Shown below. This damped vibration rapidly weakens because a normal pot 5 is placed on the top plate 4. This damped vibration is detected by the current transformer CT, and its output signal x is generated by the resistors R23 and R24.
It is divided into voltages and applied to the NAND gate NAND4, and simultaneously input to the clock terminal CK of the counter CNT. Here, the threshold voltage included in the above signal x
Only pulses equal to or higher than Vth are counted, and in this case the number of pulses is about two. Yotsute output q6
remains at L level, and the output H of inverter INV8 remains at H level and does not change. Note that the input of the NAND gate NAND5 of the flip-flop FF2 is connected from the collector of the transistor Q2 to the capacitor C5.
Since the pulse signal B obtained through the period T1 is applied at the beginning of the period _T1 , the output signal I of the NAND gate NAND5 is at H level.

When the starting pulse C is generated in the following period _T2 , this starting signal C is output to the output control circuit 9 as described above.
The signal is then applied to the drive circuit 3, and the transistor GTR is turned on to start oscillation. On the other hand, with the generation of the activation pulse C, the output J of the NAND gate NAND7 changes to L level during this time, and this signal J is input to the next stage NAND gate NAND9, inverts this flip-flop FF3, and changes the output L of NAND gate NAND9 to H level. . Therefore, when one cycle of oscillation is completed by the starting pulse C and the load current iL rises from zero, when a signal x appears at the current transformer CT terminal X, the transistor Q3 is turned on by this signal x. The input of inverter INV2 is set to L level. As a result, the output of inverter INV2 becomes H level, and inverters INV3, INV4 and
H level signal G output via INV5 and INV6
is added to drive circuit 3 and becomes a switching transistor.
GTR becomes conductive and load current iL begins to flow. In this case, the output L of the NAND gate NAND9 is at the H level, so the input side of the inverter INV3 is held at the H level, and the current transformer
The signal x from the CT is not blocked here. In this way, self-sustained oscillation continues, and this oscillation continues until time _t2 when the pulsating current power supply V _CC1 drops to around 0 V, the amplification factor decreases, and the transistor GTR is turned off. This state is illustrated in Figure 4 and Period shown in Figure 5
Shown in T ₂ and T ₃ . This oscillation is repeated every half cycle of the AC frequency, and within each cycle, high frequency oscillation of about 20 to 40 KHz is performed, and the work coil L has a frequency of about 20 to 40 KHz.
A high frequency alternating current of 40KHz flows. As a result, a high frequency alternating magnetic field is applied to the pot 5 disposed close to the work coil L, and induction heating is performed. When heating is started in this way, the temperature of the pot 5 is detected by the thermistor Th provided on the back side of the top plate 4, and when the temperature reaches the predetermined temperature of 80°C by adjusting the slide knob 17, the differential amplifier OP is turned on. The negative potential input terminal input signal becomes larger than the positive potential input terminal input signal. hence the differential amplifier
The output of OP changes from H level to L level, closes the NAND gate NAND1 in the starting circuit 8, and stops generating the starting pulse C. As a result, the starting pulse is no longer sent to the output control circuit 9, so the inverter circuit stops oscillating and the heating operation is stopped. After that, when the temperature of the pot 5 decreases and the resistance value of the thermistor Th increases, the negative potential signal input terminal signal of the differential amplifier OP decreases and becomes smaller than the positive potential signal input terminal signal again, and the output of the differential amplifier OP becomes When the level changes to H level, the NAND gate NAND1 is opened, and the sending of the starting pulse C is started again, inverter oscillation is started, and the heating operation is restarted. In this way, the heating temperature of the pot 5 is maintained at the set temperature of 80°C.

Next, the significance of the aforementioned delay circuit will be explained.

This delay circuit consists of capacitor C6, inverter
It is configured by INV3 and INV4, and delays the output E of the inverter INV4 by a short time (about 2 μsec) with respect to the input of the inverter INV3. When adjusting the output by normal frequency control, for example, if the resonance frequency is adjusted on the low frequency side (strong output), the resistance R (= 2πoL + 1/2πoC) on the circuit will increase as the frequency increases (weak output). The charging capacity of the capacitor C1 becomes smaller and the discharge ends quickly. Therefore switching transistor GTR
The transistor GTR turns on before the voltage between the collector and emitter of the device falls to 0V, causing heat generation and even damage.

Waveform M in Figure 6 shows the operating state when the resonant frequency is adjusted to the low frequency side and in the low frequency region, that is, when the output is large, and shows the load current iL and the collector-emitter voltage VCE of the switching transistor GTR.
indicates a normal relationship. On the other hand, the same waveform N
As mentioned above, indicates the case where the adjustment is made on the low frequency side and the transistor is operated in the high frequency region, that is, in a low output state, and the transistor GTR is conductive before the collector-emitter voltage VCE of the switching transistor GTR falls to 0V. I understand that.

To prevent this, the output E of inverter INV4 is slightly delayed and the switching transistor
The on-time of GTR is slightly delayed, and the transistor GTR is turned on after the collector-emitter voltage VCE reaches completely 0V.

Next, the output control operation will be explained. When performing output control, the switches S1 to S4 of the temperature and output adjustment circuit 15 are switched to terminals, and the variable resistor VR2 is further adjusted. In this way, the combined resistance between the Z0 point and the ground (this combined resistance is composed of the variable resistor VR2 and the resistors R12 and R20) changes, the time constant with the capacitor C7 changes, and the inverter
Threshold voltage Vth from when input signal F of INV5 rises
You can change the time Ta to decrease up to. Therefore, the conduction time of the switching transistor GTR can be changed, and the amount of electromagnetic energy charged in the work coil L can be changed in accordance with this change. That is, when this time Ta is set short, the electromagnetic energy supplied to the work coil L becomes smaller and the output decreases. At this time, the oscillation frequency increases. On the other hand, the above time Ta
When is set longer, the electromagnetic energy supplied to the work coil L increases and the output increases. At this time, the oscillation frequency decreases. This output level is displayed by the output display circuit 19. That is, as the output gradually increases, the output signal x of the current transformer CT also increases in proportion to this. Since this voltage signal x is an alternating current signal, it is rectified and smoothed by the diode D8 and the capacitor C1, and is applied to the next stage Zener diode ZD2. When the rectified and smoothed signal exceeds the Zener voltage of Zener diode ZD2, it first passes through resistor R
37 and the light emitting diode LED1, a current flows through the light emitting diode LED1 to light up the light emitting diode LED1. When the output voltage further increases, it exceeds the Zener voltage of the Zener diode ZD3 in the next stage, and the resistor R38 is energized to the light emitting diode LED2, which lights up the second light emitting diode LED2. In this way,
3rd light emitting diode LED as output increases
The third and fourth light emitting diodes LED4 are lit up, and when the maximum output is "strong", all the light emitting diodes LED1, LED2...LED5 are lit up.

When the temperature/output adjustment circuit 15 is in the output control state, the switches S1 to S4 are set as terminals, so the negative potential input terminal of the differential amplifier OP is grounded via the switch S1 and the resistor R32. .

Therefore, the output of the differential amplifier OP is always at the H level, and it is considered that the heating temperature will rise indefinitely if this continues. However, in this state, the pot 5
As the thermistor Th is heated and the temperature of the thermistor Th increases, its resistance value decreases, and the switch S divided by the thermistor Th, switch S1, and resistor R32
The voltage at the common terminal point of 1 increases. Therefore, if this voltage becomes larger than the input signal to the positive potential input terminal of the differential amplifier OP, this differential amplifier
OP output changes to L level, NAND gate NAND
1 is closed, the generation of the starting pulse C is stopped, and the inverter oscillation is stopped. Therefore, the heating temperature does not rise indefinitely, and the resistance R32
If the heating upper limit temperature is appropriately set by appropriately selecting , it can serve as a safety device.

(2) If an overloaded pot is placed, generally for induction heating cookers, the type and size of the loaded pot is limited, such as iron-based magnetic pots, but the actual use In this case, a pot unsuitable for heating may be placed on the top plate 4.

For example, when a pot made of 18-8 stainless steel (contains 18% chromium and 8% nickel) labeled SuS304 is heated, an excessive amount of current flows due to its low resistance. There is a risk that this excessive current will trip the breaker or destroy the circuit elements. In the present invention, the safety of the apparatus is improved by detecting the occurrence of excessive current due to inappropriate load heating or the occurrence of inrush current due to other accidental causes. That is, if an excessive current exceeding the normal load current flows through the work coil L, this excessive current is converted to a voltage x on both sides of the current transformer CT, and this voltage x is applied to the voltage dividing resistor in the overload detection circuit 11. The voltage divided by R18 and R22 and applied to resistor R22 is applied to inverter INV7.
is input. Normally, this divided voltage does not exceed the threshold of inverter INV7, but when an overcurrent occurs, the current transformer CT detection voltage x increases in proportion to this, so the threshold voltage of inverter INV7 That's all. This results in
The output of the inverter INV7 changes to the L level, and the output of the NAND gate NAND2 of the flip-flop FF1 changes from the L level to the H level. Therefore, this H level signal makes transistor Q5 conductive and Z0
A new resistor R21 is added in parallel to the point-to-ground combined resistance, and the combined resistance value decreases. As a result, the time constant of this combined resistance and capacitor C7 becomes small, and the switching transistor
The conduction time Ta of GTR becomes shorter and the output decreases. FIG. 7 shows the waveform of the voltage x across the current transformer CT, which is a waveform in which an alternating voltage signal of 20 to 40 KHz is included in the alternating frequency signal. Here the waveform x
If the above-mentioned overload detection circuit 11 is not added,
The waveform x' shows the case where the overload detection circuit 11 is operated, and oscillates repeatedly at a frequency of about 20 to 40 KHz within a half cycle of the commercial AC frequency indicated by a period T. It can be seen that at time ta shown in the waveform x', the overload detection circuit 11 operates, increases the oscillation frequency and lowers the output, and the voltage x' suddenly drops.

This prevents the input current to the load from becoming excessive and protects each circuit element. In particular, since this voltage x' and the collector-emitter voltage V _CE of the switching transistor GTR are in a proportional relationship, it is significant that this transistor GTR can be protected. Note that a startup circuit 8 is connected to the input terminal of the NAND gate NAND3 of the flip-flop FF1.
Since the collector potential signal D of the transistor Q2 is inputted, this flip-flop FF is input at the beginning of the AC frequency signal half wave (time tb of waveform
1 is reset and transistor Q5 is turned off. Therefore, the overload detection circuit 11 is stopped again after that, normal oscillation drive is performed, and if the pot 5 is overloaded, the current transformer CT
An excessive current is detected at , and the overload detection circuit 11 operates in the same manner as described above to reduce the output. This operation is performed every half wave of the AC frequency, and when the pot is replaced and the load changes to an appropriate value, the overload detection circuit 11 does not operate and normal heating operation continues.

(3) If the pot is removed from the top plate during the heating operation, when the proper pot 5 is placed on the top plate 4 and the heating operation is in progress, if the pot 5 is removed, the oscillation of the inverter will stop. If this continues, power will be wasted. Therefore, when such a situation occurs, it is desirable to stop the oscillation of the inverter. In this example, such a treatment was applied. That is, if the pot 5 is removed during the heating operation, the damped vibration due to resonance between the work coil L and the resonant capacitor C1 that constitute the inverter becomes longer, and the oscillation continues even at around 0V, which is a half wave of the commercial frequency signal. This is shown in Figure 5 as the waveform x
Shown below. In the figure, P1 indicates the oscillation state when a normal load is applied, and P2 indicates the oscillation state in a no-load state. When there is a load, the oscillation stops, and when the load is removed, the oscillation continues. These differences are detected by the no-load detection circuit 12. To explain its operation based on Figures 4 and 5, the period
When the pot 5 is removed at _T1 , the oscillation of the inverter continues as shown at point P2 of the waveform x.
Therefore, in the following period Ti+1, NAND gate NAND
The output K of 4 is that the signal A is the threshold voltage of this gate.
The above oscillation passes during the period when Vth or more, and L
change to the level. This L level signal causes flip-flop FF3 to be inverted, and the output L of NAND gate NAND9 changes to L level. The L level of this signal L is added to the Y point and drives the inverter INV3 input to L.
Since the level is maintained, the self-oscillation signal x applied via the transistor Q3 and the inverter INV2 is cut off here, and no self-oscillation occurs. Therefore, during period Ti+1, damped oscillations occur only due to the first starting pulse. This damped vibration is relatively large since there is no load, and the number of pulses input to the counter CNT is six or more. Counter CNT has 6 input pulses.
When the signal reaches the high level, an H level signal is generated at the output q6, and this signal is inverted by the inverter INV8 and becomes the H level signal.
and is input to the NAND gate NAND6. As a result, the output signal I of the NAND gate NAND5 is 6
It is at H level only during the period when the pulse is emitted. On the other hand, since the above-mentioned signal I and signal A are applied to the input of the NAND gate NAND7, its output waveform remains at the H level as shown in J.
The output L of the next stage NAND gate NAND9 does not change. Therefore, self-oscillation is not performed and no heating operation is performed. In this manner, when the pot 5 is removed from the top plate 4, the oscillation automatically stops and the heating operation is no longer performed.

Next, a case will be described in which a proper pot 5 is placed in the apparatus in such a state. Period shown in Figure 5
When pot 5 is placed at Tj, the following period Tj+1
In this case, only the damped vibration due to the starting pulse C still occurs. However, since this damped vibration is reduced by the presence of the pot, the number of pulses counted by the counter CNT is only about two. Therefore, an H level signal is not outputted from the counter CNT, and the output I of the NAND gate NAND5 is maintained at the H level changed by the signal B. and the period that lasts
When the pulse signal A is generated at the beginning of Tj+2, the output J of the NAND gate NAND7 changes to the L level, inverting the flip-flop FF3 and changing the output L of the NAND gate NAND9 to the H level. As a result, the inhibition of self-oscillation of the output control circuit 9 is canceled,
Normal oscillation operation is performed.

Now, if the cooker is in the heating operation state and the object placed on the top plate 4 is an inappropriate small load, such as a knife or fork, it is necessary to detect this and stop the heating operation. be.

In the present invention, this is the load detection circuit 13 described above.
This has been achieved by In other words, when the above-mentioned small load is placed, the number of pulses exceeding a certain value generated by damped vibration is 6 or more, so the oscillation operation stops in the same manner as when the pot is removed as described above. . Therefore, even if the above-mentioned small load is placed on the top plate 4 with the power turned on, it will not be heated, and there is a risk of getting burned by accidentally touching a heated knife, etc. do not have.

The relationship between the no-load detection circuit 12 and the load detection circuit 13 will be explained next. As shown in Figure 8, the cooking pot 5
When the cooking pot 5 and the top plate 4 are placed on the top plate 4, when the distance between the cooking pot 5 and the top plate 4 becomes d ₁ mm, the load detection circuit 12 is activated and the high frequency inverter starts oscillating. When the cooking pot 5 is removed from the top plate 4, the no-load detection circuit 13 is activated to stop the oscillation of the high-frequency inverter when the cooking pot 5 is separated from the top plate 4 by d ₂ mm. And now suppose d ₁ ≧
Suppose there is a relationship d ₂ , and the cooking pot 5 distances d ₁ and d ₂
If the no-load detection circuit 1 is located between
2 determines that there is no pot and stops the oscillation of the high frequency inverter, while the load detection circuit 13 determines that there is a pot and works to cancel the prohibition of oscillation. FIG. 10 shows such a state P3
The no-load detection circuit 12 operates to inhibit self-oscillation of the inverter, and only a starting pulse is given to the inverter. However, the damped vibration caused by this starting pulse becomes small due to the presence of the pot, and the number of pulses counted by the counter CNT becomes 6 or less. Therefore, at time P4, it is determined that there is a pot, and self-oscillation is normally executed in the next oscillation cycle.
In this way, the inverter oscillates every cycle, and heating operation is performed at half the normal output.

In this embodiment, in order to prevent such a phenomenon from occurring, the working distances of both detection circuits 12 and 13 are set so that d ₁ <d ₂ . Figure 11 shows the oscillation state when the pot is removed at P5, and the distance d ₁ and
If the pot is located between d _{and 2} , no-load detection circuit 1
2 operates (determined that there is no pot), and the load detection circuit 13 does not operate (determines that there is no pot), so the oscillation of the inverter has stopped. The above d ₁ is set within a range of about 5 mm to 10 mm, and d ₂ is set within a range of about 7 mm to 12 mm, and when d ₁ =5 mm, d ₂ =7 mm.

The working distance _d1 of the load detection circuit 13 is determined by the counter
It can be adjusted by changing the number of CNT output pulses (6 in this example). The working distance _d2 of the no-load detection circuit 12 can be adjusted by changing the values of resistors R23 and R24. FIG. 12 shows the waveforms of the two inputs A, x, and x' of the NAND gate NAND4.
The waveform x shows the waveform when the cooking pot 5 is separated from the top plate 4 and the distance d ₂ is up to about 5 mm, and the waveform X' shows the waveform when d ₂ =7 mm. In the signals x and x', Vref is a NAND gate
This is the reference potential at which NAND4 operates. signal x,
As shown in x′, as the distance d ₂ increases, the potential at the signal valley tends to increase.
In this embodiment, by adjusting the resistors R23 and R24, when d ₂ =7 mm, the potential of the signal x' reaches the reference potential Vref at the time when the starting pulse A is generated. That is, when d ₂ =7 mm, the NAND gate NAND4 generates an L level pulse to the output signal K and acts to stop the oscillation of the inverter.

Next, the output delay circuit 10 will be explained. When the power switch SPW is turned on, the output L of the NAND gate NAND9 of flip-flop FF3 becomes H.
Either level or L level. Signal L
is at H level, the inverter starts in an oscillating state, and if the load is suitable, it will oscillate normally, and if there is no load or a small load, the no-load detection circuit 12 will operate and the input of the NAND gate NAND8 will be low.
Level signal is added therefore NAND gate NAND9
The output changes to L level, inhibiting the oscillation of the inverter. On the other hand, when the NAND gate NAND9 output signal L is at L level, the state starts from the same state as when no load or a small load is detected, and if an appropriate load is placed, the load detection circuit 13 operates and the NAND gate NAND9 is at L level. A signal is input, and its output becomes H level and the inverter starts oscillating.

However, in the case of this embodiment in which the output is controlled by frequency, when the output is set to the "strong" position, oscillation does not occur near 0V of the commercial AC frequency signal when a small load is placed, and the signal is not suitable. It was confirmed that the condition was as if a load had been placed on it. Therefore, in this state, the oscillation does not stop and there is a risk that the small load will be heated. The output delay circuit 10 described above solves this problem. In other words, in the cooker of this embodiment, the resonant frequency is output as “strong”.
Since the capacitance due to the work coil L, the load, and the resistance of the resonance capacitor C1 are the lowest when the output is "strong," on the other hand, when the output is "weak,"
It is maximum when . In other words, when the output is "strong" the load is heavy, and when the output is "weak" the load is the lightest. Then, when the load becomes lighter, the oscillation continues at around 0V of the AC frequency signal, similar to the oscillation state when there is no load, and if this oscillation is detected by the no-load detection circuit 12, it is possible to identify the load of a small object. .

Next, its operation will be explained. Power switch now
When SPW is turned on, capacitor C7 and resistor R1
6 and the time constant of the base-emitter resistance of transistor Q4, capacitor C7 is charged,
Since a voltage higher than a predetermined value is applied between the base and emitter of transistor Q4, it will last for an initial period of time (approximately
1 sec), transistor Q4 becomes conductive.
Due to this conduction of the transistor Q4, a resistor R16 is newly connected in parallel to the resistor between the Z0 point and the ground, and the combined resistance during this time decreases. In other words, the oscillation frequency of the inverter increases and the output becomes "weak".
This results in a state of . In this state of "weak" output, oscillation continues near 0V of the AC frequency signal, so small loads that are not detected when the output is "strong" are reliably detected.

In the induction heating cooker of the present invention, as described above, when the pot is removed while the pot is heating, the no-load detection circuit is activated and immediately stops the oscillation of the inverter and stops the heating operation. Wasteful consumption is prevented. In addition, after this no-load detection circuit operates, the load status is checked every half cycle of the commercial AC frequency, so when a suitable pot is placed, it automatically returns to normal heating and maintains an efficient cooker. realizable. Furthermore, after no-load detection is performed, if the object placed on the top plate is an inappropriate small load such as a knife or fork, the load detection circuit detects this small load and stops the oscillation of the inverter. Since these small items are kept in the same state, there is no risk of them being heated, and therefore there is no risk of getting burned by touching a heated knife or the like, and the safety of the cooker can be improved. Similar to no-load detection, this small object load detection is performed periodically every half cycle of the commercial AC frequency, so if it is removed and a suitable pot is placed, the heating operation will immediately begin, and during this time no external switch operation is required. It is not necessary at all and has the effect of being easy to operate.

Furthermore, the load detection circuit only generates damped vibration due to the activation pulse when the load is detected, and the period is extremely short, so there is no risk of the small load being heated by this, and that is why the
It can be said that load detection timing of around msec has become possible. Due to such quick response, cooking that requires frequent raising and lowering of the pot, such as cooking in a frying pan, can be carried out without any problems. Furthermore, according to the present invention, since the working distances d ₁ and d ₂ of the no-load detection circuit and the load detection circuit are set in the relationship d ₁ < d ₂ , depending on the distance from the top plate of the pot,
Intermittent oscillation caused by the no-load detection circuit determining that there is no pot and the load detection circuit simultaneously determining that there is a pot can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the induction heating cooker of the present invention, Fig. 2 is a perspective view of the cooker of the embodiment, and Figs. 3 to 7 are signal waveform diagrams for explaining the operation of the embodiment. 8 and 9 are cross-sectional views for explaining the operation of the no-load detection circuit and the load detection circuit,
10 to 12 are signal waveform diagrams of the same example. 3... Drive circuit, 8... Starting circuit, 9... Output control circuit, 10... Output delay circuit, 11... Overload detection circuit, 12... No load detection circuit, 13...
Load detection circuit, 15...Temperature/output adjustment circuit, 1
9...Output display circuit.

Claims (1)

[Claims] 1. In an induction heating cooker that has a work coil and a high-frequency inverter that supplies a high-frequency alternating current to the work coil, when a load consisting of a cooking pot is placed on the pot mounting table, this is detected and the oscillation of the high-frequency inverter is activated. and a no-load detection means that detects when the load is removed from the pot holder and prohibits oscillation of the high-frequency inverter, and the load/pot mount allows the load detection means to operate. The sensitivity of each of the above-mentioned detection means is adjusted so that the relationship between the distance d ₁ between the two and the distance d ₂ between the load and the pot mounting table at which the no-load detection means can operate becomes d ₁ < d ₂ . induction heating cooker.