JPS6046797B2 - induction heating cooker - Google Patents

Description

[Detailed description of the invention] The present invention relates to an induction heating cooker.

J Induction heating cookers rectify commercial AC power to create a pulsating current, or further smooth the pulsating current and convert it into DC, and use this DC power to run an inverter circuit at approximately 20 to 40 KH.
The resulting high-frequency alternating current is applied to a work coil to generate a magnetic field, and this magnetic field is applied to a cooking pot made of ferrous metal placed close to the work coil to induce it. It is heated.

It is desirable for this type of induction heating cooker to be able to arbitrarily change its output depending on the type and amount of cooking.

This is equivalent to adjusting the firepower in other cookers. On the other hand, such an induction heating cooker does not have a heat generating part in the cooker itself, but during actual heating, the heat of the cooking pot is transferred to the inside of the cooker via the top plate, and the heat is transferred to the work coil or other device near the top plate. Electrical parts may become heated. In particular, if the pot is left empty, there is a danger that conductive heat from the pot may cause deterioration of the insulation of the work coil and damage to electrical components. Therefore, it is necessary to set an upper limit heating temperature and to stop heating when this upper limit temperature is reached. Furthermore, it is a necessary requirement for cooking that there are heating temperatures suitable for each type of cooking, and that the user can arbitrarily select the heating temperature. The present invention was made in view of the above circumstances, and is made possible by using a switch that links output adjustment and temperature adjustment and the same variable resistor.

Embodiments of the present invention will be described below with reference to the drawings.

In Figure 1, 1 is a commercial AC power supply, Spw is a power switch, 2 is a rectifier circuit formed by connecting four diodes (not shown) in a bridge, CH is a choke coil, and CO is rectified via a choke coil CH. The capacitor connected to the circuit 2 is a high-frequency bypass capacitor with a small capacity of about 10 μF, which has high impedance for commercial AC frequencies (50/60 Hz) and low impedance for high frequencies. Therefore, at the connection point between the capacitor CO and the coil CH, there is a pulsating current signal (■) that oscillates between 0 and 140V. . 1 (Figure 3) is obtained.

L is a work coil whose one end is connected to the positive side of the rectifier circuit 2 via a choke coil CH, GTR is a switching element such as a switching transistor, the collector is connected to the other end of the work coil L, and the emitter is connected to the negative side of the rectifier circuit 2. , and the base is connected to a drive circuit 3, which will be described later. As the switching transistor GTR, a large capacity giant transistor or a gate turn-off thyristor GTO used in this embodiment can be used.
Further, the work coil L is wound in a spiral shape, and an insulating top plate 4 made of a ceramic plate or the like is adjacent to the work coil L.
A cooking pot 5 made of ferrous metal is placed on top plate 4. Therefore, the high frequency alternating magnetic field generated in the work coil L is transmitted to the top plate 4.
is added to pot 5. C1 is a resonant capacitor connected in parallel with the switching transistor GTR;
D1 is a diode connected antiparallel to the switching transistor GTR. Each of these parts constitutes an inverter circuit. CT is a current transformer wound around the line between the work coil L and the diode D1. outputs a voltage x proportional to the input voltage to the output terminal X. Reference numeral 6 denotes a control power supply, to which AC power 1 is supplied via a power switch Spw, and DC voltages VCC2 and 6 each have a predetermined value.
Outputs VDD and pulsating current signal VCC3.

Here, the DC voltage VCC2 is approximately 24V, and the drive circuit 3
It is used as a power source for driving. Further, the DC voltage DD is made into a stable DC voltage having a value of about 13V by a constant voltage circuit 7 in the control power supply 6, and is used as a power supply for driving a multi-circuit as described later. Furthermore, the pulsating current signal VCC3 is 0 to 4.
It has an amplitude width of 0V and is applied to the starting circuit 8. The starting circuit 8 inputs the voltage ■DO as a driving power source and the pulsating current signal ■CC3 as a signal, and outputs a starting signal for starting the inverter circuit.

To explain the circuit 8, VRl has one end connected to the power supply VD.
D is a variable resistor whose other end is connected to one end of capacitor C2, and Q1 is a power supply V. D is the anode, and variable resistor VRl is SC, to which the potential at the connection point of capacitor C2 is applied to the gate.
R, whose cathode is grounded. Rl, C3 is S
A resistor and a capacitor are inserted in parallel between the anode and cathode of CRQl to absorb noise such as rush current that may occur when the power is turned on. NANDl
In this case, the anode potential of SCRQl is just a pulse. A NAND gate is applied to one end of the signal A obtained through the gate, and becomes conductive when the signal A when the gate is open becomes equal to or higher than the threshold voltage FEVth of this gate. Q2 is a transistor to which the output of the NAND gate NANDl is applied to its base via a capacitor C4 and a resistor R3, and its collector is connected to the power supply VDD via a resistor R4, and its emitter is grounded via a resistor R. C5 is a capacitor connected to the collector side of the transistor Q2, and the pulse signal B is obtained as its output. INVl is connected to the collector of transistor Q2,
Inverter D2 that inverts the collector potential is inverter I
A starting pulse C is output by a backflow prevention diode provided at the NVl output terminal. The output signal R is a signal output from the collector of the transistor Q2, and has substantially the same waveform as the signal B. 9 is an output control circuit, and Q3 is a current transformer CT.
A transistor to which the signal x from the terminal .

D3 is a diode connected between the base and emitter of the transistor 9 to half-wave rectify the input signal The starting signal C is applied to the cathode of the diode D2. C6 is a capacitor installed between the connection point (hereinafter referred to as Y point) and ground between resistor B9 and RIO, and INV4 is
An inverter to which the output of inverter IN■3 is input,
Together with the inverter INV3, it constitutes a Schmitt circuit. Rll is a resistor inserted between the input terminal of the inverter INV3 and the output terminal of the inverter INV4, and is used to increase the switching speed of the inverter. C7
, Rl. , D4 are a capacitor, a resistor, and a diode, which are connected between the output terminal of the inverter INV4 and the ground. The potential at the connection point between the capacitor C7 and the resistor Rl2 (hereinafter referred to as point ZO) is input to the inverter IN5 via the resistor Rl3, and the output of this inverter INV5 is added to another inverter INV6. These 2
The inverters INV, , IN6 constitute a Schmitt circuit. Rl4 is INV5 and inverter IN■6
This is a resistor inserted between the output terminals of . Inverter IN
The output of V6 is applied to the drive circuit 3 via a resistor Rl5. Note that this drive circuit 3 amplifies the output signal from the inverter INV6 using a transistor or transformer (not shown), and amplifies the output signal from the switching transistor GT.
When this starting signal is a positive signal, the switching transistor GTR is turned off, and when the other signal is negative, it is turned off. The drive circuit 3 made up of such an amplifier circuit can be realized using the well-known circuit configuration as described above, so its details will be omitted. 10
is an output delay circuit, C7 is a capacitor to which the power supply VDO is applied to one end, Q4 is a transistor whose base is connected to the other end of this capacitor C7 via a resistor Rl6, and the collector of this transistor Q4 is connected to a resistor Rl7. Z of resistor Rl3 through.

At the point, the emitter is also grounded. D5 is a diode connected between the base and emitter of the transistor Q4, and discharges the charge stored in the capacitor C7. The significance and operation of this output delay circuit 10 will be described later. Reference numeral 11 denotes an overload detection circuit, which protects the device from damage to electrical components due to excessive human power due to differences in the material of the pot 5 or accidental generation of inrush current.

In the figure, 1NV7 is an inverter that inputs the signal X from the output terminal of the current transformer CT via a resistor Rl8, FFl is a flip-flop consisting of two NAND gates NAND2 and NAND3, and the output of the inverter INV7 is added to the single power of the NAND gate NAND2. , and the collector potential signal D of the transistor Q2 of the starting circuit 8 is applied to the other NAND gate NAND3 to be reset.
q is the NAND gate NAND2 of the flip-flop FFl
This is a transistor whose output is inputted to its base via a resistor Rl9, its collector is connected to the ZO point via a resistor R2O, and its emitter is grounded via a resistor R2l.
R22 and D9 are a resistor and a diode inserted in parallel between the input terminal of the inverter INV7 and the ground, which divide the current transformer CT output signal X together with the resistor Rl8 and perform half-wave rectification. 12 is a no-load detection circuit which detects when the pot 5 placed on the top plate 4 is removed.

A signal A is input to one input terminal of the NAND gate NAND4, and a detection output signal X of the current transformer CT, which is voltage-divided via resistors R23 and R24, is input to the other input terminal.
At the same time, the divided voltage signal of the signal X is connected to the clock input terminal CK of the counter CNT. 21) 1 is a Zener diode connected in parallel with resistor R24 and is a NAND gate NA
It protects ND4.

A load detection circuit 13 detects when the pot 5 is placed on the top plate 4, and includes the counter CNT described above. This counter CNT is known as a Johnson counter that has one output terminal and counts clock pulses and outputs a signal from each corresponding output terminal. In this embodiment, the sixth output terminal Q6 of the above-mentioned output terminals, that is, the terminal that outputs a signal when six clock pulses are counted, is used. Therefore this counter C
NT counts the pulses of the signal x that have a value greater than a certain value, and when the number of pulses reaches 6, outputs Q6.
occurs. This number [6] serves as a criterion for the presence of a load, no load, or the presence of a load of small objects.When there are six or more, it is determined that there is no load, and when there are five or less, it is determined that there is a load. Note that the terminal CL of the counter CNT is a clear signal input terminal, and a signal A is applied from the starting circuit 8 to the terminal CL, which is cleared every half cycle of the AC signal. FF2
is a flip-flop consisting of NAND gates NAND5 and NAND6. Signal B is applied from the starting circuit 8 to the single-power terminal of the NAND gate NAND5, and the output signal of the counter CNT is applied to the single-power terminal of the NAND gate NAND6 via the inverter 1NV8. Added. The NAND gate NAND7 obtains two inputs, the signal A from the SCRQl and the output signal 1 of the NAND gate NAND5, and an output J. F
F3 is a flip-flop consisting of NAND gates NAND8 and NAND9; The output signal K of AND4 is connected to the output terminal of NAND gate NAND8, and the output signal J of NAND gate NAND7 is connected to the output terminal of NAND gate NAND8.
Input each to the single power end of AND9, and
Signal L is obtained from the output of AND9. This signal L is used for backflow prevention. It is input to the input side Y point of the inverter INV3 via the stop diode D7. R5 and D6 are NAND gate N
A resistor and a diode are inserted between the output terminal of AND5 and the input terminal of NAND gate NAND7.
When AND4 output K goes to L level, the input side of NAND gate NAND9 goes to L level to prevent both inputs of flip-flop FF3 from going to L level. Reference numeral 14 denotes an operation release circuit that stops the functions of the above-mentioned no-load detection circuit 12 and load detection circuit 13, and is constructed by inserting a normally open switch SO and a resistor R26 between the single-power terminal of the NAND 9 and the ground. .

By operating this switch SO, flip-flop FF3
The output is fixed at H (high) level, and the heating operation is performed regardless of the presence or absence of a load. This deactivation circuit 14 is used when it is desired to heat a small cooking pot that has a load comparable to the load of small items. Reference numeral 15 denotes a temperature/output adjustment circuit, which has a temperature adjustment function that controls the heating temperature of the cooking pot in a steady state, and an output adjustment function that can adjust the output within a predetermined range (in this example, a range of about 500 W to about 1350 W). It has

In this example, temperature control is divided into a low temperature range from 60°C to 100°C and a high temperature range from 160°C to 200°C. It can also be a region. Such a temperature adjustment function is effectively used for foods that have an optimal cooking temperature, such as tempura dishes. On the other hand, the output adjustment function adjusts the output from 500W to 13
By switching within the range of 50W, you can adjust the amount of energy supplied to the cooking pot, which is equivalent to the heat power in other cookers.If it is better to change the output in the middle of cooking, for example, the initial output is set to "Strong", and the after output is set to "
It is used in cases where it is better to say "weak". Also, if you want to boil water, you can boil it fastest by setting the output to "High". Note that the temperature adjustment or output adjustment is displayed by the output display circuit described later, and when the temperature adjustment function is working, the light emitting diode LED1~ is displayed until the set temperature is reached.
LED5 is lit and turns off when the set temperature is reached. This tells you whether the set temperature has been reached. Further, when the output adjustment function is working, desired light emitting diodes LED1 to LED5 are lit according to the output. Returning to the diagram and continuing the explanation of the configuration, n is the power supply ■
11) A negative characteristic thermistor, for example, is used as a heat-sensitive element inserted between D and ground together with a capacitor C9.

S1 to S4 are three-contact changeover switches whose sliding contact pieces move over terminals 1, 2, and 3, and each switch is configured to interlock with each other. Here switch Sl,
The switch S2 is used for temperature adjustment and is used for switching the heating temperature range, the switch S3 is used for switching from temperature regulation to output regulation, and the switch S4 is used for setting a reference level. Here, terminals 1 and 2 of switch S1 are resistors R27 and R2, respectively.
■Power supply via 8. o and terminal 3 is grounded via resistor R32. A common terminal C of the switch S1 is connected to one end of the thermistor n and a negative potential input terminal O of the differential amplifier 0p. Terminals 1 and 2 of the switch S2 are connected to the negative potential input terminal θ of the differential amplifier U and one end of the thermistor Th via resistors R29 and RO, respectively, and the terminal 3 is at an empty level. The common terminal C of this switch S2 is grounded via a variable resistor VR2, the terminals 1 and 2 of the switch S3 are grounded via a common resistor R3l, and the common terminal C is connected to point ZO via a resistor R2O. ing. Terminal 1 of switch S4 is grounded via resistor R33, terminals 2 and 3 are both vacant, and common terminal C is grounded via resistor R3.
4 to the positive potential input terminal of the differential amplifier 0p. This positive potential input terminal 1 has a DC voltage ■. o is resistance R3
5, the voltage is divided by R36 and inputted as a reference voltage. Further, a capacitor ClO is inserted in parallel with the resistor R36. 0p is the above-mentioned differential amplifier, which outputs an H level signal when the signal input to the positive potential input terminal 4 is larger than the signal input to the negative potential input terminal e, and conversely, the negative potential input signal is the positive potential input signal. When the value is larger than that, an L level signal is output.

The output of this differential amplifier 0p is the NAND gate N. AND
It is added to the single force end of l. Here, each of the above switches S1
The specific configuration of ~S4 will be explained based on FIG. Reference numeral 18 indicates a cooking device operating surface, and 16 indicates a switching knob provided on the operating surface 18. By switching the switching knob 16 from the top to the bottom in three stages (indicated by arrows in the figure), the temperature can be adjusted in the upper two stages. The output can be adjusted at the bottom.

That is, terminal 1 of the switches S1 to S4 is set in the upper stage, terminal 2 is set in the middle stage, and terminal 3 is set in the lower stage. In this case, the terminal 1 setting state is a low temperature heating range of 60'C to 100'C, and the terminal 2 setting state is 16
The high temperature heating range from 0°C to 200'C and the terminal 3 setting state are set to the output adjustment range. LED1~LED5
is a light emitting diode that provides output display. For example, assuming that the terminal 1 is currently set, the reference potential applied to the positive potential input terminal 1 of the differential amplifier 0p becomes a low level due to the parallel insertion of the resistor R33 connected to the terminal 1 of the switch S4.
The comparison voltage applied to the other negative potential input terminal O is the resistor R27,
It is determined by R29, thermistor n, and variable resistor VR2, and as the temperature rises, the resistance value of thermistor Th decreases, so the comparison voltage reaches the reference voltage, and the differential amplifier 0
The output of p is changed to L level. Therefore, temperature adjustment in the low temperature heating region is possible. When switching to the other terminal 2, the terminal 2 of the switch S4 is in an empty state, so the above-described parallel insertion of the resistor R33 is interrupted, and the reference potential of the positive potential input terminal 1 of the differential amplifier 0p is changed. Therefore, resistance R
28, R3Ol The comparison voltage determined by the thermistor n and the variable resistor VR2 operates in the same manner as in the low temperature region and enables heating in the high temperature region. The slide knob 17 is used to further set an arbitrary temperature in each temperature range set in this way. This slide knob 17 controls the variable resistor (R2), allowing linear temperature control. The setting state of the terminal 3 is such that the output can be adjusted, and the details thereof will be described later, but the setting state of the terminal 3 can be variably adjusted by controlling the variable resistor VR2 as described above. Here, the following conditions are attached to the temperature adjustment switch S1 and the output adjustment switch S3 in terms of their functions.

First, when switching between terminals 1 and 2 of switch S1, a configuration must be adopted in which the switching piece is once separated from terminal 1 and then comes into contact with terminal 2. This is because, if both terminals are connected when switching between terminals 1 and 2, the resistors R27 and R28 connected to each terminal 1 and 2 will be connected in parallel, and the combined resistance with the thermistor Th will be instantaneously This is because the negative potential input signal of the differential amplifier 0p rises and exceeds the reference voltage, changing its output to L level and stopping the heating operation. As such a switch, a well-known non-shorting type CnOn switch is used. Next, terminals 1, 2 of switch S3,
For switching between terminals 3 and 3, a short-circuit switch must be used, in which there is a period during which all three terminals are in contact during switching.This means that, for example, when switching from terminal 2 to terminal 3, if a disconnection condition occurs, This is because the resistance value during this period becomes infinite, and the time constant determined by the capacitor C7 exceeds the rating of the transistor GTR, which may destroy it. 19 is an output display circuit, and the output signal x of the current transformer CT is is rectified via diode D8, and further smoothed and input to capacitor Cll.

ZD2 is a Zener diode to which this DC-converted current transformer CT signal is applied, and becomes conductive when the signal exceeds its Zener voltage.LEDl is connected to the cathode of the Zener diode (small) through a resistor R.37. light emitting diode, LED2+LED3,
LED4 and LED5 are each resistor R389R399R
4O9R4l and Zener diode 21) 3, ZD
4, the Zener diode Z via ZD5 and ZD6
These are light emitting diodes connected in parallel to the cathode side of D2. Here Zener diode 2]) 3~2
1) The Zener voltage and resistance values of 6 and resistors R38 to R4l are increased as they go to the right in the figure. As a result, for example, current transformer CT output voltage signal X
When the value increases, the light emitting diode LED5 at the left end in the figure lights up sequentially in the right direction, and the level of its output is displayed. These light emitting diodes LED1 to LED5 are arranged on the operation surface 18. Next, the operation of the induction heating cooker having such a configuration will be explained.

(1) When normal heating operation is performed, the pot 5 with an appropriate load is placed on the top plate 4.

Further, it is assumed that in the temperature/output adjustment circuit 15, the switches S1 to S4 are set to the terminal 1 by the switching knob 16. As already mentioned, this setting state is in the low temperature heating range of 60 to 100°C, and the slide knob 17 further determines an arbitrary temperature, for example, 80°C. In this state, the period T shown in FIG. When the power switch Spw is turned on, the pulsating current power source ■CO3 is output from the control power source 6 and is applied to the starting circuit 8. During a period T1 of this voltage Cc3 starting from 0V, SCRQl is turned on after a predetermined time t1 from 0V.
Note that the above time t1 is the time when variable resistor ■R1 and capacitor C2
determined by the time constant of approximately 1rr1. sec. of such SCRQl. FIG. 3 shows the voltage signal A for the anode and cathode. This conduction of SCRQl is caused by the pulsating power supply VC
・Continues from time after 3 rises from 0V until time T2 when it approaches 0V again. This kind of turning on/off of SCRQl is a pulsating current power supply■. . It is repeated every 3 cycles.

■This power supply. . The period of 3 is 112 of the commercial AC signal, which is approximately 10 TrLsec (in the case of 50 Hz).

When the SCRQl becomes conductive, the single power end of the NAND1 changes from the H level to the L level. At this time, Nand Gate N. The output of ANDl changes from L level to H level. As mentioned above, the output signal of the differential amplifier U of the temperature/output adjustment circuit 15 is applied to the other inputs of the NAND gate NANDl, and since the thermistor Th is at room temperature in the initial state of heating, its output becomes H level. There is. Now, the output signal of the NAND gate NANDl which has changed to H level is applied to the transistor Q2 via the capacitor C4 and the resistor R3, and is connected to the capacitor C4 and the resistor R3.
The transistor Q2 is conductive for a period determined by the time constant, and a signal D is obtained at the collector of the transistor Q2.

This signal D is inverted by the inverter IN1 and becomes the activation signal C, which is applied to the inverter INV3 in the output control circuit 9. Due to this activation signal C, the input of inverter INV3 becomes H level, and therefore the input of the next stage inverter IN
■Output E of 4 changes to H level. In addition, from signal E to signal G
The waveform up to this point is a high frequency oscillation of 20 to 40 KHz, and the time scale is much smaller than the waveform shown in FIG. 3, and is shown separately in FIG. 4. Now signal E is capacitor C7 and Z. The falling time determined by the time constant of the combined resistance between point and ground, its output, that is, the inverter INV
The input signal No. 5 becomes a pulse that gradually decreases from the rising edge as shown in waveform F. When this signal F is higher than the threshold voltage Vtll of the inverter INV5, the output G of the inverter INV6 becomes H level. This signal G is applied to the drive circuit 3 via the resistor Rl5, where it is amplified and turns on the switching transistor GTR. Due to the conduction of this transistor GTR, a load current 1L begins to flow through the work coil L, and this current 1L is detected by the current transformer CT, and a voltage signal X proportional to the input voltage to the load is obtained at its output terminal X. When this signal X rises to a certain value, this signal turns on the transistor O and changes the input of the inverter IN2 to the L level. Therefore, the output of the inverter INV2 becomes H level and is applied to the next stage inverter 1N3.

Here, capacitor C6 and inverter IN■3, IN■4
Since inverter INV4 forms a delay circuit, the output of inverter INV4 is generated with a slight time delay with respect to the input of inverter 1NV3. Note that the significance of the delay circuit will be described later. When the output of the inverter INV4 becomes H level, the input of the inverter IN■5 becomes H level, and the inverter I
The output of NV6 also becomes H level 5. Further, the charging time of the capacitor C7 is determined by a time constant determined by the combined resistance between the capacitor C7 and the ZO point and the ground, and when charging is completed, the voltage between the ZO point and the ground decreases. When this voltage becomes lower than the threshold voltage ■peak of inverter INV5, inverter I
The NV6 output G changes to L level, stopping the drive circuit 3 and turning off the switching transistor GTR.
This period is now shown as Ta in FIG. Then the period T
Discharging of the energy charged in the work coil L at point a begins (period TO), and this energy is charged in the resonant capacitor C1. After the charging of the capacitor C1 is completed, the charging load of the capacitor C1 is transferred from the capacitor C1 to the work coil L1 and the capacitor C during the following period C. It is discharged through the path that leads back to the capacitor C1, and at the same time, the work coil L is charged. Next, work coil L
The electric charge charged in is discharged through a path consisting of the work coil L1, the capacitor CO1 diode D1, and the work coil L (period Td), thus completing one cycle of vibration caused by the activation signal C.

Thereafter, the signal X of the current transformer CT, which is output when the current 1L rises from zero in the positive direction, is applied to the transistor Q3 to turn it on. As a result, the input of the inverter INV2 changes to L level and the output changes to H level.
On the other hand, at this time, the NAND gate N of flip-flop FF3
Assuming that the output of AND9 is at L level, the input to resistor RIO is held at L level by this L level signal.

Therefore, even if the output of inverter IN■2 becomes H level as described above, the input of the next stage inverter IN■3 becomes L level.
The level remains unchanged, and therefore, no signal is output to the drive circuit 3, and the transistor GTR maintains its off state. Therefore, after the period Td, damped vibration occurs due to the work coil L and the resonant capacitor C1. This is the fourth
5 and period L in FIG. This damped vibration rapidly weakens because a normal pot 5 is placed on the top plate 4. This damped oscillation is detected by the current transformer CT, and its output signal X is voltage-divided by resistors R23 and R24, applied to the NAND gate NAND4, and simultaneously inputted to the clock terminal CK of the counter CNT. Here, only pulses having a threshold voltage Vth or higher included in the signal X are counted, and in this case, the number of pulses is about two. Therefore, the output Q6 remains at the L level, and the output H of the inverter INV8 remains at the H level. Note that since the pulse signal B obtained from the collector of the transistor Q2 via the capacitor C5 is applied to the input of the NAND gate NAND5 of the flip-flop FF2 at the beginning of the period a1, the output signal 1 of the NAND gate NAND5 is at H level. When the starting pulse C is generated in the subsequent period Ia'2, this starting signal C is applied to the drive circuit 3 via the output control circuit 9 as described above, and is further applied to the transistor GTR.
is turned on and oscillation begins.

On the other hand, due to the generation of the starting pulse C, the NAND gate NA
The output J of ND7 changes to L level, and this signal J is input to the next stage NAND gate NAND9, inverts the lower flip-flop F3, and changes the output L of NAND gate NAND9 to H level.

Therefore, when the -cycle oscillation ends with the starting pulse C and the load current 1L rises from zero, when a signal x appears at the current transformer CT terminal X, this signal x
The transistor Q3 is turned on and the inverter I
The input of NV2 is set to L level. As a result, the output of inverter INV3 becomes H level, and furthermore, inverter IN■3
, H output through IN■4 and IN■5, INV6
The level signal G is applied to the drive circuit 3 and makes the switching transition filter GTR conductive, and the load current 1L starts to flow. In this case, since the output L of the NAND gate NAND9 is at the H level, the input side of the inverter INV3 is held at the H level, and the signal X from the current transformer CT is not cut off here. In this way, self-sustained oscillation continues, and this oscillation continues until time T2 when the pulsating current power supply VCCl drops to around O2, the amplification factor decreases, and the transistor GTR is turned off. This state is shown in periods T2 and T3 in FIGS. 4 and 5. This oscillation is repeated every half cycle of the AC frequency, and within each cycle, high frequency oscillation of about 20 to 40 KHz is performed, and the work coil L has a frequency of about 20 to 40 KHz.
A high frequency alternating current of KHz flows. As a result, a high frequency alternating magnetic field is applied to the pot 5 disposed close to the work coil L, and induction heating is performed. When heating is started in this way, the temperature of the pot 5 is detected by the thermistor n provided on the back side of the top plate 4, and when the temperature reaches the predetermined temperature of 80°C by adjusting the slide knob 17, the differential amplifier 0p is turned off. The negative potential input terminal e input signal becomes larger than the positive potential input terminal 1 input signal. Therefore the differential amplifier 0p
The output changes from H level to L level, closes NAND gates N and ANDl in the starting circuit 8, and stops generating the starting pulse C. As a result, the starting pulse is no longer sent to the output control circuit 9, so the inverter circuit stops oscillating and the heating operation is stopped. After that, when the temperature of the pot 5 decreases and the resistance value of the thermistor Th increases, the negative potential signal input terminal O signal of the differential amplifier U decreases and becomes smaller than the positive potential signal input terminal 1 signal again, and the output of the differential amplifier 0p. changes to H level, opens the NAND gate NANDl, starts sending out the starting pulse C again, starts inverter oscillation, and restarts the heating operation. In this way, the heating temperature of the pot 5 is set to 80.
It is maintained at °C. Next, the significance of the aforementioned delay circuit will be explained. This delay circuit is composed of a capacitor C6, an inverter 1NV3, and an inverter INV4.
output E to inverter INV3 input for a short time (
This delay is approximately 2 μSec). When adjusting the output by normal frequency control, for example, if the resonance frequency is adjusted on the low frequency side (strong output), when the frequency becomes high (weak output), the resistance R (= 2π + ±) on the circuit will be applied. condition
As 2πFOC increases, the charging capacity of the capacitor C1 becomes smaller and the discharge ends earlier.

Therefore, the voltage between the collector and emitter of the switching transistor GTR does not fall to O■.
R is turned on, causing heat generation and even damage.
Waveform M in FIG. 6 shows an operating state in which the resonance frequency is adjusted to the low frequency side and the output is strong in the low frequency region, and the load current 1L and the collector-emitter voltage of the switching transistor GTR. . indicates a normal relationship. On the other hand, the waveform N in the figure shows the case where the voltage V between the collector and emitter of the switching transistor GTR is adjusted on the low frequency side as described above and operated in the high frequency region, that is, in a state where the output is weak. It can be seen that the transistor GTR becomes conductive before E drops to O■. To prevent this, the output E of the inverter INV4 is slightly delayed to slightly delay the turn-on time of the switching transistor GTR, and the transistor GTR is turned on after the collector-emitter voltage CE becomes completely 0V. Next, the output control operation will be explained.

When performing output control, switches S1 to S4 of the temperature/output adjustment circuit 15 are switched to terminal 3, and the variable resistor V
Adjust R2. In this way, the combined resistance between the ZO point and ground (
This combined resistance is variable resistor VR2), resistor Rl2, R2O
) changes, the time constant with the capacitor C7 changes, and the time Ta for the input signal F of the inverter IN5 to fall from the rise to the threshold voltage Vth can be changed. Therefore, the switching transistor GT
This means that the conduction time of R can be changed, and the amount of electromagnetic energy charged in the work coil L can be changed in accordance with this change. That is, if this time Ta is set short, the electromagnetic energy supplied to the work coil L becomes smaller and the output decreases. At this time, the oscillation frequency increases. On the other hand, when the time Ta is set longer, the electromagnetic energy supplied to the work coil L increases, and the output increases. At this time, the oscillation frequency decreases. This output level is displayed by the output display circuit 19. That is, as the output gradually increases, the output signal x of the current transformer CT also increases in proportion to this. Since this voltage signal X is an AC signal, diode D8 and capacitor C
rectified and smoothed by ll and then passed to the next stage zener diode Z
Applied to D2. The rectified and smoothed signal above is a small Zener diode. When the Zener voltage exceeds the Zener voltage, a current first flows through the Zener diode 21) 2 to the resistor R37 and the light emitting diode LED1, thereby lighting up the light emitting diode LED. When the output voltage further increases, it exceeds the Zener voltage of the Zener diode ZD3 in the next stage, energizes the resistor R38 and the light emitting diode LED2, and this second light emitting diode LED2 lights up. In this way, as the output increases, the third light emitting diode LED3,
The fourth light emitting diode LED4 lights up, and when the maximum output is "strong", all light emitting diodes LED1 light up.
, LED2...LED5 lights up. When the temperature/output adjustment circuit 15 is in the output control state, the switch S
1 to S4 are set to terminal 3, the negative potential input terminal of the differential amplifier 1 is switch S1 and resistor R3. is grounded through. Therefore, the output of the differential amplifier 0p is always at the H level, and it is considered that the heating temperature will rise indefinitely if this continues. However, when the pot 5 is heated in this state and the temperature of the thermistor Th increases, its resistance value decreases, and the thermistor n1 switch S1 and the resistor R3
The voltage at the common terminal C point of the switch S1 divided by 2 increases. Therefore, when this voltage becomes larger than the input signal to the positive potential input terminal 4 side of the differential amplifier L, the output of this differential amplifier changes to L level, and the NAND gate NAND1
, the generation of the starting pulse C is stopped and the inverter oscillation is stopped. Therefore, the heating temperature does not increase indefinitely, and the resistance R3. If the heating upper limit temperature is appropriately set by appropriately selecting , it can serve as a safety device. (2) When an overloaded pot is placed In induction heating cookers, the type and size of the loaded pot is limited, such as an iron-based magnetic pot, but in actual use. Pots unsuitable for heating may be placed on the top plate 4.

For example, 18-8 stainless steel (displayed as SUS3O4)
When a pot made from aluminum (containing 18% chromium and 8% nickel) is heated, an excessive amount of current flows due to its low resistance. There is a risk that this excessive current will trip the circuit breaker or destroy the circuit elements. In the present invention, when an excessive current is generated due to such inappropriate load heating, other accidental inrush currents are detected and the output is reduced to make the device safer. That is, if an excessive current exceeding the normal load current flows through the work coil L, this excessive current is converted to a voltage X across the current transformer CT, and this voltage X is applied to the voltage dividing resistor Rl8, The voltage divided by R22 and applied to the resistor R22 is input to the inverter INV7. Normally, this divided voltage does not exceed the threshold of inverter INV7, but when an excessive current occurs, current transformer CT detection voltage x increases in proportion to this, so inverter INV7
It becomes more than the threshold voltage of . This allows the inverter INV
7 output changes to L level, and the output of NAND gate NAND2 of the lower flip-flop F1 changes from L level to H level. Therefore, this H level signal conducts the transistor Q5, and a new resistor t/LR2l is added in parallel to the combined resistance between ZO and ground, and the combined resistance value decreases. As a result, the time constant of this combined resistance and capacitor C7 becomes small, and the conduction time T of the switching transistor GTR becomes smaller.
a becomes shorter and the output decreases. FIG. 7 shows the waveform of the voltage x across the current transformer CT, which is a waveform in which an alternating frequency signal includes an alternating voltage signal of 20 to 40 KHz. Here, the waveform It oscillates repeatedly at a frequency of 40KHz. It can be seen that when the overload detection circuit 11 operates at time Ta shown in the waveform X'' and increases the oscillation frequency and lowers the output, the voltage X'' suddenly decreases. This prevents the input current to the load from becoming excessive and protects each circuit element. In particular, since there is a proportional relationship between this voltage X'' and the collector-emitter voltage CE of the switching transistor GTR, it is significant to be able to protect this transistor GTR.
Since the collector potential signal D of the transistor Q2 of the starting circuit 8 is input to the input terminal of the NAND gate NAND3, the initial half wave of the AC frequency signal (time T of the waveform X'' in FIG.
In b), this flip-flop lower F1 is reset,
Transistor q is turned off. Therefore, the overload detection circuit 11 is stopped again after that and normal oscillation drive is performed, and if the pot 5 is overloaded, the current transformer CT detects an overcurrent, and the overload detection circuit 11 is detected as described above. The load detection circuit 11 operates and reduces the output. This operation is performed every half wave of the AC frequency, and when the pot is replaced and the load changes to an appropriate value, the overload detection circuit 11 does not operate and normal heating operation continues. 3) When the pot is removed from the top plate during the heating operation When the proper pot 5 is placed on the top plate 4 and the heating operation is in progress, if the pot 5 is removed, the inverter continues to oscillate. This results in wasted power consumption.

Therefore, when such a situation occurs, it is desirable to stop the oscillation of the inverter. In this example, such treatment was performed. That is, during the heating operation, the pot 5
When removed, the work coil L that constitutes the inverter
The damped oscillation caused by the resonance of the resonant capacitor C1 becomes longer, and the oscillation continues even around the half wave of the commercial frequency signal. This is shown in waveform x in FIG. In the figure, P1 indicates the oscillation state when a normal load is applied, and P2 indicates the oscillation state in a no-load state. When there is a load, the oscillation stops, and when the load is removed, the oscillation continues. These differences are detected by the no-load detection circuit 12. That action is the 4th
To explain based on the diagram and FIG. 5, when the pot 5 is removed during the period Ti, the oscillation of the inverter continues as shown at point P2 of waveform X(7). Therefore, the following period Ti+1
The output K of the NAND gate NAND4 passes through the oscillation during the period in which the signal A exceeds the threshold voltage Vth of this gate, and changes to the L level. This L level signal causes flip-flop FF3 to be inverted, and the output L of NAND gate NAND9 changes to L level. This signal L (7) L level is added to the Y point and holds the inverter INV3 input at the L level, so the transistor Q3 and inverter I
The self-excited oscillation signal x applied via NV2 is cut off here, and self-excited oscillation is not performed. Therefore, the period Tj+
1, the attenuation rapid movement occurs only due to the initial startup pulse. This damped vibration is relatively constant since there is no load, and the number of pulses input to the counter CNT is six or more. When the number of input pulses reaches 6, the counter CNT issues an H level signal to the output Q6. The signal is inverted by an inverter INV8 to become a signal H, which is input to a NAND gate NAND6. As a result, the output signal 1 of the NAND gate NAND5 becomes H level only during the period when six pulses are emitted. On the other hand, the input of NAND gate NAND7. Since the above signal 1 and signal A are added, the output waveform remains at the H level as shown in J, and the output L of the next stage NAND gate NAND9 does not change.
Therefore, self-oscillation occurs and no heating operation is performed.
In this way, when the pot 5 is removed from the top plate 4, the oscillation automatically stops and the heating operation is no longer performed. Next, a case will be described in which a proper pot 5 is placed in the apparatus in such a state.

When the pot 5 is placed in the period Tj shown in FIG. 5, only the damped vibration due to the starting pulse C still occurs in the following period Tj+1. However, since this damped vibration is reduced by the presence of the pot, the number of pulses counted by the counter CNT is only about two. Therefore, an H level signal is not outputted from the counter CNT, and the output 1 of the NAND gate NANI) 5 is held in a state changed to H level by the signal B. When the pulse signal A is generated at the beginning of the following period Tj.+1, the output J of the NAND gate NAND7 changes to the L level, inverting the flip-flop FF3 and changing the output L of the NAND gate NAND to the H level. As a result, the inhibition of self-excited oscillation of the output control circuit 9 is canceled, and normal oscillation operation is performed. Now, if the cooker is in the heating operation state and the object placed on the top plate 4 is an inappropriate small load such as a knife or fork, it is necessary to detect this and stop the heating operation. be.

In the present invention, this is achieved by the load detection circuit 13 described above. In other words, when the above-mentioned small load is placed, the number of pulses exceeding a certain value generated by damped vibration is 6 or more, so the oscillation operation is stopped in the same manner as when the pot is removed as described above. . Therefore, even if you place the above-mentioned small load on the top plate with the power on, it will not be heated, and there is a risk of getting burned if you accidentally touch a heated knife, etc. do not have. Next, the output delay circuit 10 will be explained.

When the power switch Spw is turned on, the output L of the NAND gate NAND9 of the flip-flop FF3 is at either the H level or the L level. When the signal L is at the H level, the inverter starts to oscillate, and if the load is suitable, it will oscillate normally, and if there is no load or a small load, the no-load detection circuit 12 will operate and the NAND gate NA will be activated.
An L level signal is applied to the input of ND8, and therefore the output of NAND gate NAND9 changes to L level, inhibiting the oscillation of the inverter. The other NAND gate NAND9 output signal L
is at the L level, the state starts from the same state as when no load or a small load is detected, and if an appropriate load is placed, the load detection circuit 13 operates and the NAND gate NAN
An L level signal is input to D9, and its output becomes H level and the inverter starts oscillating. However, in the embodiment of the present invention in which the output is controlled by frequency, when the output is set to the "strong" position, oscillation does not occur near 0V of the commercial AC frequency signal when a small load is placed, and the It was confirmed that the condition was as if an appropriate load had been applied.
Therefore, in this state, the oscillation does not stop and there is a risk that the small load will be heated. The output delay circuit 10 described above solves this problem. In other words, in the cooker of this embodiment, since the resonant frequency is matched when the output is "strong", the capacitance due to the work coil L1 load and the resistance of the resonance capacitor C1 are the smallest when the output is "strong", and on the other hand, when the output is "weak". ”, the maximum value is reached. In other words, when the output is "strong" the load is heavy, and when the output is "weak" the load is the strongest. When the load becomes lighter, the oscillation will continue at around 0V of the AC frequency signal, similar to the oscillation state when there is no load, and if this oscillation is detected by the no-load detection circuit 12, it is possible to identify the load of a small object. It is. Next, its operation will be explained.

Now when power switch Spw is turned on, capacitor C7
The capacitor C7 is charged by the time constant of the resistor Rl6 and the base-emitter resistance of the transistor O, and a voltage higher than a predetermined value is applied between the base and emitter of the transistor Q4, so the transistor Q4 is Becomes conductive. Z due to conduction of this transistor Q4. The point-to-ground resistance Rl6 is newly connected in parallel, and the combined resistance therebetween decreases. In other words, the oscillation frequency of the inverter increases and the output becomes "weak". In this state of "weak" output, the oscillation continues around 0V of the AC frequency signal, so the output is "strong".
It was not detected when Small object loads will be reliably detected. As described above, the induction heating cooker of the present invention has a temperature adjustment function and an output adjustment function, and since both of these functions are connected to a common variable resistor via a temperature/output selector switch, both functions can be performed. The selection is made by the temperature/output changeover switch, and the temperature or output is controlled by controlling the variable resistor.

Therefore, compared to conventional devices that require separate adjustment means such as variable resistance for temperature adjustment and output adjustment, and separate adjustment switches, only one variable resistance and two switches are required. It's easy to operate because it's easy. Furthermore, according to the present invention, a plurality of temperature ranges can be divided into a high temperature range and a low temperature range, and the switch for switching between the two ranges is configured with a non-short circuit type switch, so that it is possible to mistakenly activate the switching start circuit. There is no risk of stopping, and reliable switching operations can be performed.

Furthermore, according to the present invention, the temperature/output changeover switch that switches from temperature control to output control is configured with a short-circuit switch, so that the time constant of the CR time constant circuit in the output control circuit is extremely increased when the switch is switched. Therefore, destruction of the switching transistor caused by this can be prevented. Furthermore, according to the present invention, even during the period when the output adjustment function is working, the temperature adjustment function is
Since the inverter stops oscillating when the heating upper limit temperature is reached, the temperature of the device does not rise indefinitely, and the safety of the device is maintained.

Furthermore, according to the present invention, while the output display device displays the output, it also turns off when the temperature adjustment function is activated when the set temperature is reached, so that it can also be used to display the temperature.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the induction heating cooker of the present invention, Fig. 2 is a perspective view of the cooker of the embodiment, and Figs. 3 to 7 are signal waveform diagrams for explaining the operation of the embodiment. be. 3...Drive circuit, 8...Start circuit, 9
... Output control circuit, 10 ... Output delay circuit, 11 ... Overload detection circuit, 12 ...
...No-load detection circuit, 13...Load detection circuit, 15...
...Temperature/output adjustment circuit, 19...Output display circuit.

Claims (1)

[Scope of Claims] 1. A pulsating current power source, an inverter connected between the pulsating current power source and including a work coil and a switching element for driving oscillation, and a starting means for generating a starting signal having the same cycle as the pulsating current power source; Output control means for applying a drive signal having an arbitrary time width, which is formed by inputting the start signal and passing through a time constant circuit, to the switching element and making it conductive; The induction heating cooker includes an input detection means for sensing, a signal from the input detection means to drive the output control means to self-oscillate the inverter, the heat-sensitive means disposed close to the load, and the heat-sensitive a resistance variable means inserted in series with the means, and a midpoint potential between the resistance variable means and the heat sensitive means is compared with a reference potential, and when the midpoint potential reaches the reference potential, operation of the activation means is prohibited. An induction device comprising a temperature adjustment means, and an output adjustment means that connects the resistance variable means in parallel to the time constant circuit via a temperature/output changeover switch, and changes the time width of the drive signal by adjusting the variable means. Heating cooker. 2. The induction heating cooker according to claim 1, wherein the temperature/output changeover switch is a short-circuit type switch that switches after the contacts are short-circuited. 3. A temperature range changeover switch is provided that switches and connects a plurality of resistors with different values in parallel to the heat-sensitive element, and the temperature range changeover switch is divided into a plurality of heating areas such as a high temperature heating area and a low temperature heating area, and the temperature range changeover switch has contacts that are similar to each other. 2. The induction heating cooker according to claim 1, wherein the induction heating cooker is comprised of a non-short-circuiting switch that is switched once it is opened. 4. The temperature/output selector switch and the temperature range selector switch are interlocked, and when the temperature/output selector switch is switched to the output side, the temperature range selector switch connects a predetermined resistor in series to the heat-sensitive means, and connects the resistor and the heat-sensitive unit in series. 4. The induction heating cooker according to claim 3, wherein the midpoint potential of the means corresponds to the upper limit heating temperature.