JPS61171180A - Semiconductor coupled superconductive element - Google Patents

Semiconductor coupled superconductive element

Info

Publication number
JPS61171180A
JPS61171180A JP60012134A JP1213485A JPS61171180A JP S61171180 A JPS61171180 A JP S61171180A JP 60012134 A JP60012134 A JP 60012134A JP 1213485 A JP1213485 A JP 1213485A JP S61171180 A JPS61171180 A JP S61171180A
Authority
JP
Japan
Prior art keywords
type
semiconductor
superconducting
inversion layer
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60012134A
Other languages
Japanese (ja)
Other versions
JPH0452632B2 (en
Inventor
Hideaki Takayanagi
英明 高柳
Goji Kawakami
剛司 川上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60012134A priority Critical patent/JPS61171180A/en
Publication of JPS61171180A publication Critical patent/JPS61171180A/en
Publication of JPH0452632B2 publication Critical patent/JPH0452632B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/11Single electron tunnelling devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/128Junction-based devices having three or more electrodes, e.g. transistor-like structures

Abstract

PURPOSE:To increase the electrode gap much more than conventional, and further to realize superconductive two-terminal or three-terminal elements, by a method wherein a p-type semiconductor substrate with a two dimensional electron gas formed in the surface inversion layer and two superconductive electrodes in ohmic contact with the surface inversion layer of the substrate are included. CONSTITUTION:The surface of a p-type InAs is in inversion to n-type regardless of carrier concentration, and a two-dimensional electron gas (2DEG) is formed in this inversion layer. The ohmic contact of superconductive electrodes 2 with the semiconductor 1 is required. In this respect, the Schottky barrier height to the metal of the n-type InAs layer 5 or inversion in the surface of the p-type InAs substrate 1 is always negative and forms the ohmic contact. Therefore, the electron tunnel probability Tj at the semiconductor/superconductor interface is much larger than that of p-type Si or the like. From this point, the electrode gap L is taken long, about 0.5mum; thereby, the preparation of a three-terminal structure as well as a two-terminal structure is enabled, and the two-terminal action that superconductive current flows through the 2DEG is enabled.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体を接合部にもつ超伝導素子、即ち超伝
導体−半導体−超伝導体結合素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a superconducting device having a semiconductor at a junction, that is, a superconductor-semiconductor-superconductor coupled device.

〔発明の概要〕[Summary of the invention]

本発明は、P形半導体の弐面のn形反転層に形成された
2次元電子ガス(2DEG)によって二つの超伝導電極
が結合している半導体結合超伝導素子を提供するもので
ある。
The present invention provides a semiconductor-coupled superconducting element in which two superconducting electrodes are coupled by a two-dimensional electron gas (2DEG) formed in an n-type inversion layer on the other side of a P-type semiconductor.

〔従来の技術〕[Conventional technology]

トンネル形ジョセフンン素子の発明以来、半導体におけ
るトランジスタやFETに対応する超伝導三端子素子の
研究は数多く行なわれて来た。この中にあって、半導体
結合超伝導素子は、バリアーハイドが低く電極間隔が広
くとれること、更に半導体に対する電気的制御によシ三
端子動作の可能性があることから、多くの試みがなされ
て来たが、実用に供するものは得られていない。
Since the invention of tunnel-type Josephson devices, much research has been conducted on superconducting three-terminal devices corresponding to transistors and FETs in semiconductors. Among these, many attempts have been made to develop semiconductor-coupled superconducting devices because of their low barrier hydride and wide electrode spacing, and the possibility of three-terminal operation through electrical control of the semiconductor. However, we have not obtained anything that can be put to practical use.

第13図に従来の半導体結合素子の断面構造を示すが、
これまでに実現されたものでは、基板1の半導体として
単結晶Slを用い、拡散又はイオン注入によシ高濃度の
P形として第13図のように超伝導電極2を互に近接し
て形成した構造で超伝導電流が得られている。これにつ
いては、R,C,Ruby& T、 Van Duze
r : IEIJ Trana、 Elect、 De
vice。
Figure 13 shows the cross-sectional structure of a conventional semiconductor coupling device.
In what has been realized so far, single-crystal Sl is used as the semiconductor of the substrate 1, and superconducting electrodes 2 are formed close to each other as shown in FIG. Superconducting current was obtained with this structure. Regarding this, R, C, Ruby & T, Van Duze
r: IEIJ Trana, Elect, De
Vice.

ED−28,1394,(’81)に報告されている。It is reported in ED-28, 1394, ('81).

ところで、半導体結合超伝導素子の特性は、半導体中の
超伝導拡散長ξNと、超伝導体と半導体との表面特性に
密接に関連している。超伝導近接効果理論J、 5et
o & T、 Van Duzer : Low Te
mpera−ture Physies−LT−13+
 328. Nevr York+ Plenum。
By the way, the characteristics of a semiconductor-coupled superconducting element are closely related to the superconducting diffusion length ξN in the semiconductor and the surface characteristics of the superconductor and the semiconductor. Superconducting proximity effect theory J, 5et
o & T, Van Duzer: Low Te
mpera-ture Physies-LT-13+
328. Nevr York+ Plenum.

(’74)によれば、最大超伝導電流Icは、Iccg
Tj”exP(−L/ξN)/ξN    (式1)と
なる。ここで、Tjは超伝導体/半導体表面における電
子のトンネリング確率でアシ、上式よシ大きなIcを得
るためにはTjが大きく、ξNの長い必要のあることが
わかる。一般的に、金属/半導体表面にはショットキー
バリアーが形成されるが、Tjはこのバリアー高が低く
、バリアー幅のりすい程大きくなる。
('74), the maximum superconducting current Ic is Iccg
Tj”exP(-L/ξN)/ξN (Formula 1).Here, Tj is the tunneling probability of electrons on the superconductor/semiconductor surface, and in order to obtain a larger Ic than the above equation, Tj must be Generally, a Schottky barrier is formed on a metal/semiconductor surface, but Tj increases as the barrier height decreases and the barrier width increases.

第14図は超伝導体−P形シリコン−超伝導体素子のエ
ネルギーバンド図で6 ’) 、EFはフェルミレベル
# Ec、Eyはそれぞれ伝導帯2価電子帯の下端及び
上端エネルギーレベルを示す。P形シリコンの場合バリ
アー高Ebは0.2 eVである。バリアー J幅Wは
キャリア濃度nに依存し、nが大きい程うすくなる。従
って、P形シリコンを用い九素子では10”am7”と
nをなるべく大きくする必要があつた。一方、ξNは半
導体の移動度をp (am /VS)とすると、 ξNcg p 34 n 3((式2)%式% 前述のP形Siの場合、T = 4.2 Kでp 言6
00m”/VBと小さく、ξNは約0.011rmと短
い。このようにP形シリコンを用いた素子ではnが10
  am  と大きいにもかかわらずξNは短く、素子
長L=0.1μm前後の素子しか実現できなかった。キ
ャリア濃度が10!08m”ではもはや半導体とは言い
がたく金属的であシ、例えMIS (電圧駆動型)やM
ES (電流注入駆動型)構造が実現されても、ゲート
の印加電圧や流入電流の変化に対してごく感度の鈍いも
のになシ、トランジスタ又はFIT素子のような半導体
としての特徴を生かすことはできない。ま九超伝導電極
間隔が0.1μmでは、半導体上に第三端子を形成する
こと自体非常に困難である。
FIG. 14 is an energy band diagram of a superconductor-P-type silicon-superconductor element (6'), where EF is the Fermi level #Ec and Ey are the lower and upper energy levels of the conduction band and the double valence band, respectively. In the case of P-type silicon, the barrier height Eb is 0.2 eV. The barrier J width W depends on the carrier concentration n, and the larger n is, the thinner it becomes. Therefore, in the case of nine elements using P-type silicon, it was necessary to make n as large as possible, i.e., 10"am7". On the other hand, if ξN is the mobility of the semiconductor as p (am/VS), then ξNcg p 34 n 3 ((Formula 2)% Formula % In the case of the P-type Si described above, p at T = 4.2 K6
00m"/VB, and ξN is short, about 0.011rm. In this way, in an element using P-type silicon, n is 10
Despite the large am, ξN was short, and only an element with an element length L of around 0.1 μm could be realized. When the carrier concentration is 10!08 m'', it can no longer be called a semiconductor and is metallic.
Even if an ES (current injection driven) structure is realized, it will be extremely insensitive to changes in the applied voltage to the gate and the inflow current, and it will not be possible to take advantage of the characteristics of a semiconductor such as a transistor or FIT element. Can not. If the superconducting electrode spacing is 0.1 μm, it is very difficult to form the third terminal on the semiconductor.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明は、前述の従来の超伝導体−半導体−超伝導体結
合素子における問題点、すなわち超伝導電流を得るため
に超伝導電極間隔を極めて短かくしなければならず、ま
た半導体のキャリア濃度を極めて高くしなければならな
いという問題を解決し、特性の優れた超伝導二端子ある
いは三端子素子を実現しようとするものである。
The present invention solves the problems with the conventional superconductor-semiconductor-superconductor coupling device mentioned above, namely, the distance between superconducting electrodes must be extremely short in order to obtain superconducting current, and the carrier concentration of the semiconductor must be reduced. The aim is to solve the problem of having to increase the height extremely high and to realize a superconducting two-terminal or three-terminal device with excellent characteristics.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、P形半導体の表面反転層中に2次元電子ガス
(2DECという)が形成されること、及び2次元にお
いて超伝導拡散長ξNは、前述の3次元(バルク半導体
)の場合の式2のξドーμ帽3に対して、後述のように
8w CL pにnにとなるという解析結果に着目して
なされたものである。
The present invention is based on the fact that a two-dimensional electron gas (referred to as 2DEC) is formed in the surface inversion layer of a P-type semiconductor, and that the superconducting diffusion length ξN in two dimensions is calculated using the formula for the three-dimensional (bulk semiconductor) described above. This was done by paying attention to the analysis result that 8w CL p becomes n for the ξ do μ hat 3 of 2, as described later.

本発明において、P形半導体の表面反転層中の2DIG
Kよって二つの超伝導電極が結合している半導体結合超
伝導素子を提供する。
In the present invention, 2DIG in the surface inversion layer of a P-type semiconductor
K thus provides a semiconductor-coupled superconducting element in which two superconducting electrodes are coupled.

本発明構成において、P形半導体の狭面にn型反転層が
形成され、その中に2DECが形成されていること、 該2 DECが形成された半導体層と二つの超伝導電極
との接触がオーミックであることが必要である。
In the configuration of the present invention, an n-type inversion layer is formed on the narrow surface of the P-type semiconductor, and a 2DEC is formed therein, and the semiconductor layer on which the 2DEC is formed is in contact with the two superconducting electrodes. It needs to be ohmic.

以下よシ詳細に本発明をその作用とともに解説する・ 〔作 用〕 近接効果理論によると、半導体中の超伝導拡散長ξNは
ξN=(fID/2πkBT)牙 で与えられる。ここ
で、1=−でhはブランク定数、Dは拡散係2π 数、kBはボルツマン係数、 Tは温度である。
The present invention will be explained in detail below along with its operation. [Operation] According to the proximity effect theory, the superconducting diffusion length ξN in a semiconductor is given by ξN=(fID/2πkBT). Here, when 1=-, h is a blank constant, D is a diffusion coefficient 2π number, kB is a Boltzmann coefficient, and T is a temperature.

Dは3次元の場合、1) = T VFII(V、はフ
ェルミ速度、lは平均自由行程)であるが、2次元の場
合kp = (2gn、)y2. vF=fIk、/m
*であるから、2次元系のξNは ξN=(五”μ/4rkBTem*)’r(2rns)
¥ Cpイn3¥−(式3) と求まる。3次元の場合のξN(CpKnに と比較す
ると、例えばn 、 nBが共に1桁上がった時の効果
は2次元の場合の方が大きく、それだけ制御性は向上す
ると言える。又、ξNを大きくするためにはn + n
Bを上げねばならないことは同じであるが、前述の様に
、3次元(バルク)の半導体の場合、nを大きくするた
めにドーパントを多くドープすると、それが散乱体とな
ってpが落ち、結果としてξNが小さくなるという結果
を招く。しかし、2次元の場合は次の理由によってその
ようなことはない。
In the three-dimensional case, D is 1) = T VFII (V, where V is the Fermi velocity and l is the mean free path), but in the two-dimensional case, kp = (2gn,)y2. vF=fIk,/m
*, so ξN of the two-dimensional system is ξN=(5"μ/4rkBTem*)'r(2rns)
¥ Cp in 3 ¥ - (Equation 3) is found. Compared to ξN (CpKn) in the three-dimensional case, for example, when both n and nB increase by one digit, the effect is greater in the two-dimensional case, and it can be said that controllability improves accordingly.Also, increasing ξN For n + n
It is the same that B must be increased, but as mentioned above, in the case of a three-dimensional (bulk) semiconductor, if a large amount of dopant is doped to increase n, it becomes a scatterer and p decreases. As a result, ξN becomes smaller. However, in the case of two dimensions, this is not the case for the following reasons.

一般にバルク半導体のキャリア濃度nを増すためには、
これと同程度のドーパントをドーピングする必要があシ
、この結果前記のように移動度はこのドーパントによる
散乱によって小さくなる(前述のP形シリコンの場合*
 n=10  (7m  でμご60 am”/VS 
)のであるが、P形半導体の表面反転  4層中の2D
ECの場合、基板のキャリア濃度が元々小さくても2〜
10nmの狭い領域に自然に、あるいは電界によってキ
ャリアが集まる。このためキャリア17)面密度n、は
10’〜10”am−” (n ニ換算すると1018
cm−”以上)と大きく、又基板中の散乱体が元々少い
ため移動度μも大きい。更に、nBは外部からかけた電
界によって制御できる。
Generally, in order to increase the carrier concentration n of a bulk semiconductor,
It is necessary to dope the same amount of dopant, and as a result, the mobility decreases due to scattering by this dopant (in the case of P-type silicon mentioned above*
n=10 (7 m = 60 am”/VS
), but the surface inversion of the P-type semiconductor 2D in the 4 layers
In the case of EC, even if the carrier concentration of the substrate is originally small, it is
Carriers gather in a narrow region of 10 nm naturally or by an electric field. Therefore, the surface density n of the carrier 17) is 10'~10"am-" (1018 when converted to n2)
cm-'' or more), and the mobility μ is also large because there are originally few scatterers in the substrate.Furthermore, nB can be controlled by an externally applied electric field.

次に、本発明において、超伝導電極と2 DKGが形成
されている半導体層との接触がオーミックであることが
要求されるが、このオーミックの本発明における意味を
解説する。
Next, in the present invention, it is required that the contact between the superconducting electrode and the semiconductor layer in which the 2DKG is formed is ohmic, and the meaning of this ohmic in the present invention will be explained.

半導体と金属との接触がオーミックであるとは、その接
触部の電流電圧特性がオームの法則に従うものをいう。
An ohmic contact between a semiconductor and a metal means that the current-voltage characteristics of the contact conform to Ohm's law.

一般に金属と半導体の接触部には第14図のようなショ
ットキーバリアーや第15図のような酸化物バリアー、
そして両者のあわさったバリアー等が形成される。液体
ヘリウム温度(1気圧で4.2K)のような極低温では
このバリアーを通して流れる電流はトンネル効果による
ものが主であシ、その電流電圧特性は上に述べた意味で
オーミンクであり、これによる接触抵抗が発生する。
Generally, a Schottky barrier as shown in Fig. 14, an oxide barrier as shown in Fig. 15, etc. are used at the contact area between a metal and a semiconductor.
A barrier or the like is formed by the combination of the two. At extremely low temperatures such as liquid helium temperature (4.2 K at 1 atm), the current flowing through this barrier is mainly due to the tunnel effect, and its current-voltage characteristics are Ohmink in the sense mentioned above, and due to this Contact resistance occurs.

この抵抗はトンネル確率T・に反比例し、Tjはバコ リアーの高さ及び幅、特に幅に強く依存するから、接触
抵抗を下げて電流を多く流すためには、バリアー幅をう
すくする必要がある。これを素子にあてはめてみる。超
伝導臨界電流(最大超電導電流)■cと常伝導抵抗R,
との積は、Nb、Pb等の超伝導金属を電極2に使用し
た場合最大2mVのオーダーであシ、可観測という意味
からICとしては最小10μA程度必要と考えられるか
ら、RNとしてはZOOΩ以下が要求される。仮にRN
として、上記の接触抵抗だけを考え、超伝導電極2と反
転層5の2DECとの接触面積を5 nm x 110
0p (2DKGの厚さ×素子幅)とすると、接触抵抗
は9×10−グΩam”(、(xlo  0m)以下が
必要となる。
This resistance is inversely proportional to the tunneling probability T. Since Tj strongly depends on the height and width of the barrier, especially the width, it is necessary to make the barrier width thinner in order to lower the contact resistance and allow more current to flow. Let's apply this to the element. Superconducting critical current (maximum superconducting current) c and normal resistance R,
If a superconducting metal such as Nb or Pb is used for the electrode 2, the product of is required. Temporarily RN
Considering only the above contact resistance, the contact area between the superconducting electrode 2 and the 2DEC of the inversion layer 5 is 5 nm x 110
If 0p (thickness of 2DKG x element width), the contact resistance needs to be 9 x 10-gΩam'' (, (xlo 0m) or less).

本発明で言うところのオーミック特性とは、このような
小さい接触抵抗を持ったバリアー特性のことである。
The ohmic characteristics referred to in the present invention refer to barrier characteristics having such a small contact resistance.

〔実施例〕〔Example〕

(実施例1) 第1図に本発明の実施例の断面構造を示している。図に
おいて、1はP形InAs基板、2は超伝導電極、5は
反転層、6はスパッタ法や蒸着法によって形成されたS
iOや8102等の絶縁膜、7は金(Au)等の第三電
極である。
(Example 1) FIG. 1 shows a cross-sectional structure of an example of the present invention. In the figure, 1 is a P-type InAs substrate, 2 is a superconducting electrode, 5 is an inversion layer, and 6 is an S layer formed by sputtering or vapor deposition.
An insulating film such as iO or 8102 is used, and 7 is a third electrode made of gold (Au) or the like.

P形InAsの表面はキャリア濃度に関係なくn形に反
転してお9、この反転層中に2DECが形成される。第
2図に第1図の実施例の第三電極(ゲート)部位におけ
るバンド図を示している。図のようにP−InAiO弐
面はn形に反転し、該反転層の絶縁体との表面側に2 
DKGが発生している。該2 DEGのキャリア濃度n
は第三電極7にかける電圧vfにより制御され、それに
より2つの超伝導電極2間の2DKG中を流れる超伝導
電流を制御する。
The surface of P-type InAs is inverted to n-type regardless of the carrier concentration9, and 2DEC is formed in this inversion layer. FIG. 2 shows a band diagram at the third electrode (gate) portion of the embodiment shown in FIG. As shown in the figure, the second surface of P-InAiO is inverted to n-type, and 2
DKG is occurring. Carrier concentration n of said 2 DEG
is controlled by the voltage vf applied to the third electrode 7, thereby controlling the superconducting current flowing in the 2DKG between the two superconducting electrodes 2.

上述のようにP−InAsの表面はキャリア濃度に関係
なくn形に反転しておシ、この反転層中に2DECが形
成されるが、n反転層からP層へのトンネルによるリー
ク電流の存在を考えると、キャリア濃度は2〜3 x 
Io”am−”以下が望ましく、この場合4.2にでn
B= 2.5 X 1G”cm、” 、 p = 50
00 am”/VSが実現されておp (E、 Yam
aguchi : ExtendedAbstract
  of  the  1984  Internat
ional  Conferenceon 5olid
 5tal Devices  and Materi
als、Kobe。
As mentioned above, the surface of P-InAs is inverted to the n-type regardless of the carrier concentration, and 2DEC is formed in this inversion layer, but there is a leakage current due to tunneling from the n-inversion layer to the P layer. Considering that, the carrier concentration is 2 to 3 x
Io "am-" or less is desirable, in this case n in 4.2
B = 2.5 x 1G"cm," p = 50
00 am”/VS has been realized (E, Yam
aguchi: ExtendedAbstract
of the 1984 International
ional Conference 5olid
5tal Devices and Materi
als, Kobe.

(’84) 、 371参照)、ξNも0.19 pm
と長い。
('84), 371), ξN is also 0.19 pm
and long.

さらに、本実施例で、超伝導電極2と半導体1とが前述
のようにオーミックに接触する(半導体/超伝導体表面
での電子のトンネル確率Tjが大きい)ことが要求され
るが、この点に関して、P形InAs基板10表面の反
転層のn形I nAs層の金属に対するショットキーバ
リアー高は第3図に示すように常に負で、オーミック・
コンタクトを形成する。従って、半導体/超伝導体表面
での電子のトンネル確率TjはP形シリコン等に比べる
とずっと大きくなる。
Furthermore, in this embodiment, the superconducting electrode 2 and the semiconductor 1 are required to be in ohmic contact as described above (the tunneling probability Tj of electrons on the semiconductor/superconductor surface is large); Regarding the Schottky barrier height of the inversion layer on the surface of the P-type InAs substrate 10 with respect to the metal of the n-type InAs layer, as shown in FIG.
Form a contact. Therefore, the electron tunneling probability Tj on the semiconductor/superconductor surface is much larger than that of P-type silicon or the like.

このように、本実施例ではξNが長く、且つトンネル確
率Tjが大きいから、先に示した式2(二次元、三次元
を問わず成立)から、大きnIc(最大超伝導電流)が
得られることが明らかであろう。
In this way, in this example, since ξN is long and the tunneling probability Tj is large, a large nIc (maximum superconducting current) can be obtained from Equation 2 shown above (holds true regardless of two-dimensional or three-dimensional). That should be obvious.

電極間隔りとξNとの関係は、I)JE TRANSA
C−JTION  ON  ELKCTRON  DE
VICES  、VOL、  10−28 。
The relationship between electrode spacing and ξN is I) JE TRANSA
C-JTION ON ELKCTRON DE
VICES, VOL, 10-28.

NO,11、NOVEMBER1981,pp 139
4〜1397にLはξNの数倍乃至lO倍位までとれる
ことが示されている。
NO, 11, NOVEMBER1981, pp 139
4 to 1397 show that L can range from several times ξN to IO times.

本実施例において、このようなことから電極間隔りを約
0.5μmと長くとれ、そのため二端子構造はもちろん
、三端子構造の作成が可能とな夛、zDEG中に超伝導
電流が流れる二端子動作が可能であり、更に、半導体に
おけるNO8FETのように、電極7に加える電圧Vf
で前述のようにn8を変化させ、これによって二端子特
性を制御する。所謂三端子動作が行なえる。
In this example, for this reason, the electrode spacing can be set as long as about 0.5 μm, and therefore not only a two-terminal structure but also a three-terminal structure can be created. operation is possible, and furthermore, like a NO8FET in a semiconductor, the voltage Vf applied to the electrode 7
Then, n8 is changed as described above, thereby controlling the two-terminal characteristics. So-called three-terminal operation can be performed.

(実施例2) 第4図に示すのは、P形InAa基板1の半導体表面の
n型反転層5の上に、直接金属電極(第三電極)7t−
形成した例であシ、絶縁膜6の開口部に金属電極7が形
成されている。超伝導電極2に関しては実施例1と同様
である。
(Example 2) As shown in FIG. 4, a metal electrode (third electrode) 7t-
In this example, a metal electrode 7 is formed in the opening of the insulating film 6. The superconducting electrode 2 is the same as in the first embodiment.

第5図にゲート部(第三電極7)についてのエネルギー
バンド図が示されている。この場合、二端子動作として
は実施例1と同じであるが、三端子動作は異なる。すな
わち、この場合はMESFIT的、或いは電流注入によ
る三端子動作となる。
FIG. 5 shows an energy band diagram for the gate portion (third electrode 7). In this case, the two-terminal operation is the same as in the first embodiment, but the three-terminal operation is different. That is, in this case, MESFIT-like or three-terminal operation based on current injection is performed.

(実施例3) 第6図に示すのは、P−InAs基板1の表面にリッジ
(凸部)8を形成し、その両側に超伝導電極2ONl)
層を形成した二端子構造の例である。
(Example 3) Fig. 6 shows that a ridge (protrusion) 8 is formed on the surface of a P-InAs substrate 1, and superconducting electrodes 2ONl are formed on both sides of the ridge.
This is an example of a two-terminal structure in which layers are formed.

第9図に、そのI−V特性を示す。 図において、(a
)は直流電流を印加した時のI−V特性であシ、超伝導
電流が(1)の領域で流れており、Ql)は電圧状態で
ある。0)は10GHzのマイクロ波を照射した特性で
ある。なお、見易くするために(a) (b)の原点は
ずらして表示している。
FIG. 9 shows its IV characteristics. In the figure, (a
) is the IV characteristic when direct current is applied, superconducting current flows in the region (1), and Ql) is the voltage state. 0) is the characteristic of irradiation with 10 GHz microwave. Note that the origins in (a) and (b) are shown shifted for ease of viewing.

(実施例4) 第7図は、リッジ8を形成している他は実施例1と同等
なMIS構造三端子素子である。
(Example 4) FIG. 7 shows a MIS structure three-terminal element that is the same as Example 1 except that a ridge 8 is formed.

第10図に、本実施例においてゲート電圧を変えた時に
超伝導電流の変化すること(図中Icは最大超伝導電流
、 RNは常伝導抵抗)が示されている。
FIG. 10 shows how the superconducting current changes when the gate voltage is changed in this example (Ic in the figure is the maximum superconducting current and RN is the normal resistance).

(実施例5) 第8図に示す例は、MES構造三端子素子で、リッジ8
構造を備える他は実施例2の第4図と同等である。
(Example 5) The example shown in FIG. 8 is a three-terminal element with an MES structure, and the ridge
The structure is the same as that in FIG. 4 of the second embodiment except for the structure.

第11図は、本実施例で注入電流Ijを変えた時のIc
の変化を示し、図のようにIjによって超伝導電流が制
御されている。
FIG. 11 shows Ic when the injection current Ij is changed in this example.
As shown in the figure, the superconducting current is controlled by Ij.

(実施例6) 第n図はP形I nAs基板1の裏面にP形InA!1
とオーミック・コンタクトを形成する金属例えばAuと
Znの合金(Ausop+znto%)等で電極10を
形成した実施例である。電極10は接合ゲートに相当し
、電極10と電極2或いは7との間にかける電圧によっ
て、p−n接合(この場合n層は反転層)中の空乏層幅
を制御し、これによってn4を変化させる三端子動作を
行なう。なお、電極10と2の間に電圧をかける場合は
、電極7及び絶縁膜6は必要ない。
(Example 6) Figure n shows P-type InA on the back surface of the P-type InAs substrate 1! 1
In this embodiment, the electrode 10 is formed of a metal that forms an ohmic contact with the metal, such as an alloy of Au and Zn (Ausop+znto%). The electrode 10 corresponds to a junction gate, and the width of the depletion layer in the p-n junction (in this case, the n layer is an inversion layer) is controlled by the voltage applied between the electrode 10 and the electrode 2 or 7, thereby controlling n4. Perform three-terminal operation to change. Note that when applying a voltage between the electrodes 10 and 2, the electrode 7 and the insulating film 6 are not necessary.

以上実施例を示したが、本発明は、これに限るものでな
く、例えば表面反転層中に2次元電子ガス(2DKG 
)が生ずる他の半導体を用いることができ、また超伝導
電極材料もNb、Pb以外に種々の超伝導材料を用いる
ことができる。
Although the embodiments have been described above, the present invention is not limited thereto. For example, the present invention can include a two-dimensional electron gas (2DKG
) can be used, and various superconducting materials other than Nb and Pb can be used as the superconducting electrode material.

〔発明の効果〕〔Effect of the invention〕

以上のごとく、本発明は、P形半導体異面のn形反転層
に形成される2 DECによって二つの超伝導電極が結
合している半導体結合超伝導素子を提供するものであp
、2DEG中に超伝導電流が流れる二端子動作が可能で
あシ、シかも電極間隔りを従来の素子よシずつと広くと
れる利点がおる。更に、第三電極によシニ端子特性を制
御する、所謂三端子動作が行なえるものであり、本発明
によれば特性の優れた二端子或いは三端子素子が実現さ
れる。
As described above, the present invention provides a semiconductor-coupled superconducting element in which two superconducting electrodes are coupled by 2DEC formed in an n-type inversion layer of a P-type semiconductor with different surfaces.
, two-terminal operation in which a superconducting current flows through the 2DEG is possible, and the electrode spacing can be made wider than in conventional elements. Furthermore, it is possible to perform so-called three-terminal operation in which the multi-terminal characteristics are controlled by the third electrode, and according to the present invention, a two-terminal or three-terminal element with excellent characteristics can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は、それぞれ本発明の第1の実施例の断
面図、ゲート部位についてのバンド図及び超伝導電極部
位についてのバンド図、第4図及び第5図は、それぞれ
本発明の第2の実施例の断面図及びエネルギーバンド図
、第6図〜第8図は、本発明のそれぞれ第3〜第5の実
施例の断面図、 第9図〜第11図はそれぞれ本発明の実施例の素子のI
−V特性図、超伝導電流のゲート電圧による変化を示す
図及びICの注入電流依存性を示す図、第n図は本発明
の第6の実施例の断面図、第13図及び第14図は従来
の素子の断面図及びバンド図、 第15図は酸化物バリアーを示すエネルギーバンド図。 1・・・P形InAs基板 2・・・超伝導電極 5・・・(n形)反転層 6・・・絶縁膜 7・・・第3電極 8・・・リッジ ヒL−1 実施例1の断面図 1g1 図 エネルギーバンド2 第2日 第 3 図        実施例2の断面図第4図 エネルギーバンド図 第 5 図 実施例3の断面図 第 6 図 実R例4の断面図 第7図 実施例5のlFr面図 第80a 電圧V (5hV/div) I−V特性図 第9図 注入電流Ij(mA) ICの注入電流依存性fIホーf鍋 第11図 実施例6の#面図 第12図 従来例の断面図           従来例のエネル
髪−バンド図第13図      第14図 側ヒ物バリアー エネルギーバ〉ト図 第15 図
1 to 3 are a sectional view of a first embodiment of the present invention, a band diagram for a gate region, and a band diagram for a superconducting electrode region, and FIGS. 4 and 5 are a sectional view of a first embodiment of the present invention, respectively. The cross-sectional view and energy band diagram of the second embodiment of the present invention, FIGS. 6 to 8 are cross-sectional views of the third to fifth embodiments of the present invention, and FIGS. I of the element of the example of
-V characteristic diagram, diagram showing changes in superconducting current due to gate voltage, diagram showing dependence of IC injection current, Figure n is a sectional view of the sixth embodiment of the present invention, Figures 13 and 14 15 is a cross-sectional view and band diagram of a conventional element, and FIG. 15 is an energy band diagram showing an oxide barrier. 1...P-type InAs substrate 2...Superconducting electrode 5...(n-type) inversion layer 6...Insulating film 7...Third electrode 8...Ridghi L-1 of Example 1 Cross-sectional view 1g1 Figure energy band 2 Day 2 Figure 3 Cross-sectional view of Example 2 Figure 4 Energy band diagram Figure 5 Cross-sectional view of Example 3 Figure 6 Cross-sectional view of R example 4 Figure 7 Example 5 1Fr side view of 80a Voltage V (5hV/div) IV characteristic diagram 9th figure Injection current Ij (mA) IC injection current dependence fI Ho f pot 11th # side view of Example 6 FIG. 12 Cross-sectional view of the conventional example Energy band diagram of the conventional example Fig. 13 Fig. 14 Side barrier energy band diagram Fig. 15

Claims (4)

【特許請求の範囲】[Claims] (1)表面反転層中に2次元電子ガスが形成されている
P形半導体基板と、 該P形半導体基板の表面反転層とオーミックに接触して
いる二つの超伝導電極とが含まれることを特徴とする半
導体結合超伝導素子。
(1) Contains a P-type semiconductor substrate in which a two-dimensional electron gas is formed in a surface inversion layer, and two superconducting electrodes that are in ohmic contact with the surface inversion layer of the P-type semiconductor substrate. Features of semiconductor-coupled superconducting devices.
(2)前記P形半導体基板がP形InAs基板であるこ
とを特徴とする特許請求の範囲第1項記載の半導体結合
超伝導素子。
(2) The semiconductor-coupled superconducting device according to claim 1, wherein the P-type semiconductor substrate is a P-type InAs substrate.
(3)表面反転層中に2次元電子ガスが形成されている
P形半導体基板と、 該P形半導体基板の表面反転層とオーミックに接触して
いる二つの超伝導電極と、 該二つの超伝導電極間に備えられているMIS型、ME
S型又は接合型ゲートとを有することを特徴とする半導
体結合超伝導素子。
(3) a P-type semiconductor substrate in which a two-dimensional electron gas is formed in a surface inversion layer; two superconducting electrodes in ohmic contact with the surface inversion layer of the P-type semiconductor substrate; MIS type, ME equipped between conductive electrodes
A semiconductor-coupled superconducting device characterized by having an S-type or junction-type gate.
(4)表面反転層中に2次元電子ガスが形成されている
P形半導体基板と、 該P形半導体基板の表面反転層とオーミックに接触して
いる二つの超伝導電極と、 該P形半導体基板側に形成されたオーミック電極とを有
することを特徴とする半導体結合超伝導素子。
(4) a P-type semiconductor substrate in which a two-dimensional electron gas is formed in a surface inversion layer; two superconducting electrodes in ohmic contact with the surface inversion layer of the P-type semiconductor substrate; and the P-type semiconductor. 1. A semiconductor-coupled superconducting element comprising an ohmic electrode formed on a substrate side.
JP60012134A 1985-01-24 1985-01-24 Semiconductor coupled superconductive element Granted JPS61171180A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60012134A JPS61171180A (en) 1985-01-24 1985-01-24 Semiconductor coupled superconductive element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60012134A JPS61171180A (en) 1985-01-24 1985-01-24 Semiconductor coupled superconductive element

Publications (2)

Publication Number Publication Date
JPS61171180A true JPS61171180A (en) 1986-08-01
JPH0452632B2 JPH0452632B2 (en) 1992-08-24

Family

ID=11797053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60012134A Granted JPS61171180A (en) 1985-01-24 1985-01-24 Semiconductor coupled superconductive element

Country Status (1)

Country Link
JP (1) JPS61171180A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63228696A (en) * 1987-03-18 1988-09-22 Hitachi Ltd Electronic device
JPS6486575A (en) * 1987-06-17 1989-03-31 Hitachi Ltd Superconducting device
US5126315A (en) * 1987-02-27 1992-06-30 Hitachi, Ltd. High tc superconducting device with weak link between two superconducting electrodes

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5126315A (en) * 1987-02-27 1992-06-30 Hitachi, Ltd. High tc superconducting device with weak link between two superconducting electrodes
US5552375A (en) * 1987-02-27 1996-09-03 Hitachi, Ltd. Method for forming high Tc superconducting devices
US6069369A (en) * 1987-02-27 2000-05-30 Hitachi, Ltd. Superconducting device
JPS63228696A (en) * 1987-03-18 1988-09-22 Hitachi Ltd Electronic device
JPS6486575A (en) * 1987-06-17 1989-03-31 Hitachi Ltd Superconducting device

Also Published As

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JPH0452632B2 (en) 1992-08-24

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