JPS61171154A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61171154A
JPS61171154A JP60012013A JP1201385A JPS61171154A JP S61171154 A JPS61171154 A JP S61171154A JP 60012013 A JP60012013 A JP 60012013A JP 1201385 A JP1201385 A JP 1201385A JP S61171154 A JPS61171154 A JP S61171154A
Authority
JP
Japan
Prior art keywords
lead terminals
conductor
die pad
package
lead terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60012013A
Other languages
Japanese (ja)
Inventor
Hiroichi Ishida
博一 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60012013A priority Critical patent/JPS61171154A/en
Publication of JPS61171154A publication Critical patent/JPS61171154A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive to reduce the generation of leakage signals between adjacent lead terminals, by a method wherein a conductor is inserted between adjacent lead terminals of the package, and this conductor is fixed to the earth or a given potential. CONSTITUTION:A semiconductor pellet 11 is mounted by heating the die pad 12 of a package 1, and electrodes 11a are electrically connected to the wire bonding pads 9 of lead terminals 2-4 with conductor wires 10. Further, in order to fix the potential of the die pad 12 to a given potential, the wire bonding pad 9 of a terminal 2 is connected to the die pad 12 with a conductor wire 13. Since this device has the projection 12a of the die pad 12 fixed to the earth or a given potential inserted between the adjacent lead terminals 2-4, a leakage signal going to jump e.g. from lead terminal 4 to lead terminal 3 drops to the projection 12a of the die pad of low impedance, and similarly the leakage signal from the lead terminal 3 is difficult to jump to the lead terminal 4, resulting in the reduction in malfunction of the device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体ペレットをパッケージに搭載する半
導体装置に関し、主に高周波回路用のパッケージに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a semiconductor pellet is mounted on a package, and mainly relates to a package for a high frequency circuit.

〔従来の技術〕[Conventional technology]

第４図は従来技術により構成されたパッケージであり、
図において、ｌはセラミック、プラスチック等を材料と
したパンケージ本体、２〜４は該パフケージ本体１から
外方に延びる外部リード端子、７はリード端子取付は部
であり、太いリード端子２〜４をパッケージ本体１内の
断面積の小さいリード線に接続するためのリード端子固
定点である。８はグイパッドであり、半導体ペレットを
固定するための基板である。９はリード端子２〜４のパ
フケージ内部の先端に設けられ、半導体ペレットとリー
ド端子２〜４とを接続するためのワイヤポンディングパ
ッドである。Figure 4 shows a package constructed using the conventional technology.
In the figure, l denotes a pan cage body made of ceramic, plastic, etc., 2 to 4 are external lead terminals extending outward from the puff cage body 1, and 7 is a lead terminal mounting section, which connects thick lead terminals 2 to 4. This is a lead terminal fixing point for connecting to a lead wire with a small cross-sectional area inside the package body 1. Reference numeral 8 denotes a goup pad, which is a substrate for fixing a semiconductor pellet. A wire bonding pad 9 is provided at the tip of the lead terminals 2 to 4 inside the puff cage, and is used to connect the semiconductor pellet and the lead terminals 2 to 4.

第５図は上述したパッケージに半導体ペレット間で信号
を伝達する導体ワイヤであり、金又はアルミニウム等の
導体からなり、半導体ペレット１１よりの信号を取り出
すポンディングパッド電極１１ａとワイヤポンディング
パッド９とを接続するものである。１３は上記導体ワイ
ヤ１０と同じ材質で作られた導体であり、グイパッド８
を一定の電位に固定するためのものである。FIG. 5 shows a conductor wire for transmitting signals between semiconductor pellets in the above-mentioned package, and is made of a conductor such as gold or aluminum, and includes a bonding pad electrode 11a and a wire bonding pad 9 for extracting signals from the semiconductor pellet 11. It connects. 13 is a conductor made of the same material as the conductor wire 10, and the gui pad 8
This is to fix the voltage at a constant potential.

次に動作について説明する。Next, the operation will be explained.

今、例えばリード端子３から高周波信号が入力し、隣接
するリード端子４から出力を取り出す回路が構成されて
いる場合について考える。このとき本装置のパッケージ
において、上記リード端子３．４間の距離をｔ、パッケ
ージ本体１の比誘電率をε「、リード端子を横から見た
時の周波数に対する等価面積をＡ、真空誘電率を８０と
すると、上記リード端子３．４間の寄生容量Ｃは　Ｃ＝
この寄生容量Ｃによる洩れ信号がリード端子３に入力さ
れ、この洩れ信号は周波数に比例して大きくなり、その
ため正常な出力信号をリード端子４から取り出せなくな
る。Now, let us consider a case where a circuit is constructed in which a high frequency signal is input from the lead terminal 3 and output is taken out from the adjacent lead terminal 4, for example. At this time, in the package of this device, the distance between the lead terminals 3 and 4 is t, the relative permittivity of the package body 1 is ε'', the equivalent area for the frequency when the lead terminals are viewed from the side is A, and the vacuum permittivity is is 80, the parasitic capacitance C between the lead terminals 3 and 4 is C=
A leakage signal due to this parasitic capacitance C is input to the lead terminal 3, and this leakage signal increases in proportion to the frequency, so that a normal output signal cannot be taken out from the lead terminal 4.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このように従来の装置では、隣接するリード端子間の寄
生容量を通し、洩れ信号が発生することにより、誤動作
することがあった。As described above, conventional devices sometimes malfunction due to the generation of leakage signals through the parasitic capacitance between adjacent lead terminals.

この発明は上記のような問題点を解消するためになされ
たもので、隣接するリード端子間の寄生容量を通して洩
れ信号が発生するのを防止できる半導体装置を得ること
を目的とするものである。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device that can prevent leakage signals from occurring through parasitic capacitance between adjacent lead terminals.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、パッケージの隣接するリ
ード端子間に導体を挿入し、この導体をアース又は一定
電位に固定したものである。In the semiconductor device according to the present invention, a conductor is inserted between adjacent lead terminals of a package, and the conductor is fixed to ground or a constant potential.

〔作用〕[Effect]

この発明においては、パッケージの隣接するリード端子
間に導体を挿入し、この導体をアース又は一定電位に固
定するようにしたから、上記隣接するリード端子間の洩
れ信号の発生を減少できる。In this invention, since a conductor is inserted between adjacent lead terminals of the package and this conductor is fixed to ground or a constant potential, it is possible to reduce the occurrence of leakage signals between the adjacent lead terminals.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

虻 両図において、第５図と同一符号は同−又は相当部分を
示し、１２は半導体ペレット１１を固定するためのダイ
パッド、１２ａは該ダイパッド１２の突出部であり、こ
れはパッケージ本体１内の隣接するリード端子２〜４間
に挿入されており、ダイパッド１２の一部を突出させて
形成したものである。In both figures, the same reference numerals as in FIG. It is inserted between adjacent lead terminals 2 to 4, and is formed by making a part of the die pad 12 protrude.

第２図に示す本実施例装置は、第１図のパッケージのダ
イパッド１２を加熱し、この上に半導体ペレット１１を
搭載し、該ペレット１１の電極１１ａとリード端子２〜
４のワイヤポンディングパッド９とを金又はアルミニウ
ム等の導体ワイヤ１デイングパツド９とダイパッド１２
とを導体ワイヤ１３で接続することによって得られる。The device of this embodiment shown in FIG. 2 heats the die pad 12 of the package shown in FIG.
4 wire bonding pad 9 and conductor wire 1 of gold or aluminum etc.
This can be obtained by connecting them with a conductor wire 13.

この装置では、隣接するリード端子間にアース又は一定
電位に固定されたダイパッドの突出部を挿入したので、
上記リード端子間の洩れ信号の発生を減少できる０例え
ば、第３図に示すように、リード端子４からリード端子
３へ飛ぼうとする洩れ信号はインピーダンスの低いダイ
パッドの突出部１２ａに落ちてしまい、リード端子３へ
飛ぶ洩れ信号は少なくなる。、同様にリード端子３から
６洩れ信号もリード端子４に飛びにく（なり、装置の誤
動作は少なくなる。In this device, a protrusion of a die pad fixed to ground or a constant potential is inserted between adjacent lead terminals.
The occurrence of leakage signals between the lead terminals can be reduced.For example, as shown in FIG. 3, the leakage signal that attempts to jump from the lead terminal 4 to the lead terminal 3 falls on the protrusion 12a of the die pad, which has a low impedance. , the leakage signal to the lead terminal 3 is reduced. Similarly, the leakage signal from the lead terminal 3 is also less likely to reach the lead terminal 4, and the malfunction of the device is reduced.

なお、上記実施例ではｌパッケージに半導体ペレットを
１個搭載したものについて説明したが、１パツケージに
複数個のペレットを搭載したものにも本発明を同様に通
用できる。In the above embodiment, a case in which one semiconductor pellet is mounted in an l package has been described, but the present invention can be similarly applied to a case in which a plurality of pellets are mounted in one package.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る半導体装置によれば、パ
ッケージの隣接するリード端子間に導体を挿入し、これ
をアース又は一定電位に固定したので、上記リード端子
間に発生する洩れ信号を減少させることができ、端子間
の信号分離度が向上し、誤動作を防止できる効果がある
。As described above, according to the semiconductor device of the present invention, a conductor is inserted between adjacent lead terminals of the package and fixed to the ground or a constant potential, thereby reducing leakage signals generated between the lead terminals. This has the effect of improving signal separation between terminals and preventing malfunctions.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）　（ｂ）　（Ｃ）はそれぞれ本発明の一実
施例によ側面図及び正面図、第３図はその装置の隣接す
るリード端子と突出部を示す断面図、第４図（ａ）　（
ｂ）　（Ｃ）はそれぞれ従来のパッケージの平面図、側
面図及び正面図、第５図（ａ）　（ｂ）　（Ｃ）はそれ
ぞれ従来装置の平面図、側面図及び正面図である。 １１ａ・・・電極、１１・・・半導体ペレット、１・・
・ノ々ッケージ本体、２〜４・・・リード端子、１２・
・・グイパッド、１２ａ・・・突出部。 なお図中同一符号は同−又は相当部分を示す。1(a), 1(b), and 1(c) are a side view and a front view of an embodiment of the present invention, FIG. 3 is a cross-sectional view showing adjacent lead terminals and protrusions of the device, and FIG. 4 is a sectional view of the device. (a) (
b) (C) are a plan view, a side view, and a front view of a conventional package, respectively, and FIGS. 5(a), (b), and (C) are a plan view, a side view, and a front view, respectively, of a conventional device. 11a... Electrode, 11... Semiconductor pellet, 1...
・Nonokage body, 2 to 4...Lead terminal, 12・
... Gui pad, 12a... protrusion. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] （１）複数の電極を有する半導体ペレットをパッケージ
に搭載した半導体装置において、上記パッケージの隣接
する各々上記電極に接続されるリード端子間に挿入され
アース又は一定電位に接続された複数の導体を備えたこ
とを特徴とする半導体装置。(1) A semiconductor device in which a semiconductor pellet having a plurality of electrodes is mounted in a package, including a plurality of conductors inserted between lead terminals connected to each adjacent electrode of the package and connected to ground or a constant potential. A semiconductor device characterized by: （２）上記導体は上記半導体ペレットを固定するための
ダイパッドの突出部からなることを特徴とする特許請求
の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the conductor is a protrusion of a die pad for fixing the semiconductor pellet.
JP60012013A 1985-01-24 1985-01-24 Semiconductor device Pending JPS61171154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60012013A JPS61171154A (en) 1985-01-24 1985-01-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60012013A JPS61171154A (en) 1985-01-24 1985-01-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61171154A true JPS61171154A (en) 1986-08-01

Family

ID=11793707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60012013A Pending JPS61171154A (en) 1985-01-24 1985-01-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61171154A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574241B2 (en) * 1977-12-29 1982-01-25
JPS58190045A (en) * 1982-04-30 1983-11-05 Fujitsu Ltd Semiconductor device package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574241B2 (en) * 1977-12-29 1982-01-25
JPS58190045A (en) * 1982-04-30 1983-11-05 Fujitsu Ltd Semiconductor device package

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