JPS6117074A - Trouble detecting system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates more generally to an improved testing apparatus, and more particularly to an apparatus for testing, e.g. Or it relates to a so-called in-circuit test device for testing without disconnecting.

Various types of complex and expensive systems are commercially available for testing completed printed wiring circuit board assemblies of electrical devices. One type of system applies a test signal to the input of a powered-up printed circuit board assembly and a sequence of test signals formatted to initiate functional operation of the assembly to be monitored, and outputs of this assembly and others. The design is such that functional testing is performed by monitoring corresponding signals obtained from test nodes of. Another type of system, also called an in-circuit tester, is used for comprehensive functional testing of circuit board assemblies rather than for manufacturing defects, such as short circuits, faulty elements, incorrectly inserted elements or tolerances. Used to find stray elements. While it is true that such systems exist, they are designed to identify faults in most of the above categories before performing comprehensive functional testing of the assembled printed circuit board. There is also an undeniable need for relatively inexpensive test equipment with relatively limited uses. This requirement primarily stems from the fact that fault type analysis has revealed that most of the functional faults are due to the manufacturing defects mentioned above. It has been discovered that when preliminary elementary fault detection is performed based on the discovery of manufacturing defects, the overall functional test pass rate is greater than 90%.

Figures 1 and 2 of the accompanying drawings illustrate a known automatic fault detection system. The system of FIG. 1 includes a central processing unit 1 which, under the control of an operator unit 2, controls adapters 3 and scanners at selected circuit nodes of a printed circuit board (B, U, T,) to be tested. Controls the connection to the measuring device 5 through the switch matrix array. Adapter 3 is B.

Any conventional device 9 for contacting selected circuit nodes of U, T, including, for example, a vacuum-operated "nailbed" type coupler, the matrix array 4 is described later in connection with FIG. a plurality of selectively addressable switches configured to specify Bj U;
T.

It is possible to connect a constant current source and/or a voltage measuring device in the measuring device 5 through the adapter 3 at any circuit node of the measuring device 5 .

FIG. 2 shows the structure of the scanner switch matrix array 4. As shown, a constant current source 10 and a differential voltmeter 11, which constitute elements of the measuring device 5, are coupled to a plurality of switch networks 12 via corresponding buses. Each switch network 1 includes four field effect transistors 13.

Each also has a common connection gate 1 of FET pairs 15, respectively.
4. or provide a test point TP configured for injecting or accepting current in response to a control input to the common connection gate 16 of the FET pair 17. for example.

In operation, the values of the resistors connected between TPl and TP2 of the switch matrix are tested by means of suitable probes contacting the terminals of the corresponding resistors. One control input is applied to 14 to configure TP1 as the injection node, and gate 161 of FET pair 17 of switch network 122 associated with TP2: one control input is applied to configure TP2 as the current receiving node. be done. A current induced from the current source 10 is then applied through a resistor connected between TPl and TP2, and the voltage developed across this resistor is applied to the underside of the FET pair 15 associated with networks 1 and 21, respectively. Upper FB of FET pair 17 associated with FET and network 122
It is measured by a voltmeter 11 coupled to TPl and TP2 via T.

Although the central processing unit 1 has 9 important tasks of setting control inputs to the gates of the FET pairs 15 and 17 in conjunction with the timing operation of the measuring device 5, the overall system functionality is essentially digital. be. Just as the resistance of a resistor is measured by injecting a current pulse and measuring the resulting voltage, a capacitor is measured by measuring the voltage that the capacitor charges in response to a current pulse applied for a predetermined period of time. It can be measured by Similarly, the ability of diodes and the interelectrode characteristics of transistors can be checked, and the combination of parallel and series-parallel connected resistors, capacitors, and diodes can also be checked to ensure that current pulse characteristics (especially amplitude and duration) and measurement timing are appropriate. You can check by selecting . With this equipment, the printed circuit board under test is powered down for the duration of the test, and the overall functionality of the board assembly is tested, as well as the capabilities and tolerances of individual or collective elements on the board. The value is tested for pass/fail.

As explained above, the above-described fault detection system described in connection with FIGS. By conducting this preliminary test before the comprehensive functional test, you can significantly increase the passing rate of the comprehensive test. However, this device has significant limitations in its performance range. This constraint is mainly used in this switch matrix array as ζ2.

In one aspect of the invention, it is proposed to use a bidirectional switch arrangement within a switch matrix array.

In such a configuration.

One of its most important advantages is impedance profile technology, which measures the impedance at various frequencies by applying alternating current to the element to check the impedance characteristics of a device or network, that is, its response characteristics to a given stimulus applied. can be used to perform inductance and parallel and series-parallel network analysis as a performance test.

Accordingly, 8 a fault detection system for testing the capabilities of a device on a printed wiring board or the like in accordance with an aspect of the present invention defines test points for connection to nodes of the board at which each individual is to be tested; It also includes a matrix array of bidirectional current-conducting analog switch networks that can be connected to either a stimulation source or a reference (eg, ground) potential by control of the switch network, and at the same time to corresponding inputs of a measurement device.

The fault detection system of the present invention is further characterized in contrast to the prior art in that it includes a device for selectively connecting a plurality of stimulus sources to an array of switch networks. In the prior art, only a current source is provided, which is pulsed to induce voltage measurements.9 In the present invention, AC and DC current and voltage sources are used to test the condition of circuit boards and devices. used.

The analog switch network preferably includes four bidirectional analog transmit gates each. Although it can be constructed as a discrete field effect transistor circuit, it is preferably constructed in integrated circuit form. These four bidirectional analog transmit gates are connected together on one side to define the test points of the corresponding switch network, and on the other side define the four terminals that constitute the input/output terminals of the network. . Furthermore, the control and wholesale terminals of these four analog transmission gates are as follows.

are connected to each other, thereby defining two control terminals for this network, applying the appropriate input to a corresponding one of the two network control terminals, and applying the appropriate input to a corresponding one of the two network control terminals. Switched to a conductive state, the test points of this network are first connected to the stimulation source and then to the corresponding inputs of the measuring device. When the other network control terminal is addressed by the appropriate input, the test point of this network is in turn connected to ground and to another input of the measuring device. .

This switch network, consisting of four bidirectional analog transmission gates, is therefore:

four terminals, each of which can be selectively connected to a corresponding one of the stimulation source, reference potential and two measurement nodes, either the stimulation source and the first measurement node or the reference source and the second measurement node; It has a selectively connectable test point and two network control terminals that control which of two separate test points are available through this network.

Another aspect of the invention provides an apparatus for testing circuit boards for manufacturing defects, the apparatus comprising a body, a pluggable module removably insertable into the body.

An interface connector including a pin matrix array mounted on the plug-in module and a connector matrix array mounted on the body for providing a plurality of connections between the plug-in module and the body.

a circuit board having a plurality of probes for simultaneously probing selected circuit nodes of a circuit board received thereon for receiving a surface of a pluggable module; Contains the connections provided between the corresponding one.

Other aspects, features and advantages of the invention are as set out in the claims and read in the following description of an exemplary embodiment of a system according to the invention with reference to the drawings. This becomes even more obvious.

The embodiments of the invention described hereinafter are similar to the aforementioned prior art systems described in Figures 1 and 2 of the accompanying drawings, but this is due to the inherent bi-directional capabilities of the switch networks used. Designed to perform improved functions due to. Therefore, in the following explanation, 5
Emphasis will be placed on explaining the differences between the present invention and the prior art systems, and common features between the present invention and the prior art systems will only be touched upon in a very general manner.

FIG. 3 schematically shows a bidirectional switch network used in carrying out the present invention, which network includes 51,
32. It has four bidirectional switches, designated by reference numerals 33 and 34, which are connected to each other as shown.

and interconnected with +source, -source, test point (node) and two measurement terminals, respectively indicated by reference numbers 65 to 39. Furthermore, each switch 31
Control terminals 40 and 41 are provided for controlling the operation of switches 3 and 62 and switches 3 and 64. for example.

By selecting the control terminal 40, the switches 31 and 32 can be made conductive and the test point 67 can be connected to the stimulus + source terminal 5 and the "positive" measurement terminal 68. When control terminal 41 is selected.

Switches 33 and 34 are activated, and test point O 7 is connected to the - source terminal 66 and the "negative" measuring terminal 39.
connected to.

FIG. 3: The network shown is only one of many parallel (two-connected) networks.

These multiple networks individually stimulate their corresponding test points (nodes) via their control terminals + terminal 3
5 and measurement terminal 68 or one source (reference) terminal 36 and measurement terminal 39. Element 1 on a printed circuit board, for example a resistor whose resistance you wish to verify whether it is within a specified tolerance of its nominal value, is connected to one end of it with a probe coupled to a test point (node) of any switch network. by touching a probe coupled to a test point (node) of any other switch network at the other end, and controlling these two switch networks by addressing their appropriate control terminals. Connect one test point (node) coupled to one end of the resistor to a stimulus source (e.g., a constant current generator)
and one terminal of the voltage measuring device, and another test point (point eJ), which is also coupled to the other end of the resistor, to ground and the other terminal of this voltage measuring device. A current pulse applied from this stimulus source to ground through a resistor generates a corresponding voltage across this resistor, which is measured by a voltage measuring device to calculate the resistance of this resistor; If necessary, it can also be compared with its nominal value to determine whether this resistance value is within an acceptable tolerance range of the nominal value. Preferably, the addresses, timing of stimulation and The properties are placed under computer control.

Although FIG. 4 illustrates a practical configuration of the switch network of FIG. 3 in a manner similar to FIG. 2 which illustrates a prior art switch network.

Reference numbers used in FIG. 4 refer to the same elements as reference numbers used in FIG. As shown in FIG. 4, one individual switch, 31°32.33.34, is composed of one bidirectional analog transmitting gate, and these four gates are connected via an inverter to gates 1-31.32, 33°34
two control terminals 40 and 41 coupled to corresponding pairs of
connected to define.

In the configuration shown in FIG. and 32 are applied to the control terminal 41 of the switch network associated with test point '['P2 such as to make the switches 33 and 34 of this network bidirectionally conductive. Applying a corresponding input causes a current pulse to flow through the resistor, and a corresponding voltage generated across this resistor can be measured between measurement nodes 68 and 39. Similarly, other elements 1 e.g. Capacitors, dielectrics, diodes, transistors, etc. can also be used for current/voltage/frequency stimulation and/or
Alternatively, these combinations can be tested by selectively adding them and observing the resulting current/voltage response of the corresponding elements.

FIG. 5 shows the general circuitry of an exemplary system in accordance with the present invention. Reference numeral 51 designates a multiplexer comprising a plurality of switch networks as described above in connection with FIGS.
40' for controlling the address of
and 41, respectively, and the +source terminals 65. -source (reference) terminal 36. and the corresponding measurement terminals 68 and 39 of the switch network.
35', 36', 38' and 39' corresponding to . In order to minimize the number of connections required between the control computer and the control terminals 40 and 41 of the switch network, V,000 control terminals are typically selected in a practical embodiment of the invention. The address bus can and preferably uses serial-to-parallel conversion techniques. Source terminals 35' are selectively connected to voltage, current and frequency sources 53, 54 and 55, respectively forming part of the system, via switch devices 52 controllable from the system's central processing unit (not shown). It can also be connected to one external terminal. A standard resistor 56 in the voltage source line is used to make high value resistor measurements. The measuring terminals 38', 39' of the multiplexer 51 are connected to a high impedance buffer 58 and a differential amplifier 59 with reference number 5.
7, and the output of this instrumentation amplifier 57 is coupled via a bidirectional switch 66 to a predetermined determination of the acceptable element of the measuring element by comparison with ``high'' and ``low'' reference levels VH and VL. It is coupled to a window comparator device 60 to provide a corresponding input to a logic circuit 61 which provides a "high" within 1 "low" output representative of the relationship between the tolerance range and the measured value of that element.

The output of the metering amplifier 57 is also supplied to an analog-to-digital converter 63 which is supplied from the central processing unit via a switch device 64 which can be controlled by the direct output of the metering amplifier 57 or by the output of the RMS-DC converter 65. to the display data bus 62 via the display data bus 62. The switch 64 also connects the previously described test resistor 5 to measure the source current.
is connected to receive a signal representative of the voltage Vi induced during 6.

A digital-to-analog converter 67 selectively applies a negative reference voltage V- to the reference terminal 36' of multiplexer 51 via a bidirectional switch 68;
and switch 68 can be controlled from the central processing unit of the device.

FIG. 3 shows a modification of the circuit shown in FIG. 5 to allow measurement of the gain of a single transistor and the use of so-called guarding techniques in the analysis of multi-element networks.

As can be seen, the output of buffer amplifier 58 of FIG. is also added to a summing amplifier for summing the outputs of digital-to-analog converter 71 to induce and the collector of which is probed by a corresponding one of the circuit nodes 37 shown in FIG. 3 (i.e. 9, e.g. test points TP1 and TP2 shown in FIG.
An additional node 7 selected by one corresponding action of
probed by one of 2. With the transistor emitter and collector voltages set appropriately at node 37 and selector 69 set according to whether the transistor is an NPN or PNP transistor, digital-to-analog converter 71 will generate an additional current value. and establish a base condition for measuring the gain of this transistor.

The modified circuit configuration of FIG. 3 also allows measurements by guarding techniques. for example.

Resistors R and l- are connected between 'I'P1 and 'I'P2 in FIG. 4, and the resistors connected in series are connected to resistor R.
1 in parallel between TPl and TP2, the fifth
In the circuit configuration shown in the figure, it is difficult to measure the value of only R1 due to the influence of R2 and R3 connected in parallel.

However, in the configuration of FIG. 3, by coupling the junction of R2 and R6 to one of the test nodes 72,
Equivalent the potential on either side of R2 (or R3),
This allows R1 to be isolated and its value measured. .

By this method, it is possible to protect the resistor R1 from the influence of the parallel-connected series resistors R2 and R3.

FIG. 7 is a general diagram of a system according to the invention that is useful for understanding the principles behind the system. The multiplexer 51 described above connects a plurality of measurement nodes 1, 2 .
3...N, and control terminal selection input bus 40'.

41', and the aforementioned source node, reference (earth) node and two measurement nodes 35', 36''.

38' and 69' are provided. The measurement system designated by the reference numeral 60, which will be described more specifically in connection with FIGS. 5 and 3, originates from the central processing unit (not shown) of the system.

Measurement type (e.g. voltage stimulation, current stimulation.

Frequency stimulation), duration of stimulation pulses that should be used.

Responsive to input data representing the time period during which measurements are to be taken and high and low thresholds to which measurements are to be compared, the results of the measurements performed on the element provide a measurement output and an indication of the condition of the element.

FIG. 8 shows a perspective view of an exemplary fault detection device constructed according to the present invention, and FIG. 9 shows the lines in FIG.
A partial cross-sectional view taken along is shown. Referring first to FIG. 8, the apparatus is designed for tabletop use and includes a cast aluminum body 80 and a cast plastic cover 81.

This forms a housing with a central setback 82 for receiving a module 83. The module 86, as will be explained later, is dedicated to the particular circuit to be tested and has an interface connector 85 on its underside.

This is designed to mate with a complementary connector 85 provided at the bottom of the setback 82. The housing defined by base 80 and cover 81 contains the electronic circuitry and other elements of the device.

As shown, the cover 81 has an angled front surface which is connected to a control panel 86. which preferably uses membrane type switches. Paper roll printer87. It also includes an LCD display 88 for displaying operator instructions and other information. A flip-up lid 89 provides access to the hard disk and/or floppy disk drive.

The module 83 has a complementary connector section 84 within the setback section 82.
．． It consists of a rigid rectangular box with precise dimensions that allow the parts 85 to fit together, leaving enough room for them to be accurately positioned relative to each other. A pair of precisely shaped and precisely spaced holes 90 (one of which is shown in FIG. 9) is provided in the connector portion 84 and a corresponding precisely spaced hole 90 is provided in the connector portion 85 (one of which is shown in FIG. 9). A positioning member 91 (having a conical head mounted on a relatively hard shaft mounted in a positioned oil dashpot)
FIG. 8) is provided. When the connector parts 84, 85 are brought close to each other, the conical head of the nine member 91 fits into the hole 90, and then brings the two connector parts into correct position relative to each other.

Next, Fig. 9 is an enlarged sectional view taken along the lines ■...■ in Fig. 8.
Explain the diagram. Reference numeral 92 designates the circuit board to be tested, which is supported by a flexible membrane 94 on an insulating carrier plate 93 mounted within the module 83 of the apparatus. The carrier plate 93 has holes corresponding to the positions of probe pins 95 with a plurality of springs secured within a removable insulating floor plate 96, the position of the pins 95 within the plate 96 being determined by the configuration of the circuit board; 9 Circuit board 90 is drawn downwardly by a vacuum established within the apparatus described.

Diaphragm 94 flexes toward floorboard 96 such that pins 95 contact circuit nodes on printed circuit board 92 .

The apparatus for establishing the necessary vacuum within the apparatus for drawing circuit board 92 onto pins 95 is shown only schematically and is readily understood by those skilled in the art.

The pin 95 in the floor plate 96 has a corresponding connection pin 97 in the first
is surrounded by wires to be coupled to selected pins of a pin matrix array formed within the connector portion 84 of the connector.

The first connector section 84 has an insulating plastic support 98 in which is mounted a plurality of rows of terminal pins or "nails" 99, the shank of which are shown in FIG. Projecting from the upper surface of object 98, their heads are horizontal with the lower surface. for example.

It is also possible to provide thousands of pins 99 in the pin matrix array described herein making up connector portion 84. The cooperative I connector part 85 is an insulating plastic support 1
00, which is used to mount a connector matrix consisting of a plurality of rows of connector pins 101. Each of the connector pins 101 has a spring-loaded head that is contacted by the head of a corresponding one of the matrix array pins 99 provided within the connector portion 84. The pins 101 of the connector matrix extend into correspondingly located holes in the printed circuit board 102, and these are connected to the underside of the board 12 from FIGS. Surface-mounted integrated circuit device 1 that constitutes the electronic circuit of this system as described above
Connected to 03. This device can be mounted directly on the substrate 103 between the rows of pins 101, thus having minimal lead lengths and, as a result, minimizing stray resistance, stray capacitance, and stray inductance. can.

The configuration of FIGS. 8 and 9 allows the pin matrix array of the floor plate 96 and connector section 84 to be easily dedicated to a specific circuit board to be tested.

It is also particularly advantageous in that no additional equipment is required to modify the apparatus to test different circuit boards. The pin configuration established at the pin matrix array of connector portion 84 determines the connections made at the connector matrix of connector portion 85, which in turn determines the measurements of multiple switch circuit array 51 of FIGS. 5-7. Determine which of points 1 through N will be used to test a particular printed circuit board.

The arrangement of FIGS. 8 and 9 utilizes a vacuum to lower the circuit board to be tested in the direction of the probe pins, and for this purpose the vacuum supply device 1 is shown schematically and explanatoryly in FIG.
04 and seal 105 are required.

Although a vacuum-powered configuration is of course more preferred, it is also possible to bring the circuit board to be tested into contact with the probe pins by physical means.

By screening printed circuit boards and the like for out-of-tolerance elements, incorrectly wired elements (e.g. diodes connected in the wrong direction), lossy elements before performing these comprehensive functional tests, A fault detection system has been described for use in locating wiring faults (e.g., "U" solder connections), etc. The system according to the present invention performs such fault detection operations in a manner similar to that found in the prior art. , can be accomplished simply by applying pulses from a constant current source and measuring the voltage response at appropriate times (1. Since the system according to the invention uses a switching device that can conduct in both directions, a.
The c-stimulus can be used alone or in combination with the d- and c-stimuli, and therefore, as mentioned above, it is possible to measure impedance at various frequencies, which has the advantage of impedance profiling (characteristic recognition). ) technique allows analysis of inductance and parallel networks. The central processing unit included here controls the generation of the appropriate stimuli, as well as the loading of the generated stimuli onto the circuit nodes of the board undergoing testing.
By performing the response data collection and analysis of the response data necessary to detect failures, the present invention thus provides a powerful yet cost effective production support system.

As will be clear to those skilled in the art, a manufacturing defect analysis device according to the present invention can be used with the automatic test device disclosed in our British Patent Specification No. 8429657 filed 23 November 1984. The manufacturing defect analyzer constitutes one of the modules of the automatic test equipment.

[Brief explanation of the drawing]

1 and 2 show a known automatic fault detection system; FIG. 3 shows a schematic diagram of a bidirectional switch network used in the system according to the invention; FIG. 4 shows the network of FIG. 3 shows the array in as much detail as FIG. 2 which shows the prior art system described above; FIG. 5 is a partial circuit diagram of an exemplary embodiment of the invention; FIG. shows a circuit diagram that is a modification of the circuit diagram of FIG. 5; FIG. 7 is a simplified block diagram illustrating the test basis and implementation of the embodiments of FIGS. 5 and 3; FIG. 8 is a circuit diagram according to the present invention. 9 is a diagram schematically illustrating one possible physical configuration of an automatic fault detection system; and FIG. 9 shows a schematic cross-sectional view taken along lines . An engraving of one song (no changes to the content)

Claims (1)

Claims: 1. A fault detection system for testing the capabilities of a device on a printed circuit board or the like, the system comprising an array of bidirectional current conducting switch networks, each network being tested. defines a test point for connection to a node on a printed circuit board or the like which receives the signal, and which can be connected to a stimulus source or reference (e.g., earth) potential under the control of this corresponding switch network; A fault detection system characterized in that it can be connected to corresponding inputs of a measuring device at the same time. 2. The fault detection system according to claim 1, wherein each of the switch networks includes one analog switch network. 3. A fault detection system according to claims 1-2, wherein each of the switch networks includes four bidirectional current-conducting analog switches, each switch having a current-conducting current of the corresponding switch. a control electrode to which an input for controlling a state is applied, a current conduction path of a first switch of the switch being connected between the stimulus source terminal and the corresponding test point; a selection terminal of the switch, a current conducting path of a second switch of the switch being connected between the test point reference (e.g., ground) potential terminals, and a control electrode of the switch being connected to the second selection terminal of the switch. , a current conduction path of a third switch of the switch is connected between the test point and the first measurement terminal and a control electrode of the switch is connected to a third selection terminal, and a fourth of the switch The current conduction path of the switch is connected to the test point and the second
A fault detection system, characterized in that the control electrode of the switch is connected between the measurement terminals of the switch and the fourth selection terminal. 4. In the fault detection stem according to claim 3, the first and third selection terminals are connected in common,
The failure detection system is further characterized in that the second and fourth selection terminals are commonly connected. 5. A fault detection system according to claims 3 to 4, wherein each of the switches includes a bidirectional analog transmission gate. 6. In the fault detection system according to claim 3, 4, or 5, the stimulation source terminal and the reference potential terminal, and the first measurement terminal and the second measurement terminal are selectively connected. a multiplexer for connecting to said switch network, a switch device for selecting the output of either of said measuring terminals according to the type of polarity of said transistor for measuring the gain of a transistor, said selected measuring terminal; a device for coupling an additional current to the output to produce a base input to the transistor, and an emitter and a connector of the transistor coupled to the test point established by a corresponding one of the switch networks; A fault detection system comprising a device for applying the base input to a base. 7. A fault detection system according to any of the foregoing claims, wherein a data processing device is coupled to the array of switch networks for providing control inputs thereto; A fault detection system characterized in that a state of the switch network associated with a test point is selectively controlled. 8. A fault detection system according to any of the preceding claims, characterized in that it includes a switching device for selectively coupling a plurality of stimulation sources to the array of switch networks. . 9. The failure detection system according to claims 7 and 8, wherein the operation of the switch device is controlled by the data processing device. 10. A fault detection system according to claims 9-9, characterized in that the plurality of stimulation sources includes at least a DC voltage source, a constant current source, and a variable frequency signal generator. Detection system 11, a fault detection system according to any of the preceding claims, characterized in that the measuring device includes a device for providing an indication of the relationship of the measured value of the element to a predetermined tolerance range. fault detection system. 12. Fault detection system according to any of the preceding claims, characterized in that the measuring device includes a device for displaying the response of a test element or group of elements to a test stimulus. system. 13. A fault detection system according to any of the preceding claims, in which the measuring device responds to a predetermined combination of stimuli applied to the element or combination of elements to be tested. A fault detection system comprising: a characteristic recognition device for recognizing a response indicating that the operation of the fault detection system passes. 14. A fault detection system according to any of the preceding claims, wherein a plurality of probe members arranged for making contact with circuit nodes of a printed circuit board, on an electrically insulating carrier; a pin matrix array consisting of a plurality of pins mounted on a pin; a device for connecting each of the probe members to a selected one of the pins; a connector matrix comprising a plurality of connector pins including pins configured to connect the connector pins to corresponding points of the test points defined by the array of the switch network; A fault detection system featuring: 15. The fault detection system of claim 14, wherein the pins of the connector matrix are mounted in a plurality of rows on a printed circuit board or the like;
A fault detection system further characterized in that said switch network is comprised of integrated circuit devices mounted between said columns and connected to said pins. 16. A fault detection system as claimed in claim 15 without claim 14, wherein the plurality of probe members are mounted in a first device part that is also used to mount the pin matrix array. and the connector matrix is mounted within a second device section, the device being capable of assembling different configurations of the probe member and the pin matrix array with the first device section for testing different printed circuit boards. , and which can be assembled into operative relationship with the second device portion without modification of the second device portion. 17. The fault detection system of claim 16, wherein the first device portion includes a modular element received within a receiving recess in the second device portion;
A fault detection system characterized in that the pins of the pin matrix array contact a corresponding one of the pins of the connector matrix when the modular element is inserted into the recess. 18. The fault detection system of claim 17, wherein the first device portion includes a rigid rectangular housing having an upper surface forming a receiving surface for a circuit board under test; A circuit board to be tested received thereon is movable to migrate toward the interior of the housing, the plurality of probe members positioning the receiving surface of the circuit board in a predetermined circuit position when the circuit board is thus transferred. a plurality of pins with springs mounted in an insulating carrier covering in a pattern such that the nodal points are contacted, the pin matrix array being mounted on a surface opposite the receiving surface of the housing; has a head portion that projects inside the housing and is accessible from the outside of the housing;
further comprising a first device portion including a plurality of conductive wires for interconnecting the probe pins with selected pins of the pin matrix array projecting inside the housing;
and an upper surface with a recess dimensioned for the second device portion to receive the first device portion and for interfacing with the pin matrix when the first device portion is inserted into the recess. a lower surface on which the connector matrix is mounted, the connector matrix having a plurality of spring-loaded pins, each of the pins of the pin matrix being provided within the first device portion; A fault detection system characterized in that it is designed to come into contact with the head of a corresponding pin. 19. In the fault detection system according to claim 18, when the first device part is inserted into the retracted part of the second device part on the pin matrix array and the connector matrix array. a pair of circular members each designed to engage a corresponding one of the pair of probes; A fault detection system comprising: 20. An electrical interface device for electrically connecting a circuit board under test to a test device, the configuration of the probe within a carrier so that the device can engage corresponding circuit contacts of the board under test. a plurality of electrical probes, determined in relation to the arrangement of the circuit board, such that this engagement is achieved when the circuit board and the carrier are brought into a predetermined juxtaposition with each other; a pin matrix array having a plurality of terminal pins mounted on the substrate, and a device for connecting the probe to a corresponding one of the terminal pins, and a plurality of connectors mounted on an electrically insulating support. a connector matrix having terminals, each of the connector terminals arranged in contact with a corresponding one of the terminal pins when the pin matrix array and the connector matrix are brought into a predetermined juxtaposition with each other; , the connector terminals are mounted on a printed circuit board or the like, and an integrated circuit device forming part of the test apparatus or the like is mounted on the circuit board or the like and coupled to the connector terminals; An electrical interface device characterized in that connection between the connector terminal and the integrated circuit device is thereby achieved with short leads. 21. An electrical test device comprising an electrical interface device according to claim 20, wherein the test device has a first module device portion and a second setback portion for receiving the first module device portion. the first module part has a receiving surface for a circuit board to be tested, and the probes detect relative transitions between the circuit board on the receiving surface and the plurality of probes. a device for achieving engagement with a node, the probe is provided with a spring, and the pin matrix array is mounted on a second surface of the first module device portion with the heads of the pins on the second surface. the connector matrix of the second device section is mounted on the face of the setback and the connector matrix is mounted in mating manner with a corresponding one of the connector terminals of the connector matrix; An electrical test device characterized in that it consists of a plurality of terminal pins having springs mounted in an insulating carrier. 22, a plurality of bidirectional current conducting switch networks each capable of controlling the connection of a test point to a stimulus source or a reference source and simultaneously to a measurement device, including a plurality of bidirectional current conducting switch networks, the stimulus source and the reference source and the measurement device; a housing part containing a data processing device for controlling the operation of said switch network operating under the control of said housing, a test to be subjected to a receiving surface of a modular device designed to be removably received within a recess of said housing; a receiving circuit board, a plurality of probes for probing circuit nodes of the circuit board associated with the receiving surface, one provided on the module apparatus and the other provided on the housing portion within the recess; A circuit board fault detection device consisting of an interface connector consisting of two parts, wherein one connector part includes a pin matrix array with selected pins coupled to a corresponding one of the probes; a portion includes a connector matrix array, each connector being designed to mate with a corresponding one of the pins of the pin matrix array when the modular device is inserted into the housing recess, each connector having a test point; A circuit board fault detection device comprising: a circuit board failure detection device configured to be connected to a corresponding one of the switch networks; 23. A housing forming a recess for receiving a circuit board receiving module, a circuit board receiving module removably received in the recess, an array of bidirectional current conducting switch networks, a stimulation source and a device for establishing a reference potential; and a data processing device provided within the housing, wherein the circuit board receiving module has a receiving surface thereon for receiving a circuit board for probing circuit nodes of the circuit board. a first interface connector comprising a plurality of electrical probes mounted within an insulating carrier in a predetermined configuration and a pin matrix array with selected ones of the pins connected to corresponding ones of the probes; a second interface connector portion comprising a connector matrix array, the first interface connector portion being accessible from outside the receiving module, and a second interface connector portion comprising a connector matrix array provided in the recessed portion; has a plurality of connector pins each mating with a corresponding one of the pins of the pin matrix array when received within the recessed portion, each of the connector pins being tested via the first interface connector portion. An array of bidirectional current conducting switch networks is provided within the housing and each coupled to a corresponding one of the connector pins, forming a test point of the device connected to a node of the circuit board. selectively connected to a stimulus source or reference potential and simultaneously to an input of a measurement device, the measurement device being provided with the stimulation source provided within the housing and the device for establishing the reference potential. , the data processing device within the housing selectively controls the state of the switch network coupled to the circuit node of the circuit board under test via the first and second interface connectors and the probe. 1. A circuit board failure detection device characterized in that a predetermined electrical stimulation is applied to a circuit element coupled to the node, thereby testing the ability of the element.