JPS61170053A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS61170053A
JPS61170053A JP60010112A JP1011285A JPS61170053A JP S61170053 A JPS61170053 A JP S61170053A JP 60010112 A JP60010112 A JP 60010112A JP 1011285 A JP1011285 A JP 1011285A JP S61170053 A JPS61170053 A JP S61170053A
Authority
JP
Japan
Prior art keywords
lead frame
lead
leads
machined
plate thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60010112A
Other languages
Japanese (ja)
Inventor
Toshinori Tanaka
田中　俊範
Takayasu Handa
半田　隆保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60010112A priority Critical patent/JPS61170053A/en
Publication of JPS61170053A publication Critical patent/JPS61170053A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To load a semiconductor chip, which could not have been loaded, on a lead frame having a large number of pins by previously thinning plate thickness up to 30-70% before forming a pattern for an inner lead. CONSTITUTION:A lead frame is manufactured by using a 42% Fe-Ni alloy in 0.25mm plate thickness, but only the material plate thickness of sections corresponding to inner leads 2 is machined through etching to approximately 0.125+ or -0.01mm of approximately 50% reduction first, and a pattern for the lead frame is machined. A tab 1 is not machined at that time Outer leads 3, frames 4 and tie bars 6 are left naturally as they are 0.25mm thick. When shaping patterns for the inner leads, a 42% Fe-Ni alloy in approximately 0.125mm plate thickness is machined through etching, thus extremely thinning the leads at the pitches of the noses of the inner leads of minimally approximate ly 0.25mm, then acquiring the lead frame having a pattern of narrow lead intervals.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に使用されるリードフレ
ームに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame used in a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

従来から半導体装置用リードフレームは、帯状の金属板
を用いてプレス法あるいはエツチング法により製造さ扛
、第４図の平面図に示すように、半導体チップの搭載さ
れるタブ１、このタブの周囲に伸びたインナーリード２
、及び外部に伸びたアクタ−リード３など、全ての部分
が同一の厚さで構成されていた。４ｉ１ｔ７レーム、５
はガイドホール、６はタイバーである。Conventionally, lead frames for semiconductor devices have been manufactured using a band-shaped metal plate by a pressing method or an etching method.As shown in the plan view of FIG. Inner lead 2 extended to
, and the actor lead 3 extending outward, all parts were constructed with the same thickness. 4i1t7reme, 5
is a guide hole, and 6 is a tie bar.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の同一厚さのリードフレームは、封止樹脂
よシ導出されるアウターリードの変形及び破断が生じな
いように所定の強度が要求されることから、一般的に０
，１５〜９．３１１１厚さのものが使用されて米た。一
方、インナーリードは、アウターリードの場合と異なシ
、タブからある適当な距離にインナーリード先端を配置
する必要があり、微細な加工が要求されるものである０
微細なインナーリードパターンを形成するためには、材
料厚さを薄くする必要があり、材料厚さを薄くすること
によシリードピッチは小さくできるようになるが、リー
ドフレームの材料全体の厚さを薄くしたのではアウター
リード強度が満足さｎないこととな夛、更に半導体チッ
プの熱放散性の低下金も招いてしまうことになるので、
上記０．１５〜０．３１１４Ｍ厚さが使用さｎて米た。The above-mentioned conventional lead frames of the same thickness generally have a thickness of 0 because a certain level of strength is required to prevent deformation and breakage of the outer leads led out from the sealing resin.
, 15 to 9.3111 thick were used. On the other hand, inner leads differ from outer leads in that the tip of the inner lead must be placed at an appropriate distance from the tab, and requires fine processing.
In order to form a fine inner lead pattern, it is necessary to reduce the material thickness, and by reducing the material thickness, the series lead pitch can be reduced, but the overall thickness of the lead frame material If the outer lead strength is made thinner, the strength of the outer leads will not be satisfactory, and furthermore, the heat dissipation performance of the semiconductor chip will deteriorate.
The above thickness of 0.15~0.3114M was used.

従って、６４ピン以上のような多ピンになるにつｎて、
タブが小さい場合には、インナーリード先端の最小ピッ
チに限界があるために、インナーリード先端がタブから
遠い位置に配置さ扛ることとなシ、半導体チップ電極と
インナーリードとを接続するボンディングワイヤが長く
なって変形し易くなり、ついにはワイヤ切れあるいは隣
接インナーリードとの短絡不良を多発するという欠点が
あった。Therefore, when increasing the number of pins such as 64 pins or more,
If the tab is small, there is a limit to the minimum pitch of the inner lead tip, so the inner lead tip must be placed far from the tab and the bonding wire connecting the semiconductor chip electrode and the inner lead. The wire becomes long and easily deforms, resulting in frequent wire breakage or short-circuit failures with adjacent inner leads.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は樹脂封止さ牡るインナーリード部のリードフレ
ーム厚を他の部分よりも薄くすることによシ、インナー
リード先端位置をタブから遠ざけることなくインナーリ
ードのピッチ金小さくできるようにしたもので、タブは
半導体装置の熱放散性を低下させないために薄くしてい
ない。The present invention makes it possible to reduce the pitch of the inner lead without moving the tip of the inner lead away from the tab by making the lead frame thickness of the resin-sealed inner lead part thinner than other parts. The tab is not made thin in order not to reduce the heat dissipation properties of the semiconductor device.

〔実施例〕〔Example〕

次に実施例を用いて本発明をさらに詳細に説明する。 Next, the present invention will be explained in more detail using Examples.

第１図は本発明の一実施例の１４ピン樹脂封止型半導体
装置用リードフレームの斜視図である。FIG. 1 is a perspective view of a lead frame for a 14-pin resin-sealed semiconductor device according to an embodiment of the present invention.

板厚０．２５１１厚の４２％Ｆｅ−Ｎｉ合金を用いてリ
ードフレームを製造するものであるが、まずインナＩＪ
−ド２に和尚する部分の材料板厚のみを約（資）％４ｃ
の０．１２５±０．０１闘根度にエツチング加工し、そ
の後にリードフレームパターンを加工した０この場合、
タブ１は薄く加工せず、　０．２５ＫＩＩのままとした
。もちろん、アクタ−リード３、フレーム４、タイバー
６も０．２５３＋＊のままである０次いで、インナーリ
ードパターン形成の際には、板厚が約０．１２５龍の４
２％Ｆｅ−Ｎｉ合金の加工をエツチングで実施し、その
結果、インナーリード先端のピッチが最小的０．２５ｊ
ＥＩと非常にリードが細く、またリード間隔の狭いパタ
ーンを有するリードフレームが得らｎた０このように、
インナーリード先端の最小ピッチは、リードフレームの
板厚によって決ってくるので、インナーリード先端部分
の板厚は、必要とするピン数に応じ、またリードフレー
ム強度あるいは加工精度などを考慮して、板厚の３０〜
７０チの範囲で設定すｎばよい０ 第１図のリードフレームは、インナーリードの表の面金
加工して薄くした場合であシ、半導体装置に組立てら扛
た場合は第２図の断面図のようになるが、裏面を薄くし
た場合も同様な効果を得ることができるもので、その場
合は第３図の断面図に示したような半導体装置を得るこ
とが可能である。第２図、第３図において、７は半導体
チップ、８はボンディングワイヤ、９は樹脂である０〔
発明の効果〕 以上説明したように、本発明はインナーリードパターン
形成前に前もって板厚ｔ−３０％〜７０％に薄くするこ
とによシ、インナーリードのパターンをより微細にコン
トロールすることが可能であり、多ピンにおけるリード
フレームで、従来不可能であった小さな半導体チップの
搭載が、半導体装置の製造不良率を高めることなく、ま
た信頼性を低下させることなく可能となった。さらに、
半導体チップ搭載部であるタブは、薄くしていないので
、半導体チップの熱放散性を損なうことがない０尚、本
発明の実施例では、１４ピンの例金上げたが、本発明は
ビン数に制限なく使用可能であ夛、特に６４ピン以上の
多ピンの場合に有効となるものである。The lead frame is manufactured using a 42% Fe-Ni alloy with a plate thickness of 0.2511. First, the inner IJ
- Only the thickness of the material plate of the part to be restored to De 2 is approximately (capital)% 4c
In this case, the lead frame pattern was etched to a depth of 0.125±0.01.
Tab 1 was not made thinner and was left as 0.25KII. Of course, the actor lead 3, frame 4, and tie bar 6 also remain at 0.253+*.Next, when forming the inner lead pattern, the plate thickness is approximately 0.125+*4.
Processing of 2% Fe-Ni alloy was carried out by etching, and as a result, the pitch of the inner lead tip was reduced to a minimum of 0.25j.
In this way, a lead frame with very thin leads and a pattern with narrow lead spacing was obtained.
The minimum pitch of the tips of the inner leads is determined by the thickness of the lead frame, so the thickness of the tips of the inner leads should be determined according to the number of pins required and taking into account the strength of the lead frame and processing accuracy. Thickness 30~
The lead frame shown in Figure 1 is the case where the surface of the inner lead is processed to be thinner, and the cross section shown in Figure 2 is the case when it is assembled into a semiconductor device. As shown in the figure, the same effect can be obtained even if the back surface is made thinner, and in that case, it is possible to obtain a semiconductor device as shown in the cross-sectional view of FIG. 3. In FIGS. 2 and 3, 7 is a semiconductor chip, 8 is a bonding wire, and 9 is a resin.
[Effects of the Invention] As explained above, the present invention enables finer control of the inner lead pattern by thinning the plate thickness to t-30% to 70% before forming the inner lead pattern. With a multi-pin lead frame, it is now possible to mount a small semiconductor chip, which was previously impossible, without increasing the manufacturing defect rate of semiconductor devices or reducing reliability. moreover,
Since the tab, which is the semiconductor chip mounting part, is not made thin, it does not impair the heat dissipation of the semiconductor chip.In addition, in the embodiment of the present invention, a 14-pin metal is used as an example, but the present invention It can be used without any limitation, and is particularly effective in cases where the number of pins is 64 or more.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例のリードフレーム斜視図、第２
図及び第３図はそれぞｎ本発明のリードフレームを使用
した半導体装置の断面図、第４図は従来の同一厚さで構
成されているリードフレームの平面図である。 １・・・・・・タブ、２・・・・・・インナーリード、
３・・・・・・アウターリード、４・・・・・・フレー
ム、５・・・・・・ガイドホール、６・・・・・・タイ
バー、７・・・・・・半導体チップ、８・・・・・・ボ
ンディングワイヤ、９・・・・・・樹脂。 代理人　弁理士　　内　　原　　　　音第　１　図 華　２　圀 茅　３　圀FIG. 1 is a perspective view of a lead frame according to an embodiment of the present invention, and FIG.
3 and 3 are respectively sectional views of a semiconductor device using the lead frame of the present invention, and FIG. 4 is a plan view of a conventional lead frame constructed with the same thickness. 1...Tab, 2...Inner lead,
3... Outer lead, 4... Frame, 5... Guide hole, 6... Tie bar, 7... Semiconductor chip, 8... ...Bonding wire, 9...Resin. Agent Patent Attorney Otodai Uchihara 1 Zuka 2 Kokuhaya 3 Koku

Claims (1)

【特許請求の範囲】[Claims] 樹脂封止型の半導体装置に使用するリードフレームにお
いて、樹脂封止されるインナーリード部の板厚が他の部
分よりも薄く形成されていることを特徴とする半導体装
置用リードフレーム。A lead frame for use in a resin-sealed semiconductor device, characterized in that an inner lead portion to be resin-sealed is thinner than other portions.
JP60010112A 1985-01-23 1985-01-23 Lead frame for semiconductor device Pending JPS61170053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60010112A JPS61170053A (en) 1985-01-23 1985-01-23 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60010112A JPS61170053A (en) 1985-01-23 1985-01-23 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS61170053A true JPS61170053A (en) 1986-07-31

Family

ID=11741228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60010112A Pending JPS61170053A (en) 1985-01-23 1985-01-23 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS61170053A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02229457A (en) * 1989-03-02 1990-09-12 Hitachi Ltd Lead frame, manufacture thereof and semiconductor device using same
WO1996005612A1 (en) * 1994-08-09 1996-02-22 National Semiconductor Corporation A fine pitch lead frame and method for manufacturing same
EP0849794A1 (en) * 1996-12-20 1998-06-24 Texas Instruments Incorporated Fine pitch lead frame
EP0921562A2 (en) * 1997-10-28 1999-06-09 Texas Instruments Incorporated Improvements in or relating to lead frames
US7102216B1 (en) * 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
WO2011083368A1 (en) * 2010-01-05 2011-07-14 Nxp B.V. Delamination resistant semiconductor devices

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02229457A (en) * 1989-03-02 1990-09-12 Hitachi Ltd Lead frame, manufacture thereof and semiconductor device using same
WO1996005612A1 (en) * 1994-08-09 1996-02-22 National Semiconductor Corporation A fine pitch lead frame and method for manufacturing same
EP0849794A1 (en) * 1996-12-20 1998-06-24 Texas Instruments Incorporated Fine pitch lead frame
EP0921562A2 (en) * 1997-10-28 1999-06-09 Texas Instruments Incorporated Improvements in or relating to lead frames
EP0921562A3 (en) * 1997-10-28 2002-06-05 Texas Instruments Incorporated Improvements in or relating to lead frames
US6635407B1 (en) 1997-10-28 2003-10-21 Texas Instruments Incorporated Two pass process for producing a fine pitch lead frame by etching
US7102216B1 (en) * 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
WO2011083368A1 (en) * 2010-01-05 2011-07-14 Nxp B.V. Delamination resistant semiconductor devices

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