JPS61169049A - Digital communication system - Google Patents

Abstract

PURPOSE:To improve the error rate by converting a location of a carrier to a DSK signal where a phase shift of +pi radian or -pi radian per 1 time slot is given in response to a binary information symbol to attain a correct demodu lated output to a symbol subject to multiplex interference. CONSTITUTION:A modulation circuit of the digital communication system consists of a DSK-ENC1, DBMs2,3 and a PC4, and the 1st symbol of the binary information symbol of a prescribed time slot undergoes phase shift by +pi/2 radian each twice consecutively at each 1/2 time slot. Further, the 2nd symbol is phase-shifted twice consecutively by -pi/2 radian each at 1/2 time slot each to attain keying modulation. Furthermore, the demodulation circuit consists of a PD5, a DL6, a DBM7 and an LPF8, the modulated signal is divided into two, one signal is phase-shifted at 1/2 time slot, multiplied and integrated with the other signal to demodulate the original binary information symbol.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital communication system that is resistant to multiple wave interference.

[Conventional technology]

In conventional digital communication systems, for example, in communication systems such as mobile radio, where one digital signal modulated by one piece of digital information is often received as multiple waves via different transmission paths, mutual interference caused by these multiple waves is a problem. Therefore, there was a problem that the code error rate deteriorated significantly.

In order to solve this deterioration of the code error rate, methods are used to construct various error correction codes depending on the degree of the code error rate.

[Problem that the invention seeks to solve]

However, in a communication channel where errors occur in bursts, such as in mobile communications, the structure of such an error correction code is generally much larger than the code to be transmitted, and it is temporarily stored in memory for decoding. There is a problem in that the total transmission time becomes longer and the equipment becomes more complex.

This invention was made in order to solve the above-mentioned problems, and it solves the problem of a decrease in the code error rate without configuring an error correction code, thereby shortening the overall transmission time and simplifying the device. The purpose is to obtain a digital communication method that will improve the speed of communication.

[Means for solving problems]

In the modulation method of the digital communication system according to the present invention, when the symbol transmission interval is one time slot, the phase of the carrier wave is changed twice in each time slot in response to a binary information symbol of "0" or "1". The phase is changed by 15 radians or m=radians to change the phase by +π radians or −π radians per time slot.

The demodulation method uses delayed detection with a delay amount of 100 time slots.

Note that the above modulation method performs phase shift twice for each binary information symbol, so Double phase
This is called the Shift Keying method (hereinafter referred to as the DSK method).

[Effect]

In the digital communication system according to the present invention, since the modulation system is the DSK system, even if there is multiple wave interference, the correct demodulated output corresponding to the binary information symbol can always be large, and the code error rate can be greatly improved.

[Embodiments of the invention]

The invention will be explained below with reference to the drawings.

FIG. 1 (4) is a diagram illustrating an example of the phase transition of a carrier wave corresponding to "0" and "1" of a binary information symbol in the modulation method according to the present invention, and FIG. 1 (6) is a diagram illustrating such a phase transition. In a modulator that performs
FIG. 3 is a diagram showing a phase change of a carrier wave when modulation is performed by .

In FIG. 1(4), the arrow indicates the direction of phase transition corresponding to the binary information symbol shown above the arrow.

In addition, in the first drawing, (6) indicates a binary information signal.
In the arrangement of value information symbols, I indicates a signal (hereinafter referred to as a DSK signal) that has undergone a phase change of a corresponding carrier wave. Further, T is the length of one time slot, which corresponds to the symbol transmission interval in a unit binary information symbol.

First, the method of generating a DSK signal will be explained based on FIG. The first binary information symbol "1" constituting the binary information signal is first shifted by +π/2 radians, and after one time slot has elapsed, it is further shifted by +π/2 radians, resulting in a total phase shift of 1π radians. do. Next, for the second binary information symbol "0", starting from the final retarder π radian corresponding to the first symbol, first shift by -π/2 radian, and after - time slot elapses. Furthermore, the phase is shifted by 11 degrees, resulting in a total shift of -π radians, so that the initial phase returns to the position of 0 radians.

Furthermore, for the 8th binary information symbol "1", the final phase corresponding to the second symbol starts from 0 radians, is first unshifted by 10 radians, and then further shifted by 100 radians after the -time slot elapses. Unshifted and shifted by a total of π radians, the phase becomes +π radians with respect to the initial phase of 0 radians.

In this way, the DSK of the digital communication system according to the present invention
The signal is characterized in that one binary information symbol is shifted twice by +π/2 radians or −π/2 radians depending on the sign of the symbol every i time slot, and is shifted by 1π radians or −π radians.

Next, we will briefly explain the reproduction of a binary information signal when one DSK signal is received via communication paths with different delay times, and also explain how the DSK
We will explain why the bit error rate of this signal is better than that of a conventional two-phase PSK signal (hereinafter referred to as BPSK signal).

Figure 2 shows the first arriving signal (
This shows the phase relationship between a signal that arrives late (hereinafter referred to as a U wave) and a signal that arrives late (hereinafter referred to as a U wave). For convenience of explanation, this figure shows one U wave that arrives with a delay of τ with respect to the upstream wave.

FIG. 2(6) shows a system diagram of a demodulation circuit for a DSK signal.

The demodulation circuit consists of a delay detection circuit with a delay time set to 100 time slots.

On the receiving side, the U wave arrives with a delay of τ in addition to the D wave, and the D wave and U wave are combined and guided to the demodulator. Examining this composite wave, we find that in each one time slot in Figure 2 (b) (excluding the interval a between °C < b + C + d, there is always binary information regardless of the interference state between the D wave and the U wave. signal(
In this case, the correct information corresponds to each binary information symbol forming [1, 0, I J). In other words, the D wave and the U wave are in the interval d, the in-phase part in the interval d, and the part shifted by 100 phase in the interval C. Under conditions that can actually occur, the demodulated output in the intervals a, b, c, and d is as follows. become that way.

Here, p: Relative amplitude ratio of U wave to D wave - Carrier phase difference between secondary wave and U wave As can be seen from this calculation result, demodulated output e (t) is equal to the symbol of the preceding bit in interval a. Although it is uncertain due to the relationship between the two, the polarity is uniquely determined in sections S, c, and d corresponding to the own symbol.

Although there is a problem that the amplitude changes depending on the amplitude ratio and phase relationship between the D wave and the U wave, it is within the interval.

The relationship between d and section C is such that when one becomes smaller, the other becomes larger with respect to a change in the phase difference, so that one of them remains at a large amplitude.

Therefore, the so-called horizontal deviation of the eye pattern is at most less than the delay time τ, and the eye pattern does not close. As a result, the code error rate becomes extremely good.

In the case of the conventional BPSK method in which the unit symbol is shifted by +π or -π radian, there is no equivalent to section C, so the code error rate is significantly worse than in the DSK method.

FIG. 8(4) shows the code error characteristic in the case of the DSK signal according to the present invention. For comparison, FIG. 8(6) shows the code error characteristics in the case of a BPSK signal. In Figure 8, both the D wave and the U wave are changed by the Ray distribution. Pd and Pu are the average powers of the D wave and U wave, respectively, M is the signal energy per 1 bit, No is the noise energy per unit frequency, and fa is the maximum frequency for fading reading.

The bit error rate for BPSK signals peaks out at around 10-I, while the bit error rate for DSK signals is 1.
0-6 or more was obtained, which shows that the improvement achieved by the DSK method is extremely large.

Next, an example of a specific configuration of a modulation circuit and a demodulation circuit used in the digital communication system according to the present invention will be described.

FIG. 4 is a diagram showing an example of the configuration of a modulation circuit.

In the figure, (1) is an encoding circuit (hereinafter referred to as DSK-ENC).
), the in-phase component waveform (hereinafter referred to as l
-CH double signal) and orthogonal component waveform (hereinafter referred to as (,!-C
This is to generate an H signal). (2) and (3)
is a multiplicative modulator (emission, D
(referred to as BM), respectively l-CH times signal coswct
s Q-CH multiplied signal - sinwct (where - is the angular frequency of the carrier wave). (4) is a power combiner (hereinafter referred to as PC
), and a DSK signal is obtained as its output.

FIG. 5 is a diagram showing an example of the configuration of a demodulation circuit.

(5) is a power divider (hereinafter referred to as FD) which divides the received signal into two. (6) is the delay line (hereinafter referred to as D
(referred to as L), and its delay time is set to one time slot. (7) is product modulation (hereinafter referred to as DBM),
It consists of a double balance modulator and takes the product of two signals. (8) is a low-pass filter (hereinafter referred to as LPF)
The high frequency component is removed from the output signal of the DBM (7) to obtain a delayed detection output corresponding to a desired binary information signal.

Next, DSK-ENC (1) will be explained using FIG. 6. FIG. 6(a) shows a binary information signal represented by binary information symbols. FIG. 6(b) shows the phase transition of the DSK signal due to this binary information signal, with the initial value being +1. If the initial □ value of the DSK signal is an odd multiple of 5, then 1 to be applied to DBM (2) and DBM (3)
-CH multiplication signal and Q-CH compensation code are 2 consisting of +1 and -1.
l-C which can be configured into a value signal and corresponds to the binary information signal.
The H-multiple signal is shown in FIG. 6(C), and the Q-CH-multiple signal is shown in FIG. 6(d).

Therefore, on the contrary, corresponding to the binary information signal, FIGS. 6(c) and (
If the waveform of d) is generated and this is applied as an l-CH multiplied signal and a Q-CH multiplied signal to DBM (2) and DBM (3), it corresponds to a binary information signal (Fig. 6 (a)). DS
K signal can be obtained.

Let al be the n-th information symbol of the binary information signal, and the encoding rule is expressed as follows.

Izn = Q211-tea.

I2fl+1 = Qzne) an Qgn = l2n-Ie) an Q2n+1 = I2nΦafi However, when an=rtJ, it is softened as +2' +2, and when an=porcelain, it is shifted as -2'2. Further, when the suffix k of each component is an even number, it indicates one time slot in the first half, and when k is an odd number, it indicates an orthogonal component. Binary symbol rlJ obtained like Jin
When the rOJ series is level-converted into voltage r+VJ and r-VJ signals required for DBM (2) and DBM (3), the actual signals for driving DBM (2) and DByYe are obtained.

The DSK-ENC (1) that performs such encoding may have a circuit configuration as shown in FIG. 7, for example.

In FIG. 7, @ is an input terminal for a binary information signal indicated by a binary information symbol, (121) is a first D-type flip-flop (hereinafter referred to as FFI), and (122) is a first
Exclusive OR gate (hereinafter referred to as EXOR1)
2B) is the second exclusive OR gate (hereinafter referred to as EXOR2
), (124) is the second D-type flip-flop (hereinafter referred to as FF2), (125) is the eighth D-type flip-flop C (hereinafter referred to as FF8), (126)
) is the first level converter (hereinafter referred to as LCI)
, (127) is the second level converter (hereinafter referred to as LC
2), (128) is a − frequency divider (hereinafter referred to as DIV), (to) is an in-phase component output terminal (hereinafter referred to as ICH output terminal), and α◆ is a quadrature component output terminal (hereinafter referred to as QCH output terminal). Input (to) is a clock signal input terminal, which is a terminal to which a clock signal of the same synchronization as the i time slot is input.

First, by FFI (121) and DIW128), 2
An and 5 corresponding to the value information symbol are output. Using this signal, EXORI (122), EXOR2
(128), FF2 (124), FF8 (1
25) The above afi and IhyQh are
Processing is performed according to the encoding rules. This output is converted to LCI (
126).

Level converted by LC2 (127) and DBM (2)
and a l-CH multiplied signal and a Q-CH multiplied signal which change to a voltage of 10 V and -■ required for phase inversion control in the DBM (3).

Demodulation is performed using the circuit shown in FIG. FIG. 8 is a diagram explaining the operation of the demodulation circuit. FIG. 8(a) shows the input value information signal, and FIG. 8(b) shows the DSK signal by its phase transition. Figure 8(c) is the delayed detection output, Figure 8(d)
) indicates a decoded binary information signal. By taking the product of the DSK signal shown in the delay diagram (b) and the DSK signal delayed by i time slots and passing it through LPF (8), the delayed detection output shown in Figure 8 (C) is obtained, which is input to the modulation side. The decoded binary information signal corresponding to the binary information symbol (
d) is obtained.

Although the above embodiment has been described with reference to mobile communications where the delay time of multiplexed waves is large, other communication forms such as line-of-sight/out-of-line-of-sight fixed communications, etc., where the delay time of multiplexed waves is negligible compared to time slots. The same effect can be achieved by applying this method to cases where the bit error rate is large due to delay distortion or synchronization shift.

Furthermore, it is possible to transmit digital signals with good quality using a device as simple as a normal modulator/demodulator without using expensive devices such as privacy reception or error correction control.

[Effects of the Invention] As described above, according to the present invention, the phase of the carrier wave is shifted by +i mitzian or -π/2 radian twice in every time slot corresponding to the binary information symbol, and Since a DSK signal giving a phase shift of a total of 1π radians or −π radians per slot is used, the bit error rate can be significantly improved even under conditions of multiwave propagation with a large delay time.

[Brief explanation of drawings]

FIG. 1 (6) shows the DS of the digital communication system according to this invention.
FIG. 1B is a diagram illustrating an example of the phase transition of a carrier wave corresponding to a binary information symbol in the K system, and is also a diagram illustrating the relationship between a binary information signal and a DSK signal. Second
FIG. 4 is a diagram for explaining the relationship between two DSK signals, a U wave and a D wave, and the second diagram is a diagram showing a system diagram of a demodulation circuit for the DSK signal. FIG. 8 is a diagram showing an example of the code error characteristics of the DSK system and the BPSK system, FIG. 4 is a diagram showing an example of the configuration of a modulation circuit in the DSK system, and FIG. 5 is a diagram showing an example of the configuration of a demodulation circuit in the DSK system. The figure shown in Figure 6 is DSK-EN.
A diagram explaining the operation contents that C (1) should have, Figure 7 is D
A diagram showing an example of the configuration of SK-ENC (1), Figure 8 is a DSK
FIG. 3 is a diagram illustrating the operation of a signal demodulation circuit. C. Shoes. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Fig. 1 (A) CB) Fig. 2 (, 4) Fig. 3 Eb/No [d5] (A) l) 511 formula % formula % Figure 4-15rnl&Ict Figure 5 Figure 7 (f, = bamboo) Figure 8 Procedural amendment (voluntary) March 5, 1985 [EJ

Claims (1)

[Claims] Corresponding to a binary information symbol transmitted in a predetermined time slot, the first information symbol undergoes a phase shift of +π/2 radians twice in every 1/2 time slot, and the second information symbol Symbols are modulated using a modulation method that performs phase shift keying modulation by performing a phase shift of -π/2 radians twice every 1/2 time slot, and a signal modulated by this modulation method is received and its output is Digital communication characterized by comprising a demodulation method in which one signal obtained by dividing is phase-shifted by 1/2 time slot and multiplied and integrated with the other signal to obtain the original binary information symbol. method.