JPS61168163A - Capstan motor control circuit of magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To reduce frequency dividers and to reduce the size and cost of a circuit by switching the reset operation point of a common-use frequency divider counter according to switching between a recording mode and an N-fold fast reproducing mode. CONSTITUTION:A frequency divider 16 is so constituted as to serve as a frequency divider counter which divides the frequency of rotation pulses from a capstan motor 1 by M and a frequency divider counter which divides the frequency of rotation pulses in N-fold fast reproducing mode by N. The reset operation point, i.e. frequency division ratio of this common-use frequency divider counter 16 is switched with a control signal supplied to a terminal 17 according to switching between respective modes such as a standard play mode, a long-play mode, and an expand play mode in recording and the N-fold fast reproducing mode. Consequently, the number of frequency dividers is decreased and the circuit is therefore reduced in size and cost.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a capstan motor control circuit for a magnetic recording/reproducing device, and a circuit for controlling the phase and speed of a capstan motor in a recording mode and in an N times high speed reproduction mode. Regarding.

BACKGROUND OF THE INVENTION FIG. 5 shows a block diagram of an example of a conventional capstan motor control circuit. In the figure, during recording, the switch SW 1 is connected to the terminal R1, and the switch SW 2 is connected to the terminal S. The capstan pulse (720H7) from the pulse detector 2 of the capstan motor 1 is supplied to the 1/M frequency divider 4 via the amplifier 3 and divided by 24 to 30Hz, while the signal from the crystal oscillator 5 is counted down in a countdown circuit 6 to produce a 30Hz signal, and the output of the frequency divider 4 and the output of the countdown circuit 6 are phase-compared in a phase comparator 7 to produce a phase control signal, which is then passed through a low-pass filter 8. The signal is supplied to the adder 9 via the adder 9.

On the other hand, the output of the amplifier 3 is converted into a voltage according to the frequency by the FV converter 10, and is supplied as a speed control signal to the adder 9, where it is added to the phase control signal from the low-pass filter 8, and the motor drive amplifier 11 The signal is amplified and supplied to the capstan motor 1 to control its speed and phase.

Next, during playback, switch SW + is connected to terminal P1 switch S
Connect W3 to the terminal. control spatula 1 mi 1
The control signal (30H2) reproduced by the amplifier 13 and the switch SW3. Phase comparator 7 via SWI
The phase control signal is supplied to the phase control signal, and is added to the speed control signal in the adder 9 to control the capstan motor 1, as in the case of recording.

Next, when searching, switch SW2 and SW3 are connected to terminal S.
Connect to. The output of the amplifier 3, which has a frequency proportional to the search speed, is divided by N by a 1/N frequency divider 14 and used as a speed control signal by the FV converter 10. The reproduced=1 control signal from the head 12 is frequency-divided by N in the 1/N frequency divider 15 to 301-1z, and is converted into a phase control signal in the phase comparator 7.

Problems to be Solved by the Invention The conventional circuit shown in FIG.
5 is also required, which causes the problem that the circuit becomes large and cannot be constructed at low cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a capstan motor control circuit that can be configured with a small number of frequency dividers, can be downsized, and can be configured at low cost.

Means for Solving the Problems In FIG. 1, the frequency divider 16 is a frequency division counter that divides the rotation pulse from the capstan motor 1 by M, and a frequency division counter that divides the rotation pulse in N times high speed reproduction mode by N. This is an embodiment of a frequency dividing means which also functions as a frequency counter and whose reset operating point is switched in response to switching between the recording mode and the N times high speed reproduction mode.

The frequency division ratio of the working frequency divider 16 is switched according to the recording mode and the N times high speed reproduction mode by a control signal supplied to the terminal 17.

Embodiment FIG. 1 shows a block system diagram of a first embodiment of the circuit of the present invention. In the figure, the same components as those in FIG.

This embodiment includes the standard play mode (SP) (2 hour mode), long play mode (LP>(4 hour mode), and expanded play mode (EP) (6 hour mode) shown in FIG. 2 together with the second embodiment. can be applied to each tape speed mode.

In FIG. 1, reference numeral 16 denotes a frequency divider consisting of, for example, a 4-bit counter, which has the configuration shown, for example, in FIG. 3 <A>. The frequency division ratio is set to 1 in response to the control signal taken out from
The frequency can be varied up to 6 divisions, and is a known method. Reference numeral 19 denotes a frequency divider consisting of, for example, a 3-bit counter, which has the configuration shown in FIG. 3(B), and divides the frequency of the input signal by N, which is a well-known device.

The first embodiment has a structure that also serves as the frequency divider 4.14 shown in FIG.

During recording and playback, the switch SW2 is connected to the terminal S1, and the switch SW3 is connected to the terminal S1, and in the SP and LP modes, a signal corresponding to the mode is supplied to the terminal 17 to change the frequency division ratio of the frequency divider 16. Set it to 1/12.

In the same figure, the output a of amplifier 3 (720H at SP
z, 360Hz at LP time, the frequency is divided by 2 by the 1/2 frequency divider 18 at the time of SP to produce a 360Hz signal, while at the time of LP
The time is supplied to the frequency divider 16 as a signal as it is,
Here, the frequency is divided by 12 to obtain a signal C of 30 Hz, and the signal d is supplied to the FV converter 10 via a switch SW 2 as a signal d (same as the signal d).

On the other hand, when in EP mode during recording or playback, a signal corresponding to the mode is supplied to the terminal 17 to change the frequency division ratio of the frequency divider 16 to 1/1.
Set it to 8. The output a (24.0 Hz) of the amplifier 3 is divided by 8 by the frequency divider 16 to become a signal C of 30 l-i z, and the output a is converted to a signal d via switches SW4 and SW2. (same as signal a) and is supplied to the FV converter 10.

On the other hand, when searching, switch SW 2 is connected to terminal S1, switch SW 3 is connected to terminal S, and a signal corresponding to the search speed N times is supplied to terminal 17 in each mode of SP, LP, and EP to perform frequency division. The frequency division ratio of the device 16 is set to N. Output a of amplifier 3 (720XNH2 when SP, 3 when LP
60+NHZ, 240xNHZ at EP) is LP and E
While it is said that the signal remains unchanged during P, the signal is reduced to 1/2 during SP.
The frequency is divided by 2 in the dividing period 18 to produce a signal of 360XNHZ, and the frequency is divided by N in the frequency divider 16 for SP and LP signals.
The signals are supplied to the FV converter 10 as a signal C (signal d) of 360 Hz during EP and as a signal C (signal d) of 240 H7 during EP. This signal C has the same value as the signal d supplied to the FV converter 10 during recording and reproduction.

On the other hand, the output of the amplifier 13 is frequency-divided by N by a 1/N frequency divider 19 to produce a 30H2 signal, which is then supplied to the phase comparator 7.

Its operation is similar to that of the conventional device shown in FIG.

FIG. 4 shows a block system diagram of a second embodiment of the circuit of the present invention. In the figure, the same components as in FIGS. 5 and 1 are given the same numbers, and the explanation of their operation will be omitted. In the same figure, S
Ws is configured to be connected to terminal R/S during recording and searching, and to terminal P during playback. The second embodiment has a structure in which the frequency divider 4.15 shown in FIG. 5 is also used.

Note that if the present invention is applied only to the SP mode or the L P/E P mode, the 1/2 frequency divider circuit 18 and the switch SW 4 can be omitted in FIGS. 1 and 4.

Effects of the Invention The circuit of the present invention has a frequency division counter that divides the frequency of the rotation pulse from the capstan motor by M and a frequency division counter that divides the frequency of the reproduction control signal by N, or the rotation pulse from the capstan motor in the N times high speed reproduction mode. It is also used as a frequency division counter that divides the frequency by N, and the reset operating point of this dual-purpose frequency division counter is changed according to switching between the recording mode and the N-times high-speed reproduction mode, so that the reproduction control signal system and rotation pulse system Compared to the conventional device, which required a total of three frequency dividers, the present invention has the advantage that fewer frequency dividers can be drawn, and the circuit can therefore be constructed in a smaller size and at lower cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the first embodiment of the circuit of the present invention, FIG. 2 is a diagram showing the relationship between modes, signals, and frequency division ratios, and FIG.
The figures are a specific circuit diagram of the frequency divider in FIG. 1, FIG. 4 is a block diagram of a second embodiment of the circuit of the present invention, and FIG. 5 is a block diagram of an example of a conventional circuit. 1... Capstan motor, 2... Pulse detector,
7... Phase comparator, 9... Adder, 10... F'
V converter, 12...control head, 16, 18
．． 19... Frequency divider.

Claims (1)

[Claims] The rotation pulse from the capstan motor in recording mode is M.
The phase of the capstan motor is controlled by the phase comparison error signal between the frequency-divided signal and the reference signal, and in the N times high speed playback mode, the phase comparison error signal between the frequency-divided signal and the reference signal is used to control the phase of the capstan motor. In a capstan motor control circuit of a magnetic recording/reproducing device that controls the phase of the capstan motor and controls the speed of the capstan motor using a signal obtained by dividing the frequency of the rotation pulse by N, the rotation pulse is frequency-divided by M. A frequency division counter and a frequency division counter that divides the frequency of the reproduction control signal by N or a frequency division counter that divides the frequency of the rotation pulse by N are used together, and the reset operating point of the dual-purpose frequency division counter is set to the recording mode and the frequency division counter that divides the frequency of the rotation pulse by N. 1. A capstan motor control circuit for a magnetic recording/reproducing device, characterized in that the circuit is configured to switch in response to switching of a high-speed playback mode.