JPS6171446A - Phase control circuit of double cassette type vtr - Google Patents

Abstract

PURPOSE:To attain stable dubbing with simple circuit constitution by utilizing rise/fall of a reference signal respectively to apply phase control of two sets of VTRs thereby using a phase control circuit in common as well as a reference signal. CONSTITUTION:A 30Hz reference signal ST is given from a reference signal generating circuit 1 and this reference signal is rectanglar wave and its duty cycle is 50%. Further, the 1st head output switching signal RF1 corresponding to a rotary phase detection output of the 1st head motor 2 of the 1st VTR is introduced from the 1st RF signal generating circuit 3 detecting the rotation of the rotary cylinder. Similarly, the 2nd head output switching signal RF2 corresponding to the rotary phase detection output of the 2nd head moor 4 is introduced from the 2nd RF signal generating circuit 5. The reference signal SF and the 1st and 2nd head output switching signals are inputted. Moreover, in case of a capstan servo, a frequency division signal (at recording) in 30Hz obtained by frequency-dividing an FG signal of the capstan motor in a reproducing control signal (at reproduction) must be inputted in place of the head output switching signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a phase control circuit for a so-called double cassette type VTR.

2) Conventional technology A double cassette type VTRK that incorporates two VTRs and records the playback output of one VTR on the other VTR.
(is disclosed in JP-A-58-150106.

In this conventional device, the reference signal of the recording side VTR is used as a synchronized separated output of the reproduced video signal.

(c) Problems to be Solved by the Invention However, in the case of the conventional example described above, stable recording is difficult because the recording VTR performs recording based on the unstable vertical synchronization signal of the reproduced video signal.

Therefore, it may be possible to make stable dubbing possible by sharing the reference signal, or if the reference signal is simply branched and supplied to each VTR.
There are few benefits from integrating TR.

B) Means for solving the problem of bad luck Therefore, in the present invention, the phase control of two VTRs is achieved by utilizing the rising edge and falling edge of a square wave-like reference signal, respectively.

(E) Effect Therefore, in the present invention, a single phase comparator circuit can be used for two VT
The phase comparison of R will be performed at different timings.

(F) Example Hereinafter, the present fr311 will be explained according to an example that can be illustrated. In this embodiment, the servo circuit of the head motor employs the present invention.

First, in this embodiment, the reference signal generation circuit (1) generates 30Hz.
A reference signal (ST) is derived. This reference signal is a square wave with a frequency of 5096. True %
The first head output switching signal (RFl) corresponding to the rotational phase detection output of the first head motor (2) of the IVTH is generated by the first RF signal generation circuit (3) that detects the rotation of the rotating cylinder.
Derived from n. Similarly, 's2 head motor (4)
The second head output switching signal (
RF2) is also derived from the signal generation circuit (5) to the second RFj.

In this embodiment, a reference signal (SF) and a first/second head output switching signal are input. In the case of capstan servo, instead of the above-mentioned head output switching signal, a 50 Hz branch signal (during recording) obtained by dividing the FG signal of the capstan motor or a playback control signal (during playback) is used. must be entered.

The phase control circuit, which is the gist of this embodiment, will be explained below. First, the reference signal (ST) is a 90° shift circuit (6)
The signal is converted into a phase shift signal (SF) via the . This phase shift signal (8F) and the first head output switching signal (RF
The first comparison signal (CFl) is derived by the logical product of 1). The falling edge of this first comparison 'signal (CFl) is
This coincides with the falling edge of the first head output switching signal (RFl), and the information of the comparison signal is present at this falling edge.

Similarly, the inverted signal (SF) of the phase shift signal (SF)
By the logical product of and the second head output switching signal (RF2),
A second comparison signal (CF2) having information at the falling edge is derived.

Both comparison signals (CFl) (CF2) do not overlap in time and are added in the OR circuit, and this added signal is input to the reference wave generation circuit (7).

This reference wave generation circuit (7) forms a reference slope at the falling edge of the addition signal, and the derived reference signal (SL) is input to the first and second f-number hold circuits (87 (91). .

On the other hand, the first sampling pulse (SPl) obtained by delaying the reference signal (8T) t - the manually generated first sampling pulse generation circuit (101 is the falling edge of the reference signal) is input to the first sample hold circuit (8). are doing.

Further, the second sampling pulse generation circuit I inputting the reference signal (8T) generates the second sampling pulse (SF2) with a delayed rise of the reference signal to the second sample hall circuit (9T).
) is entered.

Therefore, the slope of the reference signal (SL) is determined by the slope of the first sample and hold circuit (8) and the second sample and hold circuit (9).
The data will be sampled alternately.

Each phase control output obtained by this chimple hold is added together with the rotation control output derived from the first and second AFC circuits in an adding circuit, and this added output is used to control the first and second head motors. 121 (
The rotational phase of 41 is controlled.

Although this AFC circuit inputs the head output switching signal, in the case of a capstan servo, it is possible to input the FG multiplied signal of the capstan motor without frequency division.

The above explanation is based on the assumption that both VTRs are operating, but when one VTR is in a stopped state, the corresponding sample and hold output becomes 0 because the corresponding comparison signal is to be derived. However, the sample and hold of the other VTR is properly performed.

(g) Effect Therefore, according to this fill, the reference signal is
``The phase control circuit can also be shared, making it possible to have a simple circuit configuration and stable dubbing operation.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention;
FIG. 2 shows waveform diagrams of the same essential parts. (1)...Reference signal generation circuit, +21 (41...First and second heged motors, (ST)...Reference signal.

Claims (1)

[Claims] (1) In a double cassette type VTR in which the head motor or capstan motor of a first VTR and a second VTR is driven by a reference signal consisting of a square wave, the falling part of the reference signal and the first VTR The phase control of the capstan motor or head motor of the first VTR is performed by comparing the rotation detection output of the second VTR, and the rotation detection output of the second VTR is compared with the rising edge of the reference signal. A phase control circuit for a double cassette type VTR, characterized in that it controls the phase of a capstan motor or a head motor of a second VTR.