JPS61166671A - Composite processor control system - Google Patents

Abstract

PURPOSE:To improve the efficiency of a processor and to increase the processing speed by discontinuing the action control state of a processor that delivered a bus using right request during the control of the bus using right and switching a processor set under a stop mode to an action control state. CONSTITUTION:A processor A controls a processor B to a stop state in an access mode of a local bus in order to avoid the conflict of bus. A bus using right request is delivered to a bus arbiter 6 for a system bus 5 while the processor A is kept under an action control state. In this case, the processor A switches the processor B to an active state in order to ensure the effective use a period of the arbitration control for decision of the bus using right. Then the action control state is shifted back to the processor A from the processor B when the processor A acquires the bus using right after the arbitration control. This improves the working efficiency of processors and increases the system processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] When one processor out of two processors and a memory device connected to a local bus issues a bus usage right request to the system bus.

Since that processor will be in the waiting state until it acquires the right to use the bus, if the other processor is in the stopped state at this time, that processor will be switched to the operation control state instead of the waiting processor, and the processor will be placed in the idle state. allows access to memory devices via the local bus,
Increase processing efficiency.

[Conventional technology]

Conventional control for acquiring the right to use a system bus shared by a plurality of devices (hereinafter referred to as arbitration) will be briefly described.

FIG. 2 shows an example of a system in which a plurality of devices are connected via a system bus.

21 is a processor A, 22 is a processor 8, 23 is a memory device, and 24 and 25 are channel devices.

26 is a system bus, and 27 is a hash arbiter that performs bus control.

When each processor and channel device needs to use the system bus 26 for data transfer, they each issue a request to the path arbiter 27 to acquire the right to use the bus.

When the system bus 26 becomes vacant, the bus arbiter 27 determines if there are multiple devices requesting the right to use the bus.
A battle for the right to use the bus is held between them, and control, ie, arbitration is performed to give the right to use the bus to the device with the highest priority.

When the device that has acquired the right to use the bus in this way finishes using the bus, the path arbiter 27. Arbitration is executed again, and bus usage rights are granted one after another to devices requesting bus usage rights.

FIG. 3 shows an example of arbitration operation when processor A and processor B request the right to use the lotus.

In this example, system bus 26 is in use by channel devices when processor A and processor B request bus access. For this reason.

Arbitration between processor A and processor B is performed after waiting for the bus to be used.

Since processor A is set to have a higher priority than processor B, it acquires the right to use the bus as a result of arbitration, and uses the system bus 26 to execute data transfer with, for example, the channel device 25. On the other hand,
Processor B continues to issue bus usage rights requests during this time.

Next, when the use of the bus for the processor ends, processor B acquires the right to use the bus. This allows system bus 2
6 is used to transfer data to and from the memory device 23, for example.

[Problem that the invention seeks to solve]

In a conventional information processing system using a system bus, even if two processors connected to the system bus both request bus use, the lower processor remains in a waiting state until the upper processor finishes using the bus, resulting in parallel processing. There was a problem in that the processing efficiency of the system did not improve because the process was not performed.

[Means for solving problems]

The present invention connects two processors and a memory device via a local bus and configures them separately from a system bus.
One of the processors requests the right to use the system bus, and while arbitration control is being performed, the control unit allows the other processor to access the memory device from the local bus.

FIG. 1 is a system configuration diagram for explaining the present invention in detail. In the figure, 1 is a processor A, 2 is a processor B, 3 is a memory device, 4 is a local bus, 5 is a system bus, 6 is a path arbiter, and 7 and 8 are channel devices.

In order to prevent bus contention, Broce Nosa A controls the other processor B to be in a stopped state when accessing the local hash.

For example, when processor A is in the operation control state, a bus usage right request to use system bus 5 is sent to path arbiter 6.
If processor A issues the bus during arbitration control to determine the right to use the bus.

Since the process is in a waiting state, if processor B is not operating at this time, it is in a stopped state, and in order to make effective use of this period, processor B is switched to an operation control state.

Processor B connects memory device 3 via local bus 4.
access and execute predetermined processing.

When arbitration control ends and processor A acquires the right to use the lotus, the operational control state is returned from processor B to processor A. Due to this.

Processor A has local bus 4 and system bus 5.
Perform data transfer using .

[Effect]

FIG. 4 shows two cases during arbitration control according to the present invention.
An example of the operation sequence of two processors is shown below.

In the illustrated example, a channel device is using the system bus when processor A requests the right to use the bus. When arbitration control is started, processor B is operated and access to the memory device is executed in parallel with arbitration control. During this time, when arbitration control is completed and processor A acquires the right to use the bus, it uses the system bus to execute data transfer.

This improves the processing efficiency of the system.

〔Example〕

FIG. 5 is a diagram showing the main parts of a system according to an embodiment of the present invention.

In the figure, 51 is processor A, 52 is processor B
, 53 is a memory device, and 54 is a data line.

55 is an address line, 56 is an arbitration control circuit, 57 is a system bus, 58 is a bus arbiter, 59 is a D
The MA controller is shown.

The data line 54 and the address line 55 are connected to the processor A,
It constitutes a local bus for processor B and memory device 53.

Arbitration control circuit 56 is a common interface circuit for bus usage rights requests from processors A and B.

FIG. 6 shows an example of the operation sequence of the embodiment system shown in FIG. 5, and the operation of the embodiment system will be explained below based on this.

When the system bus 57 is being used by the DMA controller 59 for DMA transfer to the memory device 53, the need arises for the processor A to use the bus, and a request for the right to use the bus is sent to the bus arbiter via the arbitration control circuit 56. 58 shall have been notified.

This is because the DMA controller 59 has a higher priority than the processor A in acquiring the right to use the lotus.

As long as the DMA controller 59 continues to issue requests for the right to use the bus, it will not be able to win the battle to determine the right to use the bus, and the arbitration control will be performed as indicated by the dotted line in the figure.

It lasts for a long time.

However, with the start of arbitration, processor B, which had been in a halted state, is switched to a control operating state, during an interval between DMA transfers.

The memory device 53 is accessed and the processing is executed.

Next, when the DMA controller 59 ends the DMA transfer control and the processor A acquires the right to use the bus, the processor A enters the control operating state again.

Processing using the system bus 57 is executed.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to improve the conventional case where two processors are in a waiting and stopped state during arbitration control, and to operate one processor even during arbitration control.
It can increase the efficiency of the processor and increase the processing speed of the system.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram according to the present invention method, Fig. 2 is a system configuration diagram according to the conventional method, Fig. 3 is an operation sequence diagram according to the conventional method, Fig. 4 is an operation sequence diagram according to the present invention method, and Fig. 5 is a system configuration diagram according to the present invention method. FIG. 6 is a block diagram of the embodiment system, and FIG. 6 is an operation sequence diagram of the embodiment system. In FIG. 1, 1 is processor A, 2 is processor B
, 3 is a memory device, and 4 is a local bus. 5 represents a system bus, and 6 represents a bus arbiter. Patent Applicant: Panafacom Co., Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) Han 41 Pimon 2)
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Claims (1)

[Claims] The system has two processors (1), (2) and a memory device (3), and connects these two processors (1), (2) and the memory device (3) via a local bus (4). In an information processing system connected to a bus (5), when one of the two processors (1) and (2) is in the operation control state and issues a bus usage right request for the system bus (5), the other processor is in a stopped state, interrupts the operation control state of the processor that has issued the bus use right request while bus use right acquisition control is being performed, and switches the other processor in the stopped state to an operation control state; A multiprocessor control system characterized in that it enables access to a memory device (3).