JPH0128970B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a disk control method for efficiently transferring data between a disk device and a central processing unit or a communication control device.

(Prior Art) A conventional data transfer system for a disk control device is a communication control system centered on a disk control device having only a sector buffer, as shown in FIG. The data received by the communication control unit (CCU-A) 5 is transferred to the direct memory access device (DMA).
1 transfers the data to the main memory (MM) 3 via the processor bus 10. Among the data stored in the main memory 3, for example, analysis and conversion processing of the header part is performed by the central processing unit (CPU).
2, the header section and data are transferred to the disk controller 4 via the processor bus 10 under the control of the direct memory access device 1. When all the data is stored in the sector buffer (SBUF) 8, the control unit (CTL) 9 instructs the disk device (DKC) 7 to perform a write operation and starts writing.
During this time, the central processing unit 2 executes normal access to the main memory 3 via the processor bus 10. On the other hand, when another communication control unit (CCU-B) 6 starts receiving data, the data is transferred to the main memory 3 via the processor bus 10 under the control of the direct memory access unit 1. As mentioned above, when the usage rate of the processor bus 10 increases, the transfer capacity of data stored in the sector buffer 8 decreases, and the time required to transfer one sector worth of data from the main memory 3 to the sector buffer 8 via the processor bus 10 becomes longer. Become. Therefore, the period for transferring the data of the next sector becomes longer, and the transfer capacity of the disk device 7 cannot be fully satisfied, resulting in a reduction in the processing capacity of the system.

(Object of the Invention) The present invention has been made in view of the drawbacks of the prior art, and uses a plurality of buses to improve the transfer capacity of the buses, thereby sufficiently increasing the transfer capacity between the disk control device and the disk device. This provides a method for withdrawing data. The present invention has a three-port shared memory in the disk control device that accommodates a processor bus, a communication data bus connected to a communication control device, and an internal bus for transferring disk data. The purpose of this is to improve the data transfer ability to the disk device by independently performing a cycle steal operation. The present invention will be explained in detail below using the drawings.

(Structure of the Invention) In disk control in which data is transferred between a communication control device and a disk device using a direct memory access device and a central processing unit, a shared memory that stores received data for each device;
It is a disk control system that includes a bus arbiter that accommodates a plurality of buses and performs connection priority control for each bus, and that accesses between the plurality of buses and the shared memory are prioritized and controlled by the bus arbiter.

(Example) FIG. 2 shows an example according to the present invention. A central processing unit (CPU) 2, a direct memory access device (DMA) 1, and a main memory (MM) 3 are connected to a processor bus 10, and a communication control unit (CCU-A) 23 and a communication control unit (CCU-B) 2 are connected to a processor bus 10.
4. The communication control unit (CCU-C) 25 and the direct memory access device 22 are connected to the communication data bus 2.
Connect to 1. On the other hand disk controller (DKC)
11 is a bus arbiter (ARBT) 12, a shared memory (CM) 13, and a sector buffer (SBUF)
14, a control unit (CTL) 15, a disk unit (DKU) 7, a processor bus 10,
Connect to the communication data bus 21. The bus arbiter 12 also has a processor bus 10 and a communication data bus 2.
1 and an internal bus 16 for disk transfer.

Next, the operation will be explained. Communication control device 23
When the communication control device 23 starts a receiving operation, the data received by the communication control device 23 is stored in the A area 131 of the common memory 13 via the communication data bus 21 under the control of the direct memory access device 22. Of the stored data, only the header part is transferred from the shared memory 13 to the main memory 3 via the processor bus 10 under the control of the direct memory access device 1 for analysis and conversion processing of the header part. The central processing unit 2 analyzes the header portion stored in the main memory 3 via the processor bus 10, and after the processing, the data is transferred from the main memory 3 via the processor bus 10 to the disk control device again under the control of the direct memory access device 1. The data is transferred to the shared memory 13 in 11. Analyzed stored data such as addresses are transferred from the shared memory 13 to the sector buffer 14 via the internal bus 16. The control unit 15 transfers the accumulated data transferred to the sector buffer 14 to the disk device 7.
A write operation instruction is given to write to. During this time, the other communication control devices 24 and 25 also perform the above-mentioned processing in parallel, but the bus arbiter 12 performs a competing operation for each memory access cycle, and the internal bus 1
6. The data transfer capability of the disk controller 11 is ensured by assigning competitive priorities to the processor bus 10 and the communication data bus 21 in that order. In this embodiment, the A area 131 of the shared memory 13 stores data of the communication control device 23, and
Data transfer route 17 between and sector buffer 14
The B area 132 of the shared memory 13 stores the data of the communication control device 24, and the common memory 1
Data transfer route 18 between 3 and main memory 3
is executed, and the area 133 of C is the communication control device 25.
A data transfer route 19 between the shared memory 13 in which data is stored and the communication control device 25 is executed.
A third timing chart of the bus arbiter 12 that performs the above operation is shown. FIG. 3A shows the memory machine cycle allocation of the common memory 13,
A, B, and C are the names of the allocated data areas. B is between the shared memory 13 and sector buffer 14 (route 17), C is between the shared memory 13 and main memory 3 (route 18), and D is the shared memory 1
3--communication control device 25 (route 19). In the figure, a rising edge of a signal indicates a memory request, and a shaded area indicates memory access execution. Each of the routes is prioritized in the order of (B), (C), and (D) in the figure, and (B) ensures the data transfer speed to the sector buffer 14 by executing every other memory cycle. Now data transfer route 17,1
When there are transfer requests at the same time in 8 and 19, memory accesses are executed in the order of B, C, and D in the figure according to the priority order. That is, while data transfer is being executed on route 17, routes 18 and 19 are in a waiting state, and after route 17 has finished transferring, route 18 starts transferring, and after route 18 has finished transferring, route 19 starts transferring. Even if there is a request for continuous transmission of route 17 during this period, the waiting state is maintained until the transmission of route 19 is completed, and after the transmission of route 19 is completed, the continuous transmission of route 17 is started. By performing the cycle steal operation in this way, the central processing unit 2 and the communication control unit 25
The data processing capacity of the system can also be improved.

(Effects of the Invention) As explained above, the present invention provides a bus arbiter with priority control for a shared memory, a processor bus, a communication data bus, and an internal bus in a disk control device, thereby providing high-speed transfer to disk devices and a central processing unit. , it becomes possible to improve the processing capacity of a communication control device, and it is useful for use in a storage processing system using a communication line.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional storage processing system, FIG. 2 is a block diagram of a storage processing system using a disk control device according to the present invention, and FIG. 3 is a timing diagram showing competition control. 1, 25...direct memory access device,
2...Central control unit, 3...Main memory, 4,
11...Disk control device, 5, 6, 23, 2
4, 25... Communication control device, 7... Disk device, 8, 14... Sector buffer, 9, 15...
Control unit, 10...processor bus, 12...bus arbiter, 13...shared memory.

Claims (1)

[Scope of Claims] 1. In disk control in which data is transferred between a communication control device and a disk device by a direct memory access device and a central processing unit, a processor bus to which the central processing unit is connected and a communication control device are connected. a bus arbiter that accommodates a communication data bus and an internal bus to which disk devices are connected; a shared memory that is connected to each of the buses via the bus arbiter; and a shared memory that controls the transfer of accumulated data in the shared memory to the disk device. having a disk control device comprising control means;
A disk control method characterized in that accesses between the buses and the shared memory are prioritized and controlled according to the priority order of the internal bus, processor bus, and communication data bus.