JPH0512197A - Bus control system - Google Patents

Abstract

PURPOSE:To improve the working speed of a bus control system and to improve the performance of a system bus by providing a bit which designates the start of the burst transfer to the system bus after the data are stored and therefore converting effectively a single-shot I/O access given to an I/O device set on the system bus from a processor into a burst mode. CONSTITUTION:A bus converter 100 contains a means 13 which can decide whether the conversion is needed into a burst mode or not in terms of software. Based on the decision of the means 13, a single-shot I/O access is effectively converted into a burst mode and an access is given to an I/O device connected to a system bus. Thus it is possible to apply a burst transfer mode for the continuous ones of those I/O accesses which are given in a single shot to the system bus. Then it is just required to output once an address cycle for each transfer of blocks that is so far outputted for each access of a single-shot I/O access. As a result, a high speed access is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus such as a personal computer and a workstation, and more particularly to a computer system having a multiplex bus in which addresses and data are multiplexed as a system bus,
And its bus control system.

[0002]

2. Description of the Related Art In a conventional device in this technical field, a bus used as a system bus is, for example, "Future Bus Plus, P896.1, Logical Layer Specifications, Futurebus +, P".
896.1, Logical Layer Spec
Due to the limitation of the number of pins, a bus in which an address and data are multiplexed has come to be widely used, such as "fications" (1990, IEEE). In addition, in order to access consecutive addresses at high speed, the Future
Buses such as bus + that support burst transfer for high-speed block transfer of continuous data are also increasing. FIG. 9 shows a typical example thereof. FIG. 9 shows an access time chart of a bus in which addresses and data are multiplexed. (A) is an access time chart when a single write access is performed four times in a row. in this case,
Data of the data width of the bus can be transferred in one transfer (4 bytes in one transfer for a 4-byte width bus,
That is, 16 bytes can be transferred in four times). (B) is an access time chart of four consecutive burst write transfers. This is a transfer mode used when accessing continuous addresses. It can be performed by designating the start address (address 0) and then continuously outputting the data to be written to the following three addresses onto the bus. . In this way, when accessing continuous addresses, the burst transfer mode can be used for faster access than single access, and the bus occupancy period is short, which improves bus utilization efficiency. .

FIG. 2 is a system configuration diagram of a typical multiprocessor system. Reference numeral 100 is a bus converter for converting between a processor bus and a system bus.
2, 103 are multi-compatible processor modules, 10
Reference numeral 4 is a main memory, 105 and 106 are I / Os (input / output devices), 107 is a bus converter for converting between the system bus and I / O bus, 108 is a multiprocessor-compatible processor bus, and 109 is an address and data. The multiplexed system bus 110 is an I / O bus.

In such a system, how the processors 101 to 103 access the main memory 104 and how to increase the speed are important for improving the system performance.

In such a system, a means for efficiently using the burst transfer mode is disclosed in Japanese Patent Laid-Open No.
There are methods as disclosed in Japanese Patent No. 12358 and Japanese Patent Laid-Open No. 2-278362.

[0006]

As described above, in the system bus, in many cases, in order to reduce the number of pins of the bus, the address and the data are multiplexed (multiplex).
It has become essential to do so. In this case, burst transfer is effective for speeding up access and improving bus usage efficiency, and is frequently used in DMA (Direct Memory Access) and the like.

An object of the present invention is to perform I / O by a processor.
When accessing continuous addresses by access, it is possible to use the burst transfer mode to achieve high-speed access.

Another object of the present invention is to perform I processing performed by a processor.
The purpose is to make it possible to use the burst transfer mode when accessing continuous addresses with / O access, shorten the period occupied by the system bus, and improve the bus usage efficiency of the system bus.

A further object of the present invention is a system having means for converting a continuous address I / O access made by a processor into a burst transfer mode, wherein the continuous address is accessed by the I / O access made by the processor. The purpose is to improve the processing efficiency by effectively using the two modes of the presence or absence of conversion.

Still another object of the present invention is a system having means for converting a continuous address I / O access made by a processor into a burst transfer mode, and the conversion mode is effective when a multiprocessor system is constructed. To provide a means for improving processing efficiency.

Another further object of the present invention is to enable efficient use of the burst transfer mode when the I / O access made by the processor is used to access consecutive addresses, and to shorten the period occupied by the system bus. , To improve the bus usage efficiency of the system bus.

[0012]

In order to achieve the above object, in the present invention, a buffer for accumulating a single I / O access request from the processor bus side to the system bus is provided, and these access destinations are continuous addresses. In this case, a means for converting them to burst transfer (block transfer) and accessing the system bus is provided. And
Burst transfer of single I / O access (block transfer)
As a method of determining whether to activate the system bus by converting to, if the addresses of the access activated from the processor to the bus controller are continuous addresses, convert them to burst transfer (block transfer). Access the system bus.

Further, in the present invention, the following means are added to achieve the above-mentioned other objects.

(1) Waiting for access to the system bus until a single I / O access request is accumulated, or a single I / O access request
As a condition for determining whether to access the system bus as an O access, the system does not perform a single I / O access until the data for the number of burst transfers is accumulated in the control register in the bus controller, and the system is executed when the data is accumulated. Provide a bit to specify that burst transfer is activated for the bus. In addition to this, a monitoring timer is also provided in order to prevent performance deterioration due to waiting for I / O access requests to accumulate for too long.

(2) When a multiprocessor system is constructed, a bit is set in the bus arbiter of the processor bus for designating that the burst transfer is activated on the system bus after the data of (1) is accumulated. In this case, a means for giving the bus right of the processor bus is provided only to the processor that sets this bit until the data for the number of burst transfers is accumulated. Further, there is provided means for automatically clearing this bit and returning to the normal mode when an interrupt request is issued to the processor or when addresses are not consecutive due to a program switch.

[0016]

[Operation] As a result, the system bus goes out in a single shot.
Of the / O accesses, the burst transfer mode can be used for continuous address access,
In single-shot I / O access, it is sufficient to output the address cycle that was output every time once for each block transfer, so access can be speeded up, and bus occupation when transferring the same amount of data The time can be shortened and the bus usage efficiency is improved. Further, it is possible to prevent performance degradation due to arbitration overhead.

Also, an I / O that goes out to the system bus in a single shot
Of the accesses, the burst transfer mode can be selectively used by software for accesses with consecutive addresses, and the address cycle that was output every single I / O access is output once per block transfer. Therefore, the access speed can be increased, the bus occupation time can be shortened when the same amount of data is transferred, and the bus usage efficiency is improved. The number of times of arbitration is also reduced, for example, from four times to one, and it is possible to prevent performance deterioration due to overhead of arbitration. Also, the bit that specifies that the burst transfer is activated to the system bus after the data is accumulated is the I / O for the continuous address.
Since software that knows in advance the access will occur, it is faster to access the system bus as a single I / O access, for example, when the I / O access interval is very long. It is possible to prevent a decrease in processing efficiency.

Further, when a multiprocessor system is constructed, the number of burst transfers is set when a bit is set in the bus arbiter of the processor bus to start the burst transfers to the system bus after data is accumulated. By giving the bus right of the processor bus only to the processor that sets this bit until the minute data is accumulated, it is possible to prevent the mode conversion efficiency from being lowered due to the switching of the processor. Furthermore, when an interrupt request is issued to the processor, the normal mode is automatically returned to enable interrupt processing with good responsiveness. Also, by providing a means to automatically clear this bit and return to the normal mode when the addresses are no longer continuous,
Flexible support for program switches is also possible.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. The first embodiment is a bus converter 10 in the system configuration of FIG. 2 described in the conventional example.
FIG. 1 is a detailed block diagram of the bus converter 100 of the present invention. 2 is a bus arbiter that arbitrates the bus usage right of the processor bus 108,
3 is a processor bus control unit, 4 is an address unit of an I / O write buffer for four stages, 5 is a data unit of an I / O write buffer, 6 is an address unit of an I / O read buffer for four stages, and 7 is I / O read buffer data section, 8 is an input latch from the processor bus 108, 9 is an output latch to the processor bus, 10 and 11 are comparators that determine whether the write or read access address is a continuous address, and 12 is a processor Is a control register group in the bus converter 100 that can be directly write-accessed via the processor bus 108, 13 is a control register for burst I / O access control, 14 is a burst I / O access designation bit in the control register 13,
Reference numeral 15 is a timer, 16 is an interrupt control unit, 17 is a system bus control block, 18 is a system bus signal control unit, 19
Is an I / O access control unit, 20 is a one-shot I / O access control unit, 21 is a burst I / O access control unit, 22 is a system bus access address latch, 23 is an output data latch to the system bus, and 24 is a system. Input data latch from the bus, 25 is an OR gate, 26, 27,
28 is an inverter, and 29 and 30 are selectors.

Reference numeral 31 is an interrupt request signal for a processor on the processor bus, 32 is a processor bus arbitration signal, 33 is a processor bus control signal, 34 is a multiplexed address / data bus of the processor bus 108, and 35 is The burst I / O access designating bit 14 in the control register 13 outputs the burst I / O access designating signal, 36 clears the burst I / O access designating bit 14 and resets the timer 15, and 37 burst I / O access Control signal, 38
Is an interrupt request signal from the system bus 109, 39 is a system bus control signal, 40 is a multiplexed address / data bus of the system bus 109, and 41 and 42 are addresses indicating that the write or read access address is a continuous address. A hit signal, 43 is a burst I / O access cancel signal due to an interrupt from the system bus, and 44 is a burst I due to overflow of the timer 15.
/ O access cancel signal, and 45 is an internal control signal.

First, I / O read and write operations in this embodiment will be described. In the case of normal access, that is, when the value of the burst I / O access designation bit 14 in the control register 13 is “0” (initial value is 0), one of the processors 101 to 103 is I
When the I / O write operation is activated, the burst I / O access designation signal 35 is false, so the burst I / O access control unit 21 does not operate, and instead the single-shot I / O access control unit 20 operates, Single-shot I / O read / write is activated to the system bus. On the other hand, when a processor wants to perform I / O read / write to consecutive addresses and convert it to burst access,
Burst I / in the control register 13 in advance
The value of the O access designation bit 14 is set to "1". Here, the access method of the control register group 12 in the bus converter 100 is that the address and data output by the processor are taken in via the address / data bus 34 and the input latch 8, and the address is the control register group in the bus converter 100. When the address is assigned to 12, the access data is controlled to be taken into the control register group 12.

Burst I / O access designation signal 3
Since 5 is true, the single I / O access control unit 2
The burst I / O access control unit 21 operates instead of 0, and in the case of writing, after accumulating four accesses in the address unit 4 and the data unit 5 of the I / O write buffer, the system bus 109 Write access can be activated in the burst I / O mode.

At this time, in this embodiment, the burst I / O access can be canceled under some conditions. First of all, in order to prevent performance degradation due to the I / O access interval being too wide, monitoring is performed by the timer 15. If the set value of the timer is exceeded, burst I / O due to overflow of timer 15
The O access cancel signal 44 forcibly clears the access designation bit 14 and outputs the accumulated access request to the system bus as a single I / O access. Conditions for clearing the timer 15 and the like are shown in the flowchart of FIG.

When performing the burst access conversion mode,
First, immediately after the start of 601, the timer is in a stopped state as indicated by 602. When it is detected at 603 that the burst I / O access designation bit 14 is set, at 604, the timer is counted up. Immediately after this, 605
The timer is cleared with and the counting up is started from "0" in 606. After this, as in 607, it is constantly monitored whether an interrupt or timeout occurs. 6
At 08, as in the case of a series of controls in FIG. 4 which will be described later, when an access is made, it is stored in the buffer without making a single I / O access. Then, it is determined whether the address is a continuous address. If it is not a continuous address, all the access accumulated up to that point is a single I / O.
Burst I / O access is issued as an access, and the burst I / O access designation bit 14 is automatically cleared to return to the normal state. In the case of continuous addresses, the number of stored accesses reaches four, and then burst I / O access is performed at 609. Convert to and execute. When an interrupt or timeout occurs, all the access accumulated up to that point is a single I / O.
It is discharged as an access, the burst I / O access designating bit 14 is automatically cleared, the state transits to 602, and the normal state before the burst I / O access designating bit 14 is set is returned.

As a result, in the burst access conversion mode, it is possible to prevent the performance from being deteriorated due to the fact that the data is not easily accumulated.

The second is cancellation of burst I / O access due to an interrupt. When there is an interrupt request from the system bus, interrupt processing must be performed as quickly as possible. Therefore, it is possible to forcibly clear the access designation bit 14 by the burst I / O access cancel signal 43 due to an interrupt from the system bus, and to discharge the accumulated access request to the system bus as a single I / O access. To perform. The third is a case where addresses are discontinuous due to process switches or the like. To address this, the addresses are constantly monitored by the comparators 10 and 11 that determine whether the write or read access address is a continuous address, and the access designation bit 14 is forcibly set when the addresses become discontinuous. The control is performed by clearing and discharging the accumulated access request to the system bus as a single I / O access. A transition diagram of a series of these operations is shown in FIG. In the same figure ,,, and are FIFOs (first-in first-out) of the address portion of the I / O write buffer or the I / O read buffer, and are stored first and are first discharged. In addition, the operation flow chart is shown in FIG.
Shown in.

When performing the burst access conversion mode,
First, immediately after the start of 401, the burst I / O access designation bit 14 is set at 402. After this, as in 403, it is constantly monitored whether an interrupt or timeout occurs. If an interrupt or timeout occurs,
After transitioning to 410, all the access accumulated up to that point is discharged as a single I / O access, the burst I / O access designation bit 14 is automatically cleared at 411, and terminated at 412 to return to the normal state. If the determination is made at 404 and there is an access, the data is stored in the buffer at 405 without performing a single I / O access. Then, in 406, it is determined whether or not the address is a continuous address. If it is not a continuous address, transition to 410 is performed, and all the accesses accumulated up to that point are discharged as single-shot I / O accesses, and at 411, burst I / O access designation bit 14
Is automatically cleared, and the process ends at 412 and returns to the normal state.
In the case of continuous addresses, if the number of accesses stored in 407 is less than 4, transition to 403, and if the number of stored accesses reaches 4, burst I in 408.
Convert to / O access and execute. After that, it is judged at 409 whether or not the burst I / O access designation bit 14 is cleared by the processor. If not cleared, the process returns to 403 to repeat the above series of operations. If the burst I / O access designation bit 14 is cleared by the processor, control ends in 412 and returns to the normal state.

Regarding the arbitration of the processor bus, when the burst I / O access designation bit 14 is set by a processor, the processor bus arbiter 2 times out, interrupts, and causes the processor to perform the burst I / O access. , A control such that the bus use right is not passed to a processor other than the processor that sets the burst I / O access designation bit 14 until the burst I / O access designation bit 14 is automatically cleared due to a mis-hit by the process switch. To do.

The operation of the bus arbiter at this time is shown in the flowchart of FIG. When performing the burst access conversion mode in a multiprocessor system, first 501
The burst I / O access designation bit 14 is set at 502 immediately after the start of. After this, on the multiprocessor bus 108, the bus right is fixed to the processor that sets the burst I / O access designation bit 14 at 502, that is, the bus right is granted to the processor other than the processor that sets the burst I / O access designation bit 14. The arbitration control of the multiprocessor bus 108 is changed so that it is not given. At 504, if there is an access, the data is stored in the buffer without performing the single I / O access, as in the case of the series of controls in FIG. Then, it is determined whether the address is a continuous address. If it is not a continuous address, all the accesses accumulated up to that point are discharged as single I / O access, and burst I / O access designation bit 1
4 is automatically cleared to return to the normal state, and in the case of continuous addresses, after the accumulated access count reaches 4, it is converted to burst I / O access at 506 and executed. During this time, constantly monitor 505 for interrupts or timeouts. When an interrupt or a timeout occurs, the transition is made to 507, all the access accumulated up to that point is discharged as a single I / O access, the burst I / O access designation bit 14 is automatically cleared, and the burst I / O is set at 502. After releasing the bus right fixed to the processor in which the O access designation bit 14 is set, the processing ends at 508 and returns to the normal state.

Next, a second embodiment of the present invention will be described with reference to FIGS. 7 and 8. In this embodiment, as shown in FIG. 8, the main memory 104 of the first embodiment is directly connected to the bus converter 111 via the memory bus 112, and the main memory access of the processor and the I / O on the system bus are performed. It is configured to improve the efficiency of DMA (Direct Memory Access) transfer. The present applicant has previously established this system configuration in Japanese Patent Application No. 2-144301.
Filed as "bus system for information processing equipment".

FIG. 7 shows the bus converter 111 of this embodiment.
52 is a detailed block diagram of the main memory for four stages (M
M) write buffer address part, 53 main memory (MM) write buffer data part, 54 four-stage main memory (MM) read buffer address part, 55
Is the data section of the main memory (MM) read buffer, 5
6 is an input data latch from the memory bus, 57 is an output data latch to the memory bus, 58 is a memory bus access address latch, 59 is a main memory control unit, 60 is a DMA controller, and 61, 62, 63 and 64 are selectors. , 65 are control signals for the main memory control unit at the time of DMA, 6
6 is a system bus control unit control signal at the time of DMA, 67 is D
A system bus address for MA, 68 is a memory bus address for DMA, 69 is a data bus on the memory bus, 70 is a memory bus control signal, and 71 is an address bus on the memory bus. Also here, the main memory is directly connected to the bus converter 111 to access the main memory of the processor and DM from the I / O on the system bus.
The same control as in the first embodiment is performed except that the configuration is made to improve the efficiency of A transfer.

In the present embodiment, the transfer between the processor and the memory and the transfer between the I / O and the memory are possible even while the I / O access is accumulated in the buffer in the burst access conversion mode. There is an effect that the data processing efficiency is further improved as compared with the first embodiment.

[0033]

According to the present invention described in detail above, burst access to the system bus is carried out after the data is accumulated in the continuous access of the addresses among the I / O accesses which go out to the system bus in one shot. By providing a bit that specifies the activation of the burst transfer mode, it becomes possible to selectively use the burst transfer mode by software, and the address cycle that was output every single I / O access is blocked once. Since it is sufficient to output the data once for each transfer, the access speed can be increased, and the bus occupation time can be shortened when the same amount of data is transferred, and the bus usage efficiency is improved. This has the effect of preventing a reduction in processing efficiency, such as faster access to the system bus as a single I / O access when the I / O access interval is very long. Further, the number of times of arbitration is reduced, performance deterioration due to overhead of arbitration can be prevented, and bus usage efficiency is improved. In addition, when a multiprocessor system is built, when the bit that specifies that the burst transfer is activated to the system bus after the data is accumulated in the bus arbiter of the processor bus is set, the data for the number of burst transfers is set. By granting the bus right of the processor bus only to the processor that sets this bit until is accumulated, it is possible to prevent the mode conversion efficiency from being lowered due to the switching of the processor. On the other hand, when an interrupt request is issued to the processor, it is possible to automatically return to the normal mode to perform interrupt processing with good responsiveness. Further, when addresses are no longer continuous, by providing means for automatically clearing this bit and returning to the normal mode, there is an effect that it is possible to flexibly cope with the program switch.

[Brief description of drawings]

FIG. 1 is a detailed block diagram of a bus converter according to a first embodiment of the present invention.

FIG. 2 is a system configuration diagram of the first embodiment of the present invention.

FIG. 3 is an operation transition diagram of the first embodiment of the present invention.

FIG. 4 is an operation flowchart of the first embodiment of the present invention.

FIG. 5 is an operation flowchart of the processor bus arbiter according to the first embodiment of this invention.

FIG. 6 is an operation flowchart of the timer according to the first embodiment of this invention.

FIG. 7 is a detailed block diagram of a bus converter according to a second embodiment of the present invention.

FIG. 8 is a system configuration diagram of a second embodiment of the present invention.

FIG. 9 is a timing chart of burst access.

[Explanation of symbols]

100 ... Bus converter, 2 ... Processor bus arbiter, 3 ... Processor bus control unit, 4 ... I / O write buffer address unit, 5 ... I / O write buffer data unit, 6 ... I / O read buffer address unit , 7 ... data part of I / O read buffer, 8 ... input latch from processor bus, 9 ... output latch to processor bus, 10, 11 ... comparator, 12 ... control register group, 13 ... burst I / O access control Control register, 14 ... Burst I / O access designation bit, 15 ... Timer, 16 ... Interrupt control unit, 17 ... System bus control block, 18 ... System bus signal control unit, 19 ... I / O access control unit, 20 ... Single-shot I / O access control unit, 21 ... Burst I / O access control unit, 22 ... System Address latch for bus access, 23 ... Output data latch to system bus, 24 ... Input data latch from system bus, 25 ... OR gate, 26, 27, 28 ... Inverter, 29, 30 ... Selector, 31 ... Processor Interrupt request signal, 32 ... Processor bus arbitration signal, 33 ... Processor bus control signal, 34 ... Processor bus address / data bus, 35 ... Burst I / O access designation signal, 36 ... Burst I / O access designation bit clear and Timer reset signal, 37 ... Burst I / O access control signal, 38 ... Interrupt request signal, 39 ... System bus control signal, 40 ... System bus address / data bus, 41, 42 ... Address hit signal, 43 ... Burst I / Cancel O access No., cancel signal burst I / O access by 44 ... timer, 45 ... internal control signals.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kenichi Kurosawa             Hitachi, Ltd. 4026 Kujicho, Hitachi City, Ibaraki Prefecture             Inside Hitachi Research Laboratory (72) Inventor Seiji Kaneko             1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Stock             Hitachi Systems Development Laboratory (72) Inventor Hideaki Genma             810 Shimoimazumi, Ebina City, Kanagawa Prefecture Co., Ltd.             Hitachi Office System Design and Development Center             Within (72) Inventor Koichi Okazawa             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi, Ltd. Microelectronics             Equipment Development Laboratory (72) Inventor Masatsugu Shinozaki             810 Shimoimazumi, Ebina City, Kanagawa Prefecture Co., Ltd.             Hitachi Office System Design and Development Center             Within

Claims (10)

[Claims] 1. Information having a bus interface between a processor bus to which at least one or more processors are connected and a system bus to which a main memory of the processor and I / O (input / output device) are connected. In the processing system, a buffer that stores an access address and data between the processor bus and the system bus, a unit that determines whether the access destination stored in the buffer is a continuous address, and the determination unit is the buffer. A bus control system comprising means for converting the addresses into burst transfers (block transfers) and accessing the system bus when it is detected that the access destinations stored in the system are continuous addresses. 2. The bus interface has a control register connected to the processor bus, and the judging means refers to a burst I / O access designating bit provided in the control register to store the data in the buffer. 2. The bus control system according to claim 1, wherein it is determined whether or not to convert the stored data into burst transfer (block transfer). 3. The bus interface has a timer means that is activated when a single access request is made to the system bus from the processor bus side, and before the timer means counts a predetermined value, Next, it waits for a single access request from the processor bus side to the system bus. In the case of continuous addresses, burst transfer (block transfer) is converted to access the system bus. 3. The bus control system according to claim 2, wherein the bus control system is controlled so that a single access is made to the system bus. 4. After the timer means counts the predetermined value, the bus right of the system bus is acquired and the access request accumulated in the buffer is controlled to be accessed as a single access to the system bus. 4. The bus control system according to claim 3, wherein: 5. When the processor bus side knows in advance that the access destination to the system bus is a continuous address, the burst I / O access designation bit in the control register is set, and data for a plurality of times is set. Are stored in the buffer, they are converted into burst transfers (block transfers) to access the system bus, and then the burst I / O access designation bit in the control register is cleared. The bus control system according to claim 2, wherein: 6. The information processing system is a multiprocessor system in which a plurality of the processors connected to the processor bus are present, and one of the processors has the burst I / O access designation bit in the control register. The bus control system according to any one of claims 2 to 5, wherein when set to, the bus right of the processor bus is not passed to another processor until data for a burst transfer is accumulated in the buffer. 7. When one of the processors sets the burst I / O access designating bit in the control register, the one processor is arbitrated for the system bus until data for burst transfer is accumulated in the buffer. 6. The bus control system according to claim 2, wherein the bus control system does not participate in. 8. An information processing system comprising a processor bus to which at least one processor is connected, and a bus interface means of a system bus to which I / O (input / output device) means and the like are connected, Between the processor bus and the system bus, a buffer means for accumulating at least an access address and data for an access request to the I / O means is provided, and a plurality of the addresses and data are accumulated in the buffer means, and access destinations thereof are provided. Is a continuous address, it is converted into burst transfer (block transfer) to access the system bus. 9. The bus interface means is a three-way bus interface of the processor bus, the system bus, and a memory bus for accessing a main memory of the processor. Bus control method. 10. The buffer means is provided in each of the transfer paths between the processor bus and the memory bus, between the processor bus and the system bus, and between the memory bus and the system bus. The bus control system according to claim 9.