JPS6116592A - Manufacture of chip of semiconductor laser - Google Patents
Manufacture of chip of semiconductor laserInfo
- Publication number
- JPS6116592A JPS6116592A JP59137678A JP13767884A JPS6116592A JP S6116592 A JPS6116592 A JP S6116592A JP 59137678 A JP59137678 A JP 59137678A JP 13767884 A JP13767884 A JP 13767884A JP S6116592 A JPS6116592 A JP S6116592A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- adhesive sheet
- wafer
- coating
- cleavage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
- H01S5/0202—Cleaving
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2301/00—Functional characteristics
- H01S2301/17—Semiconductor lasers comprising special layers
- H01S2301/176—Specific passivation layers on surfaces other than the emission facet
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Dicing (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体レーザのチップを製造する方法に関し、
詳しくは、へき関した端面に酸化防止用のコーティング
を施こす工程に特徴を有するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor laser chip.
Specifically, the process is characterized by applying an anti-oxidation coating to the separated end faces.
半導体レーザのチップは素材ウエハをへき開して得られ
た細長いウエハ小片をその長手方向に細断して形成され
るものであり、発光端面となるへき開面の酸化を防止し
て寿命を延ばすためにSi3N。Semiconductor laser chips are formed by cleaving a raw material wafer and cutting the obtained long thin wafer pieces into pieces in the longitudinal direction.In order to extend the life of the semiconductor laser by preventing oxidation of the cleavage plane, which becomes the light-emitting end face, Si3N.
又はAl2O3等の被膜をコーティングしている。Alternatively, it is coated with a film such as Al2O3.
この場合、従来は、ウエハからへき開分断したウェハ小
片の1本ごとに端面コーティングを施こし、その後にこ
のウエハ小片を長手方向に所定ピッチで細断していた。In this case, conventionally, an end face coating was applied to each small wafer piece that was cleaved from the wafer, and then the small wafer pieces were cut into pieces at a predetermined pitch in the longitudinal direction.
上記手段は、ウェハ小片を1本ごと扱うために、コーテ
ィング装置への装填や取出しに時間がか\す、生産性が
低いものとなっていた。In the above-mentioned means, since each wafer piece is handled one by one, it takes time to load and unload the coating device, resulting in low productivity.
又、上記手段で得られたチップは第10図に示すように
、へき開面Sにのみ酸化防止被膜15が形成され、細断
面である両側面Tには何んらコーティングが施こされず
、チップ本体のpu接合部が露出するものであったため
に、ヒートシンク等にチップ表面が融着される際に、P
N接合部がチップ側面においてロー材の回り込みで短絡
さ1することかあり、組立て歩留り、及び性能の信頼性
が低下する問題が生じていた。Further, as shown in FIG. 10, the chip obtained by the above method has an antioxidant coating 15 formed only on the cleavage surface S, and no coating is applied on both side surfaces T, which are narrow sections. Since the PU joint of the chip body was exposed, when the chip surface was fused to a heat sink etc.
The N-junction may be short-circuited at the side surface of the chip due to the brazing material wrapping around the chip, resulting in a problem of lower assembly yield and performance reliability.
本発明は、端面酸化防止用のコーティング手段に改良を
施こすことによって、ウェハ単位の処理を可能にし、生
産性の高いチップ製造を行うことができるとともに、組
立て歩留り及び性能信頼性の向上を図ることができるチ
ップ製造方法を提供しようとしたものである。By improving the coating means for preventing edge oxidation, the present invention enables wafer-by-wafer processing, enables highly productive chip manufacturing, and improves assembly yield and performance reliability. This is an attempt to provide a chip manufacturing method that can.
このため、本発明においては、以下の各工程を含む方法
を採用した。Therefore, in the present invention, a method including the following steps was adopted.
■ 素材ウェハの、へき開起点用ケガキ傷を形成する面
に、アルカリ可溶のポジレストラコーティングする工程
。■ The process of coating the surface of the raw wafer where the scribe scratches for cleavage starting points are to be formed with an alkali-soluble PosiRestra coating.
■ 前記ケガキ傷の形成面を露呈させた状態で粘着シー
ト上に貼着したウェハを、シート外面からの印圧によっ
てへき開処理する工程。(2) A step of cleaving the wafer adhered to the adhesive sheet with the surface on which the scratches are formed exposed by applying pressure from the outer surface of the sheet.
■ 粘着シート上で各ウェハ小片を、その長手方向に所
定ピッチで細断してチップ群を形成する工程。■ A process in which each wafer piece is cut into pieces at a predetermined pitch in the longitudinal direction on an adhesive sheet to form a group of chips.
■ 粘着シートを伸展して各チップを互いに分離する工
程。■ The process of stretching the adhesive sheet and separating each chip from each other.
■ 粘着シート上で分離されたチップ群の露呈面全面に
酸化防止被膜をコーティングする工程。■ The process of coating the entire exposed surface of a group of chips separated on an adhesive sheet with an antioxidant film.
■ 各チップのポジレストをアルカリで溶解除去したの
ち、水洗・乾燥する工程。■ Process of dissolving and removing the positive rest of each chip with alkali, washing with water, and drying.
上記方法によると、貼着シートに貼着したウェハ単位ご
とにへき開、酸化防止被膜のコーティング、細断、及び
チップの分離を一連に行うことになる。又、分離された
チップのへき開面はもちろんのこと、その側面にも酸化
防止被膜がコーティングされる。According to the above method, cleaving, coating with an antioxidant film, shredding, and separation of chips are performed in a series for each wafer attached to the adhesive sheet. Furthermore, not only the cleavage planes of the separated chips but also their side surfaces are coated with an antioxidant coating.
以下に、本発明方法の各工程を図面に基づいて順次的に
説明する。Below, each step of the method of the present invention will be sequentially explained based on the drawings.
■ へき開削処理工程(第1図乃至第3図参照)電極面
を上面にした半導体レーザの素材ウニ/・1は、予めア
ルカリで溶解可能なポジレジスト (例えばA Z 1
350 )の保護被膜が上面にコーティングされており
、このウェハ1が真空チャック2を備えた可動テーブル
3の上面に吸着固定され、一定ピツチづつ側方に間欠移
動される。保護被膜がコーティングされたウェハ1の上
面には15μ程度の厚さのアルミ箔4が添着されるとと
もに、ウエハ1の前端縁の上面はアルミ箔4の前端より
少し露呈される。■ Cleavage treatment process (see Figures 1 to 3) The material of the semiconductor laser with the electrode surface facing up is the positive resist (for example, A Z 1) that can be dissolved in an alkali in advance.
A protective film (350) is coated on the upper surface of the wafer 1, and the wafer 1 is suctioned and fixed on the upper surface of a movable table 3 equipped with a vacuum chuck 2, and is intermittently moved laterally at a constant pitch. An aluminum foil 4 having a thickness of about 15 μm is attached to the upper surface of the wafer 1 coated with a protective film, and the upper surface of the front edge of the wafer 1 is slightly exposed than the front edge of the aluminum foil 4.
テーブル3の上方には上下及び前後に駆動されるダイヤ
モンドスクライバ−5が配備され、そのダイヤモンド針
6がウェハ1の後端側においてウェハ1から外れた位置
でアルミ箔4上に落下され、引続いてウエハ1上を通過
して前方に掃引移動される。A diamond scriber 5 that is driven up and down and back and forth is provided above the table 3, and its diamond scriber 6 is dropped onto the aluminum foil 4 at a position away from the wafer 1 on the rear end side of the wafer 1, and then The wafer 1 is then swept forward, passing over the wafer 1.
そして、アルミ箔4の前端縁から露呈されたウェハ前端
縁上にのみへき開起点用のケガキ傷7が形成される。Then, a scribing scratch 7 for a cleavage starting point is formed only on the front edge of the wafer exposed from the front edge of the aluminum foil 4.
上記作動をテーブル3の定ピッチ送りごとに繰返してウ
ェハ1の前端縁上に一定ピッチで多数のケガキ傷7・・
が形成され、このウェハ1が、片面が粘着面Aに形成さ
れたビニール等の伸展可能な軟質プラスチック製の粘着
シート8上に、ケガキ傷7が露呈されるように貼着され
る。The above operation is repeated every time the table 3 is fed at a fixed pitch, resulting in a large number of scratches 7 on the front edge of the wafer 1 at a fixed pitch.
is formed, and this wafer 1 is pasted onto an adhesive sheet 8 made of extensible soft plastic such as vinyl and having an adhesive surface A on one side so that the scribing scratches 7 are exposed.
■ へき開処理工程(第4図参照)
次に、大径ゴムローラ9と、これに対向する硬質の小径
ローラ10との間に、ウェハ1をゴムローラ9側にして
粘着シート8を供給通過させる。(2) Cleavage process (see FIG. 4) Next, the adhesive sheet 8 is fed and passed between the large-diameter rubber roller 9 and the hard small-diameter roller 10 opposing it, with the wafer 1 facing the rubber roller 9 side.
すると、ウエハ1は小径ローラ10の作用部においてゴ
ムローラ9側に加圧され彎曲され、各ケガキ傷7を起点
としてへき開が進行し、粘着シート8の下面に多数のウ
ェハ小片11が並列状に貼着された状態でローラ間から
出てくる。Then, the wafer 1 is pressed against the rubber roller 9 side at the action part of the small-diameter roller 10 and is bent, and cleavage progresses starting from each scribing scratch 7, and a large number of wafer pieces 11 are pasted in parallel on the lower surface of the adhesive sheet 8. It comes out from between the rollers in a state where it is covered.
■ 細断線形成工程(第5図参照)
上記のようにウェハ小片11群を並列貼着17た粘着シ
ート8は、間欠送りされる可動テーブル16上に吸着保
持され、ダイヤモンドスクライバー17によって小片1
1群の上面に、小片長手方向に一定のピッチで細断線と
してのケガキ傷18が形成される。■ Shredding line forming process (see Figure 5) The adhesive sheet 8 on which 11 groups of wafer pieces are pasted 17 in parallel as described above is held by suction on a movable table 16 that is fed intermittently, and a diamond scriber 17 cuts the pieces 1 into pieces.
On the upper surface of the first group, scribing scratches 18 are formed as shredding lines at a constant pitch in the longitudinal direction of the small pieces.
■ 細断工程
細断線18群が形成されたウエハ小片11群は、第4図
に示したローラ式へき聞手段と同様な押圧手段を用いて
、各細断線18で細断され、縦横に並列されたチップ1
9群が得られる。■ Shredding process The 11 groups of wafer pieces on which the 18 groups of shredding lines have been formed are shredded along each shredding line 18 using a pressing means similar to the roller-type cracking means shown in FIG. chip 1
Nine groups are obtained.
■ チップ分離工程(第6図参照)
チップ19群が貼着された粘着シート8は、その端縁が
チャック20によって挟持固定された状態でリフタ21
上に装着され、リフタ下方のヒータ22で適当に加熱さ
れたのち、リフタ21の上昇によってシート8は大きく
伸長され、貼着された各チップ19は適当間隔をあけて
分離される。■ Chip separation process (see Fig. 6) The adhesive sheet 8 to which the group of chips 19 is attached is placed in the lifter 21 with its edge being clamped and fixed by the chuck 20.
After being appropriately heated by the heater 22 below the lifter, the sheet 8 is greatly expanded by the lifter 21 rising, and the attached chips 19 are separated at appropriate intervals.
このシート伸長処理を前後・左右方向に各別、もしくは
同時に行うと七によって第〒図に示すように、縦横に互
いに分離されたチップ19群を得ることができる。If this sheet stretching process is carried out separately or simultaneously in the front-back and left-right directions, groups of 19 chips separated vertically and horizontally can be obtained as shown in FIG.
■ 酸化防止被膜コーティング工程(第8図参照)次に
、チップ19群を分離貼着したま\の粘着シート8が低
温気相成長装置又はスパッタ装置に導入され、シート8
及び先にコーティングしたポジレジスト14に悪影響を
与えない比較的低温条件で、813N4、Sl、S i
O2又はA]、203等の酸化防止被膜15が各チップ
の露呈面全面にコーティングされる。■ Antioxidant film coating process (see Figure 8) Next, the adhesive sheet 8 with the chip 19 group separated and pasted is introduced into a low temperature vapor phase growth device or sputtering device, and the sheet 8
and 813N4, Sl, Si under relatively low temperature conditions that do not adversely affect the previously coated positive resist 14.
An antioxidant coating 15 such as O2 or A], 203 is coated over the entire exposed surface of each chip.
■ 保護被膜除去工程
次に、アルカリ液、例えば10%NaO爪でポジレジス
ト14を溶解除去して、その上層の酸化防止被膜部分も
除去したのち、充分水洗し乾燥される。これによって、
第9図に示すように、へき開面Sのみならず両側面Tに
も酸化防止被膜15を残したチップ19が得られる。(2) Protective film removal step Next, the positive resist 14 is dissolved and removed using an alkaline solution, for example, a 10% NaO nail, and the upper layer of the anti-oxidation film is also removed, followed by thorough washing with water and drying. by this,
As shown in FIG. 9, a chip 19 is obtained in which the antioxidant coating 15 is left not only on the cleavage surface S but also on both side surfaces T.
尚、上記のようにして得られたチップ19は特性チェッ
クの後、/−ト8に貼着したま\で組立工程に移される
ことになる。Incidentally, after checking the characteristics of the chip 19 obtained as described above, the chip 19 is transferred to the assembly process while being attached to the plate 8.
以上説明したように、本発明方法によれば、貼着シート
を用いてウエハ単位ごとにへき開、細断、酸化防止被膜
のコーティング、チップの分離を一連に行うことができ
、生産性を極めて向上することが可能となった。As explained above, according to the method of the present invention, each wafer can be cleaved, shredded, coated with an antioxidant film, and separated into chips using an adhesive sheet, which greatly improves productivity. It became possible to do so.
そして、特に本発明によれば、酸化防止被膜をへき開面
のみならず、チップ側面にも同時にコーティングするた
めに、チップ表面をヒートンンク° 等に融着連結する
場合においても側面コーティングがPN接合部を短絡す
る絶縁材として働き、組立て歩留り、及び性能信頼性の
向上を図ることができた。In particular, according to the present invention, since the antioxidant coating is applied not only to the cleavage surface but also to the side surfaces of the chip at the same time, the side surface coating covers the PN junction even when the chip surface is fused and connected to a heat tank or the like. It acted as an insulating material to prevent short circuits, improving assembly yield and performance reliability.
第1図は本発明方法におけるへき開前処理手段の斜視図
、第2図はその側面図、第3図はへき開用の前処理の完
了したウエハを示す斜視図、第4図はへき開処理手段の
斜視図、第5図は細断線形成子段の斜視図、第6図はチ
ップ分離手段の側面図、第7図は分離処理後のチップを
示す斜視図、第8図は酸化防止被膜コーティング処理の
完了したチップ群を示す一部切欠き斜視図、第9図は完
成したチップ単体の拡大斜視図、第10図は従来方法で
得られたチップ単体の拡大斜視図である01・・ウェハ
、4・・アルミ箔、7・・ケガキ傷、8・・粘着シート
、19・・チップ。
出 願 人 ローム株式会社
代 理 人 弁理士岡田和秀FIG. 1 is a perspective view of the cleavage pretreatment means in the method of the present invention, FIG. 2 is a side view thereof, FIG. 3 is a perspective view of a wafer that has been pretreated for cleavage, and FIG. 4 is a perspective view of the cleavage treatment means. A perspective view, FIG. 5 is a perspective view of the chopping wire forming element stage, FIG. 6 is a side view of the chip separation means, FIG. 7 is a perspective view showing chips after separation processing, and FIG. 8 is an antioxidant film coating treatment. FIG. 9 is an enlarged perspective view of a single completed chip, and FIG. 10 is an enlarged perspective view of a single chip obtained by the conventional method. 4. Aluminum foil, 7. Marking scratches, 8. Adhesive sheet, 19. Chip. Applicant: ROHM Co., Ltd. Agent: Kazuhide Okada, patent attorney
Claims (1)
面に、アルカリ可溶のポジレジストをコーティングする
工程と、前記ケガキ傷の形成面を露呈させた状態で粘着
シート上に貼着したウェハを、シート外面からの印圧に
よつてへき開処理する工程と、粘着シート上で各ウェハ
小片を、その長手方向に所定ピッチで細断してチップ群
を形成する工程と、粘着シートを伸展して各チップを互
いに分離する工程と、粘着シート上で分離されたチップ
群の露呈面全面にSiO_4、Si、SiO_2、Al
_2O_3等の酸化防止被膜をコーティングする工程と
、各チップのポジレジストをアルカリで溶解除去したの
ち、水洗・乾燥する工程とを含む半導体レーザのチップ
製造方法。(1) The process of coating the surface of the raw wafer with an alkali-soluble positive resist on which the scribe scratches for cleavage starting points are to be formed, and the wafer pasted on the adhesive sheet with the surface where the scribe scratches are formed exposed. A process of cleaving the wafer by applying pressure from the outer surface of the sheet, a process of cutting each wafer piece on the adhesive sheet into pieces at a predetermined pitch in the longitudinal direction to form chip groups, and a process of stretching the adhesive sheet. A process of separating each chip from each other using a pressure-sensitive adhesive sheet, and applying SiO_4, Si, SiO_2, and Al to the entire exposed surface of the separated chip group on the adhesive sheet.
A method for manufacturing a semiconductor laser chip, which includes a step of coating with an antioxidant film such as _2O_3, and a step of dissolving and removing the positive resist of each chip with an alkali, followed by washing and drying.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59137678A JPS6116592A (en) | 1984-07-02 | 1984-07-02 | Manufacture of chip of semiconductor laser |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59137678A JPS6116592A (en) | 1984-07-02 | 1984-07-02 | Manufacture of chip of semiconductor laser |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6116592A true JPS6116592A (en) | 1986-01-24 |
JPH0260076B2 JPH0260076B2 (en) | 1990-12-14 |
Family
ID=15204255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59137678A Granted JPS6116592A (en) | 1984-07-02 | 1984-07-02 | Manufacture of chip of semiconductor laser |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6116592A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5081895A (en) * | 1989-08-11 | 1992-01-21 | Kabushiki Kaisha Kawai Gakki Seisakusho | Keyboard |
WO2001086719A1 (en) * | 2000-05-10 | 2001-11-15 | Gemplus | Thin layer chip insulation for conductive polymer connection |
JP2007201305A (en) * | 2006-01-30 | 2007-08-09 | Sony Corp | Semiconductor laser device, semiconductor laser chip, and method for manufacturing semiconductor laser device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52134387A (en) * | 1976-05-06 | 1977-11-10 | Oki Electric Ind Co Ltd | Semiconductor laser device |
JPS55110088A (en) * | 1979-02-16 | 1980-08-25 | Mitsubishi Electric Corp | Measurement of semiconductor laser characteristic |
JPS5671952A (en) * | 1979-11-16 | 1981-06-15 | Nec Home Electronics Ltd | Breaking semiconductor wafer |
JPS58125886A (en) * | 1982-01-22 | 1983-07-27 | Hitachi Ltd | Manufacture of semiconductor device |
JPS58138050A (en) * | 1982-02-10 | 1983-08-16 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
-
1984
- 1984-07-02 JP JP59137678A patent/JPS6116592A/en active Granted
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52134387A (en) * | 1976-05-06 | 1977-11-10 | Oki Electric Ind Co Ltd | Semiconductor laser device |
JPS55110088A (en) * | 1979-02-16 | 1980-08-25 | Mitsubishi Electric Corp | Measurement of semiconductor laser characteristic |
JPS5671952A (en) * | 1979-11-16 | 1981-06-15 | Nec Home Electronics Ltd | Breaking semiconductor wafer |
JPS58125886A (en) * | 1982-01-22 | 1983-07-27 | Hitachi Ltd | Manufacture of semiconductor device |
JPS58138050A (en) * | 1982-02-10 | 1983-08-16 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5081895A (en) * | 1989-08-11 | 1992-01-21 | Kabushiki Kaisha Kawai Gakki Seisakusho | Keyboard |
WO2001086719A1 (en) * | 2000-05-10 | 2001-11-15 | Gemplus | Thin layer chip insulation for conductive polymer connection |
FR2808920A1 (en) * | 2000-05-10 | 2001-11-16 | Gemplus Card Int | Method for protecting chips arranged on a wafer comprises cutting wafer to loosen chips, depositing electrically insulating layer on active surface and flanks of at least one chip, and clearing at least one opening in the insulating layer |
JP2007201305A (en) * | 2006-01-30 | 2007-08-09 | Sony Corp | Semiconductor laser device, semiconductor laser chip, and method for manufacturing semiconductor laser device |
Also Published As
Publication number | Publication date |
---|---|
JPH0260076B2 (en) | 1990-12-14 |
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