JPS61165793A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image display device that displays both binary one-value data and multi-value data.

Conventional technology Conventionally, multi-value data 22 and 2 are displayed on one screen as shown in FIG.
When displaying a mixture of value data 23, an image display@haze as shown in FIG. 6 has been used. This has separate display memories 24 and 26 for multi-value data and binary data, and when displaying multi-value data, the O/A converter 25 converts the multi-value data into analog data, and the binary data is converted into an analog signal by n times. The signal is converted to an appropriate brightness level through a converter 21, and after this image processing, the sum of both analog values is calculated by an adder 28 and outputted to an output terminal 29 as a video signal.

Problems to be Solved by the Invention In such a conventional configuration, separate display memories are required for multi-value data and binary data, and after converting multi-value data into analog, binary data Since it is necessary to take the sum of the circuit configuration? ! It's rough.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image display device that can simultaneously display multi-value data and binary data with a simple configuration.

Means for Solving the Problems The image display device of the present invention includes a data display memory that stores binary data and multivalued data, and a 2fIi memory that stores the position where the binary data is displayed on the screen. A binary data display position address storage circuit detects the timing of binary data display by comparing the address that the display is sequentially scanning with the address read from the binary display position address storage circuit. - a multivalued data identification signal generation means; a data conversion means for synthesizing a pseudo child from the binary data read from the data display memory;
One of the data output from this data converting means and the multi-valued data read from the data display memory is converted into the 21!・
The present invention is characterized by further comprising a switching means for outputting display data based on the result of the multivalued data identification signal generating means.

Effect: With this configuration, when displaying binary 1m data and multi-value data, the data to be displayed is identified and the data is selected by the switching means. It can be displayed on one screen.

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 to 4. FIG. 1 shows a uniform display device of the present invention. In Figure 1, 1 is a data display memory that stores 2m data and multi-value data to be displayed, and 2 is a data bus coming from data display memory 1, the number of which depends on the number of gradation bits of the multi-value data to be displayed. Similarly, in this embodiment, if one image has 8-bit gradation, the data bus has eight data lines. Reference numeral 3 denotes one data line having the value of binary data on the data bus 2 coming from the data display memory 1. In this example, the binary data is sent to the most significant bit (hereinafter referred to as MSB). . 4 is a binary data/multi-value data conversion circuit for making the data line 3 equal to the number of data buses that multi-value data has, and 5 is a 2-value data/multi-value data conversion circuit after passing through the binary data/multi-value data conversion circuit 4. value data bus, 6 is a multiplexer for switching between binary data bus 5 and data bus 2;
8 is a D/A converter that converts the digital data on the data bus output from multiplexer 6 into analog; 8 is a display that displays the analog-converted data; 9 is a display for displaying the analog-converted data;
is a binary/multi-value data identification signal that specifies the switching state of the multiplexer 6, 10 is an identification signal generator that generates the binary/multi-value data identification signal 9, and the value is the binary data display position in which the stomach address is written. 12 is a display control circuit that controls the display 8; 13 is a display control circuit 12;
14 is a binary data display position address sent from the memory circuit value.

Next, the configuration shown in FIG. 1 will be explained in detail based on its operation.

First, binary data and multivalued data to be displayed on the display 8 are written into the data display memory 1.

At this time, when writing binary data, two
At the same time write the display position stirrup address where the value I data should be displayed. Furthermore, in this embodiment, binary data is written to the data display memory 1 using one of the eight data buses.
The signal is output to the main data line, in this embodiment, the MSB data line 3. Do it like this. Therefore, in the present invention, when data is written to the data display memory 1, the data is managed so that it can be determined whether the data to be written is binary or multi-valued. The data written in the data display memory 1 in this manner is sequentially sent to the data bus 2. Of this data bus 2, the MSB data line 3 through which the value of the binary data passes when the binary data is sent out.
enters the binary data/multivalue data conversion circuit 4. Two possible circuits for this are shown in FIG. 2 and FIG. 3.

In Figure 2, data line 3 is wired OR with 7 lines.
2 with a total of 8 data lines, which is the same as the multivalued data.
It becomes a value data bus 5, and binary data is pseudo-converted into multi-value data.

FIG. 3 shows a consideration of measures against flicker that occurs when displaying binary data such as characters. Reference numeral 15 denotes a switching circuit which connects the data line 3 to at least one of the eight output lines and sets the other outputs to the "L" level to pseudo-convert binary data into multi-value data. Reference numeral 16 denotes a control signal which specifies which of the eight output lines the switching circuit 15 connects the data line 3 to, and is output from the CPU 17.

The differences between Figure 3 and Figure 2 are as follows. In FIG. 2, wired OR was used, so the value when converting into multivalued data was fixed, but in FIG.
Since it controls whether to connect to the 8 data lines of
The brightness level when displaying binary data as multi-value data can be controlled. Generally, when a CRT is used as the display 8 for display, the relationship between the screen brightness and the flicker phenomenon is as shown in FIG. In this figure, the horizontal axis shows the brightness level on the screen, and the vertical axis shows the critical frequency of flicker. At this critical frequency, we perceive flickering in response to a stimulus in which light flickers periodically, but as we gradually increase the frequency of blinking, we eventually stop sensing flicker and it becomes indistinguishable from uniform light. The frequency at this limit is shown. Further, t in the figure is the afterglow time of the phosphor of the display, and indicates the afterglow time until the brightness drops to 5%. A normal CRT display uses a number of images per second of 50HZ or 60H2. As can be seen from this figure, there is a proportional relationship between the brightness on the screen and the critical frequency of flicker, and it can be seen that flicker can be suppressed by changing the value of brightness.

Therefore, in this embodiment, when flicker occurs due to the display state of binary data displayed on the display, the CPU 17 controls the switching circuit 15.
can be controlled to lower the brightness level of the two data to suppress flicker.

In the binary data/multi-value data conversion circuit 4 as described above, the binary data is pseudo-converted into multi-end data and has eight data lines.The binary data bus 5 is connected to one input of the multiplexer 6. It is connected to the. The data bus 2 is also connected to the other input of the multiplexer 6.

On the other hand, the binary data display position address stored in the memory circuit value is sent to the identification signal generator 1° during the display operation. Further, the display position address 13 of the scanning screen sent from the display division circuit 12 is also sent to the identification signal generation a10. This identification signal generator 1o compares the two address values and when they match, a binary/multi-value data identification signal 9 is generated.
is generated and sent to the multiplexer 6. Multiplexer 6 selects binary data bus 5 or data bus 2.
Select one. The signal selected by the multiplexer 6 in this manner is sent to the D/A converter 7, where it is converted into an analog signal and displayed on the display 8 as a video signal.

Effects of the invention As explained above, according to the image display system of the present invention,
A data display memory for storing binary data and multi-end data, a binary data display position address storage circuit for storing a position at which the two-value data is displayed on the screen, and a display are sequentially scanned. Address and said 21il!
binary/multi-value data identification signal generating means for detecting the timing of displaying binary data by comparing the address read from the display position address storage circuit; a data converting means for synthesizing pseudo multi-valued data from the output data of the data converting means and the multi-valued data read from the data display memory; Since a switching means for outputting display data based on the data is provided, binary data and multi-value data can be displayed simultaneously with a simple circuit configuration.

In addition, the data conversion means is a binary 1 of the data display memory.
In the case where the switching circuit for connecting the data read data line to any one of the plurality of output data lines is configured with an instruction means for externally instructing. The flicker phenomenon that occurs when displaying binary data such as characters can also be suppressed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the image display device of the present invention, and FIGS. 2 and 3 are 21i! in FIG. 1, respectively. First and second specific configuration diagrams of the data/multi-value data conversion circuit,
FIG. 4 is an explanatory diagram of the relationship between flicker and screen brightness, FIG. 5 is an explanatory diagram of a display screen in which 21m data and multi-value data are mixed, and FIG. 6 is a block diagram of a conventional image display device. DESCRIPTION OF SYMBOLS 1... Memory for data display, 4... Binary data/multi-value data conversion circuit, 6... Multiplexer, 10...
・Identification signal generator, value...Binary data display position address storage circuit, 12...Display control circuit agent Yoshihiro Morimoto No. z- Figure 3 Figure 4 Screen Q/I (ft.MuJ

Claims (1)

[Scope of Claims] 1. A data display memory that stores binary data and multi-value data, a binary data display position address storage circuit that stores a position where the binary data is displayed on a screen, and a display. A binary data display device that detects the timing of binary data display by comparing the address that the digital display is sequentially scanning with the address read from the binary display position address storage circuit.
a multivalued data identification signal generating means; a data conversion means for synthesizing pseudo multivalued data from the binary data read from the data display memory; and a data conversion means for synthesizing pseudo multivalued data from the data display memory. and switching means for outputting one of the multivalued data as display data based on the result of the binary/multivalued data identification signal generation means. 2. The data conversion means is composed of a switching circuit that connects the binary data reading data line of the data display memory to any one of the plurality of output data lines, and an instruction means that instructs this switching circuit from the outside. An image display device according to claim 1, characterized in that: