JPS6116366A - Vector data processor - Google Patents

Abstract

PURPOSE:To transfer element data in a high speed by transferring directly element data from the first vector storage means to the second vector storage means and setting the address following a maximum address as a minimum address to transfer element data successively. CONSTITUTION:A vector data processor is provided with vector registers 100 and 101, read address registers 110 and 111, write address registers 120 and 121, read address selecting circuits 130 and 131, write address selecting circuits 140 and 141, and an element data input selecting circuit 200. Element data are transferred directly between vector registers 100 and 101; and when the read address and the write address set by read address registers 110 and 111 and write address registers 120 and 121 reach maximum addresses, addresses following maximum addresses are set to minimum addresses to transfer element data successively.

Description

TECHNICAL FIELD The present invention relates to a vector data processing device that transfers element data between vector registers.

Prior Art A conventional vector data processing device is disclosed in U.S. Patent No. 4.128.
, No. 880 can be referred to. Referring to FIG. 2, according to this publication, vector registers 10 and 11, read/write address registers 20 and 21 . It is composed of an element data input selection circuit 30, an element data output selection circuit 40, and an arithmetic unit 50.

Vector registers IO and 11 hold a plurality of element data, and a plurality of them are usually provided. Read/write address registers 20 and 21 specify the location of element data held in vector registers 10 and 11, and are initially set to I.
□ Cleared to II and has a +1 power count function.

When performing a partial vector operation on two recommendation data held in one vector register, it is necessary to transfer part of the element data held in this vector register to another vector register.

For this purpose, a method is used to transfer element data using a store/load instruction between a vector register and a main memory, or a method is used to transfer element data using a shift instruction.

In the former method, the element data held in the vector register 10 is sequentially stored in the main memory by the amount specified by the vector length by a store instruction, and a part of the stored element data is loaded into the vector register 11. First, transfer source vector register 1 in the store instruction
In response to the specification of 0 and the vector length to be transferred, read/write
The write address register 20 is initialized to n011.

In response to this initial setting, location 0 of the element data held in the vector register 10 is output to the element data output selection circuit 4o, and as the read/write address register 20 counts up, the element data are sequentially output. Vector register 10 given via element data output selection circuit 40
The output data is sequentially transferred to main memory. Next, the address between the load start address of the element data necessary for partial vector operation in the load instruction and the vector register of the load destination is specified.
1 and the vector length designation, element data is sequentially loaded from the main memory to the vector register 11 according to the instructions of the read/write address register 21.

In the latter method, the element data held in the vector register IO is shifted word by word by a shift command and transferred to the vector register 11. A vector register 10 that holds element data to be shifted by a shift command and a vector register 11 that transfers the shift result.
, shift amount, and vector length, the element data held in the vector register 10 is sequentially output from location O to the element data output selection circuit 40 as the read/write address register 20 counts up. The output of the vector register 10 provided via the element data output selection circuit 40 is provided to the arithmetic unit 50. The arithmetic unit 50 performs a shift operation in response to the output of the element data output selection circuit 40 and the shift amount specified by the command. The shift amount is usually specified as a one word shift to the right. By shifting the element data by one word to the right and outputting it, the output of the arithmetic unit 50 is sent to the vector register 1 via the element data input selection circuit 30.
It is transferred in a format shifted by one word to 1. The read/write address register 21 also has a +1 count function and sequentially specifies element data no locations output from the element data input selection circuit 30. By repeating this shift operation, the predetermined element data transfer is completed. Therefore, both systems require a main memory IJ-arithmetic unit, which has the disadvantage that the performance of element data transfer is low and that there is contention when a subsequent instruction requires the main memory or an arithmetic unit.

OBJECTS OF THE INVENTION An object of the present invention is to enable direct transfer of data from a first vector storage means to a second vector storage means, set the address following the maximum address as the minimum address, and sequentially transfer elements An object of the present invention is to provide a vector data processing device that can transfer element data between vector registers at high speed by transferring data.

Structure of the Invention The vector data processing device of the present invention includes a first vector storage means for holding ordered element data, and an address that continues when the readout address of the first vector storage means reaches the maximum address. a first address setting means for setting the minimum address to a minimum address; a transfer means for sequentially transferring element data read from the address set by the first address setting means to a second vector storage means; The present invention is characterized in that it includes a second address setting means for setting the next address as the minimum address when the write address of the second vector storage means reaches the maximum address when the transfer means transfers the vector.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes vector registers 100 and 101, read address register 11,
0 and 111, write address registers 120 and 1211 read address selection circuits 130 and 131
, write address selection circuits 140 and 141, and element data input selection circuit 200.

The operation of this embodiment is as follows. A plurality of Ω vector registers, two vector registers 100 in this embodiment.
and 101, each of which holds a plurality of ordered element data, stores the calculation results output from the arithmetic unit or the load data output from the main memory. When performing a partial vector operation on element data held in one vector register, it is necessary to transfer part of the element data held in this vector register to another vector register.

The transfer source vector register holding the calculation results output from the arithmetic unit or the load data output from the main memory is set as the vector register 100, and a part of the element data stored in the vector register 100 is transferred. Transfer destination register to vector register 101
In this case, the instruction transfers the source vector register 1
The number 00 and the number of the destination vector register 101 are specified. The transfer source vector register read start address is input to the read address selection circuit 130 as a command or instruction accompanying information, but if it is not specified by the command, an IIO address is input.

Furthermore, the write start address to the transfer destination vector register is similarly input to the write address selection circuit 141 as an instruction or instruction accompanying information (not shown).
If not specified by the instruction, n01 is input.

Note that the setting paths for these start addresses are also not shown.

On the other hand, if the instruction is such that the source vector register number specifies vector register 101 and the destination vector register number specifies vector register 100, the source vector register read start address is specified as the instruction or instruction accompanying information. , read address selection circuit 1
31, and the write start address of the transfer destination vector register is similarly input to the write address selection circuit 140, although not shown, as an instruction or instruction accompanying information. In these cases as well, It 01 is input if it is not specified by the instruction.

Note that the setting paths for these start addresses are also not shown.

The maximum element data length that can be held in the vector registers 100 and 101 is 64 pieces each, and when transferring 32 pieces of element data from the vector register 100 to the vector register lot, first specify the vector length by l. '3211. The transfer source vector register number is set to vector register 1 by the instruction.
The OO1 transfer destination vector register number is designated as vector register lot, and the read start address of vector register 100 is designated as It321T. The read start address specified by the instruction is input to the read address selection circuit 130, selected, and the value l+32N is stored in the read address register 110. At the same time, since the write start address is not specified by the instruction, It□If is input to the write address selection circuit 141.

This is selected and the write address register 121 is set to n0.
1 is initialized. The vector register lOO transfers the element data at the location specified by the read address register 110 to the element data input selection circuit 200.
Output to. The read address register 110 has a +1 count function for sequentially reading out element data.
The next location after location 32 is counted as location 33, and the next location is counted as location 34. Vector register 10 is added to the counted location for the specified vector length.
Element data held within 0 is read out and output to element data input selection circuit 200. Element data input selection circuit 200 is vector register 1
A selection instruction is given to input the element data read from 00 into the vector register 101.

On the other hand, the vector register 101 starts writing element data to the location specified by the write address register 121 at the time when the first element data is output from the element data input selection circuit 200. Like the read address register 110, the write address register 121 also has a +1 count function for sequentially writing element data, and the next one after locator=i10 is counted as location 1, and the next one is counted as locator M/2. Element data output from the element data input selection circuit 200 is written to the counted location by the amount specified by the vector length. This operation ends when the number of transferred element data reaches 132'', that is, when it becomes equal to the vector length specification.

When the read start address of the transfer source vector register is defined as m, if a value of 64-(m-t) or more is specified by the vector length specification, the following will occur. That is, the read address register 110 is the vector register 100.
When the location number 63 is reached, the next location is designated 0, and the function is to sequentially count by the designated number of vector lengths.

In another instruction, specify the transfer source vector register number as vector register 100, the transfer destination vector register number as vector register 101, and specify vector register 101 as the transfer source vector register number.
Assume that the write start address of is specified as 32. Since the read start address is not specified by the instruction, II□l is input to the read address selection circuit 130, which is selected and set to the read address register 110 as II□n.
is initialized. The write start address designated by the instruction is input to the write address selection circuit 141, selected, and a value of 32 is stored in the write address register 121. The read address register 110 has a +1 output count function. In response to the address from register 110, element data is sequentially read from location 0 of vector register 100 and output to element data input selection circuit 200. The write address register similarly has a +l count function, and starts writing when the element data input selection circuit 200 outputs the first element data, that is, the element data read from location 0 of the vector register 100. . In this operation, the number of element data transferred is If 3
It ends when it reaches 21, that is, when it becomes equal to the vector length designation. Furthermore, when the write start address of the transfer destination is m, if a value greater than or equal to 64-(m-1) is specified in the vector length specification, the write address register 121 is set to 1 in the vector register 101.
When it reaches 163If, it returns to location 0.
It has a function of sequentially counting the specified number of vector lengths.

Furthermore, another instruction specifies the transfer source vector register number as vector register 1001 and the transfer destination vector register number as vector register 101.
Set the read start address of 0 to "32-vector register 1"
Assume that the write start address of 01 is specified as ll3211. Since both the read start address and the write start address are specified by the instruction, the start address 13211 is input to the read address selection circuit 130 and the write address selection circuit 141, respectively, and is selected, and the read address register 110 and the write address register 121. Since the read address register 110 has a +1 output count function, it sequentially reads vector data from the location 32 of the vector register lOO and outputs it to the element data input selection circuit 200. The write address register 121 also has a +1 count function, and sequentially writes the element data output from the element data input selection circuit 200 from the location 32 of the vector register 101. In this operation, the number of element data transferred is N 321
It ends when it reaches 1, that is, when it becomes equal to the vector length specification. Further, when the read start address and write start address are m and n, respectively, if the vector length designation is greater than 64-(m-1), the contents of the read address register return from 63 to O and continue counting. If the vector length designation is greater than 64-(n-1), the contents of the write address register return from 63 to 0 and continue counting.

In this embodiment, the number of vector registers is two, but the present invention is not limited to two, and the element data transfer source is the vector register 100, and the transfer destination is the vector register 101. It is not limited and can be specified arbitrarily by command.

Effects of the Invention The present invention includes element data transfer means between vector storage means, and address setting means for setting the following address to the minimum address when the address reaches the maximum address. This has the effect of realizing high-speed data transfer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. 10.11, 100, 101...Vector register, 20,21...-Read/write address register, 20,200...Element data input selection circuit, 40... ...Element data output selection circuit, 50... Arithmetic unit, 110, 111.
...Read address register, 120, 121.
...Write address register, 130, 131.
... Read address selection circuit, 140, 141.
...Write address selection circuit. ／−１＼ Agent Patent Attorney Susumu Uchihara ,′、−１−also□
The old rod Z that takes ten noton once in a half

Claims (1)

[Claims] A first vector storage means for holding ordered element data, and a first vector storage means for setting the next address as the minimum address when the read address of the first vector storage means becomes the maximum address. an address setting means; a transfer means for sequentially transferring the element data read from the address set by the first address setting means to a second vector storage means; A vector data processing device comprising second address setting means for setting a subsequent address as the minimum address when the write address of the means reaches the maximum address.