JPS6116355A - Bus switching device of data transfer system - Google Patents
Bus switching device of data transfer systemInfo
- Publication number
- JPS6116355A JPS6116355A JP13651284A JP13651284A JPS6116355A JP S6116355 A JPS6116355 A JP S6116355A JP 13651284 A JP13651284 A JP 13651284A JP 13651284 A JP13651284 A JP 13651284A JP S6116355 A JPS6116355 A JP S6116355A
- Authority
- JP
- Japan
- Prior art keywords
- input
- signal line
- transfer request
- output
- bus switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、データチャネル装置と複数の入出力制御装置
とを一組の入出力パスで接続したデータ転送システムの
パス切換装蟹に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a path switching device for a data transfer system in which a data channel device and a plurality of input/output control devices are connected by a set of input/output paths.
従来のデータ転送システムの構成例を第1図に示す。 An example of the configuration of a conventional data transfer system is shown in FIG.
第1図において例えば入出力制御装置(以下IOCと略
す)4から発せられる転送要求信号線(以下REQと略
す。)301はl0C3、l0C2の内部回路素子を経
由して、原にREQ 201 。In FIG. 1, for example, a transfer request signal line (hereinafter referred to as REQ) 301 issued from an input/output control device (hereinafter referred to as IOC) 4 is transmitted via internal circuit elements of 10C3 and 10C2 to REQ 201.
REQIOIとなり、最徒にデータチャネル装置1に伝
わる。This becomes the REQIOI and is finally transmitted to the data channel device 1.
また上記REQIOIに応答してデータチャネル装置1
よプ発せられる転送要求受付信号線(以下ACKと略す
)102は、l0c2.l0C3の内部回路素子を経由
して順にACK 202 、 ACK 302となり、
最後にl0C4に伝わる。尚110はデータ及びアドレ
スバスである。ここでl0C2またはIOC3の前記内
部回路素子に供給される電源がオフした場合を考えると
、何れの場合もl0C4のデータ転送動作は全く不可能
になるという欠点があった。In addition, in response to the above REQIOI, the data channel device 1
The transfer request acceptance signal line (hereinafter abbreviated as ACK) 102 that is issued by l0c2. ACK 202 and ACK 302 in order via the internal circuit elements of l0C3,
Finally, it is transmitted to l0C4. Note that 110 is a data and address bus. Now, if we consider the case where the power supply to the internal circuit elements of IOC2 or IOC3 is turned off, there is a drawback that the data transfer operation of IOC4 becomes completely impossible in either case.
(発明の目的〕
本発明は、電源断となったIOCがそれ以外のIOCの
データ転送動作に悪影響を与えないようにして、上記欠
点を除去したデータ転送システムのバス切換装置を提供
することを目的とする。(Objective of the Invention) An object of the present invention is to provide a bus switching device for a data transfer system that eliminates the above disadvantages by preventing an IOC whose power is cut off from having an adverse effect on the data transfer operations of other IOCs. purpose.
そのだめの本発明の構成は、データチャネル装置と複数
の入出力装置とを一組の入出力バスで接続し、入出力制
御装置から出力される転送要求信号線および該転送要求
信号線の応答として前記データチャネル装置から出力さ
れる転送要求受付信号線が、該入出力制御装置と該デー
タチャネル装置の間に接続された複数の入出力制御装置
内部の回路素子を経由してデータ転送を行なうデータ転
送システムにおいて、各入出力制御装置と前記転送要求
信号線および前記転送要求受付信号線との間にバス切換
装置を具備し、該入出力制御装置内部の回路素子に供給
される電源が切断状態時に前記転送要求信号線および前
記転送要求受付信号線を該入出力制御装置を経由せずに
前記バス切換装置内部でバイパスさせるよう構成したも
のである。To avoid this, the configuration of the present invention connects a data channel device and a plurality of input/output devices with a set of input/output buses, and a transfer request signal line output from the input/output control device and a response of the transfer request signal line. A transfer request acceptance signal line outputted from the data channel device as a transfer request reception signal line transfers data via circuit elements inside a plurality of input/output control devices connected between the input/output control device and the data channel device. In the data transfer system, a bus switching device is provided between each input/output control device and the transfer request signal line and the transfer request acceptance signal line, and power supply to circuit elements inside the input/output control device is cut off. In this state, the transfer request signal line and the transfer request acceptance signal line are bypassed within the bus switching device without passing through the input/output control device.
〔1発明の実施例〕 次に、その一実施例を図面と共に説明する。[1 Example of the invention] Next, one embodiment will be described with reference to the drawings.
第2図は本発明になるデータ転送システムのバス切換装
置の一実施例を適用した該データ転送システムの回路構
成図、第3図は上記バス切換装置の回路構成図であり、
各図中、第1図と同一部分には同一符号を付してその説
明を省略する。FIG. 2 is a circuit configuration diagram of a data transfer system to which an embodiment of the bus switching device of the data transfer system according to the present invention is applied, and FIG. 3 is a circuit configuration diagram of the bus switching device.
In each figure, the same parts as in FIG. 1 are given the same reference numerals, and their explanations will be omitted.
図中、転送要求信号線(REQ) 101 、転送要求
受付信号線(ACK) 102と、REQ 201 、
ACK202との間に入出力制御装置(IOC)2の
バス切換装置10を設け、該切換装置10とl0C2と
をREQ 103 、105及びACK 104 、1
06によシ接続する。In the figure, a transfer request signal line (REQ) 101, a transfer request acceptance signal line (ACK) 102, REQ 201,
A bus switching device 10 of an input/output control device (IOC) 2 is provided between the ACK 202 and the switching device 10 and the l0C2.
Connect to 06.
また同様にREQ 201 、 ACK 202とRE
Q301 、 ACK 302との間に他のバス切換装
置11を設け、該切換装置11とl0C3とをREQ2
03 、205およびACK 204 、206によシ
接続する。Similarly, REQ 201, ACK 202 and RE
Another bus switching device 11 is provided between Q301 and ACK 302, and the switching device 11 and l0C3 are connected to REQ2.
03, 205 and ACK 204, 206.
以下l0C4以降のIOCについても同様に接続される
が図では省略しである。The IOCs after 10C4 are also connected in the same way, but are omitted from the diagram.
ここで前記バス切換装置10.11および図では省略し
であるl0C4以降のIOCに接続されるバス切換装置
はすべて同一である。Here, the bus switching devices 10.11 and the bus switching devices connected to the IOCs after 10C4, which are omitted in the figure, are all the same.
第3図中、バス切換装置10は、l0C2の内部回路素
子150に供給される電源Pで制御されるリレーのコイ
ルRLと、該コイルRLで制御されるリレー回路A、お
よびBとから構成される。In FIG. 3, the bus switching device 10 is composed of a relay coil RL controlled by a power supply P supplied to an internal circuit element 150 of the l0C2, and relay circuits A and B controlled by the coil RL. Ru.
電源Pがオンの状態の場合はリレーのコイルRLは励磁
されリレー回路Aはal側に倒れ、REQ201はRE
Q 105 、 IOC2(7)内部回路素子150を
経てREQ 103 、 REQ 101としてデータ
チャネル装置lに伝達する。When the power supply P is on, the relay coil RL is energized, the relay circuit A falls to the al side, and REQ201 becomes RE
Q 105 and IOC2 (7) are transmitted to the data channel device l via the internal circuit element 150 as REQ 103 and REQ 101.
同時にリレー回路Bはbl側に倒れ、ACK102はA
CK 104 、 IOC2の内部回路素子151を経
テACK 106 、 ACK 202として後続IO
Cに伝達される。At the same time, relay circuit B falls to the bl side, and ACK102 becomes A.
CK 104 , the internal circuit element 151 of IOC2 is transferred to subsequent IO as ACK 106 , ACK 202
It is transmitted to C.
前記電源Pがオフの状態の場合はリレーのコイルRLは
消磁されリレー回路Aはa2側に倒れ、リレー回路Bは
b2側に倒れることにより、REQ 201 、 AC
K 102はl0C2の内部回路素子150を経ること
なく、それぞれ直接REQ 101 。When the power supply P is off, the coil RL of the relay is demagnetized, the relay circuit A falls to the a2 side, and the relay circuit B falls to the b2 side, so that REQ 201, AC
K 102 is directly REQ 101 without passing through the internal circuit element 150 of l0C2.
ACK202に接続される。Connected to ACK202.
これKよれば、バス切換装置10,11.・・・を設け
ているため、所定のIOCの電源が断となっても、その
パス□切換装置の機能によfi REQ 、 ACKが
夫々電源断のIOCの内部回路を経ることなく、これを
飛び越して次のIOCにデータ転送を行なえ、従来例の
如くデータ転送が不可能になるという不都合を生じない
。According to K, bus switching devices 10, 11 . ... is provided, so even if the power to a given IOC is cut off, the function of the path switching device will allow fi REQ and ACK to be processed without going through the internal circuits of the IOC whose power was cut off. Data can be skipped and transferred to the next IOC, and the inconvenience of being unable to transfer data unlike the conventional example does not occur.
(発明の効果〕
以上説明した如く、本発明になるデータ転送システムの
パス切換装置によれば、入出力バスに接続された入出力
制御装置に入出力パスをバイパスする機能を有するパス
切換装置を設けることにより、電源断となった入出力制
御装置以外の入出力制御装置が正常にデータ転送を行え
る効果があゐ。(Effects of the Invention) As explained above, according to the path switching device of the data transfer system according to the present invention, the path switching device has the function of bypassing the input/output path of the input/output control device connected to the input/output bus. By providing this, the effect is that input/output control devices other than the input/output control device whose power has been cut off can normally transfer data.
第1図は従来のデータ転送システムの回路構成図、第2
図は本発明になるデータ転送システムのパス切換装置の
一実施例を適用した該データ転送システムの回路構成図
、第3図は上記パス切換装置の回路構成図である。
1°°゛データチヤネル装置
2.3.4・・・入出力制御装置(IOC)10.11
・・・パス切換装置
110・・・データ及びアドレスバス
150.151・・・入出力制御装置の内部回路素子R
L・・・リレーのコイル
A、B・・・リレー回路Figure 1 is a circuit diagram of a conventional data transfer system;
The figure is a circuit configuration diagram of a data transfer system to which an embodiment of the path switching device of the data transfer system according to the present invention is applied, and FIG. 3 is a circuit configuration diagram of the path switching device. 1°°゛Data channel device 2.3.4... Input/output control device (IOC) 10.11
...Path switching device 110...Data and address bus 150.151...Internal circuit element R of input/output control device
L...Relay coil A, B...Relay circuit
Claims (1)
入出力バスで接続し、入出力制御装置から出力される転
送要求信号線および該転送要求信号線の応答として前記
データチャネル装置から出力される転送要求受付信号線
が該入出力制御装置と該データチャネル装置の間に接続
された複数の入出力制御装置内部の回路素子を経由して
データ転送を行なうデータ転送システムにおいて、各入
出力制御装置と前記転送要求信号線および前記転送要求
受付信号線との間にバス切換装置を具備し、該入出力制
御装置内部の回路素子に供給される電源が切断状態時に
前記転送要求信号線および前記転送要求受付信号線を該
入出力制御装置を経由せずに前記バス切換装置内部でバ
イパスさせるよう構成したことを特徴とするデータ転送
システムのバス切換装置。A data channel device and a plurality of input/output control devices are connected by a set of input/output buses, and a transfer request signal line output from the input/output control device and a transfer request signal line output from the data channel device in response to the transfer request signal line are connected. In a data transfer system in which a transfer request reception signal line transfers data via circuit elements inside a plurality of input/output control devices connected between the input/output control device and the data channel device, each input/output control A bus switching device is provided between the device and the transfer request signal line and the transfer request acceptance signal line, and the bus switching device is provided between the transfer request signal line and the transfer request acceptance signal line when the power supply supplied to the circuit elements inside the input/output control device is in a disconnected state. A bus switching device for a data transfer system, characterized in that the transfer request reception signal line is configured to be bypassed within the bus switching device without passing through the input/output control device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13651284A JPS6116355A (en) | 1984-07-03 | 1984-07-03 | Bus switching device of data transfer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13651284A JPS6116355A (en) | 1984-07-03 | 1984-07-03 | Bus switching device of data transfer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6116355A true JPS6116355A (en) | 1986-01-24 |
Family
ID=15176902
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13651284A Pending JPS6116355A (en) | 1984-07-03 | 1984-07-03 | Bus switching device of data transfer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6116355A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017068796A (en) * | 2015-10-02 | 2017-04-06 | 株式会社ジェイテクト | Programmable controller |
-
1984
- 1984-07-03 JP JP13651284A patent/JPS6116355A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017068796A (en) * | 2015-10-02 | 2017-04-06 | 株式会社ジェイテクト | Programmable controller |
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