JPS61161823A - Input circuit - Google Patents

Abstract

PURPOSE:To obtain an excellent histeresis characteristic by providing a series circuit comprising a switch and a D-FET between an output terminal of a D-FET load inverter and a common and using an inverted output signal of the said inverter so as to turn on/off the said switch. CONSTITUTION:An output terminal N1 of an inverter I1 is connected to an input gate of an inverter I2 of the 2nd stage and connected to a series circuit comprising transistors (TRs) Q3, Q4. The series circuit is turned on/off by a signal at an output terminal N2 of the inverter I2. When the level of the output terminal N2 is logical L, the TRQ3 is turned off. When the level of an input terminal A goes to logical H, the output terminal N1 goes to logical L, a TRQ6 is turned off and the output terminal N2 goes to logical H. As a result, the TRQ3 is turned on and a TRQ4 attains connection to common. As a result, a histeresis characteristic is provided. The TRQ4 acts like adjusting the gm ratio of the inverter I1 against the characteristic fluctuation of the TRQ1.

Description

[Detailed Description of the Invention] [Industrial Application Field] To prevent the operating range of input information from narrowing due to the current flowing into the reference potential when a large output circuit or address inverter circuit is activated. The present invention relates to an input circuit having a hysteresis characteristic.

[Conventional technology]

In general, in high-speed semiconductor memory, the transistor size is increased due to the need to transfer information at high speed, so the d i /d t of each inverter is large, and even in large-capacity semiconductor memory, inverters with heavy load capacity are required. di/d due to the need to increase the transistor size
As t becomes larger, from the formula Δv=L・di/dt, the voltage below the reference potential is called GND. ) noise is likely to occur.

In particular, the output circuit transistor has a large capacity, and during ana when the output information is switched from 11'' to 10'', a current of several tens of mA flows into GND, causing large noise. Further, in the address inverter circuit, when all addresses are switched at the same time, noise is generated at 9GND, where d i/d t is large, and the allowable operating range of input information becomes narrow.

As a countermeasure to this problem, an input circuit having a hysteresis characteristic that is insensitive to noise is usually used.

Figure 2 shows a simple E/D inverter circuit, consisting of a depletion type transistor Ql and an enhancement type transistor Q2.
Threshold 1- in Ogm ratio (gm of Ql/gm of Qz)
When the gm ratio is large, the threshold voltage is low, so the response time for the rising edge of the input waveform is fast, but the rising time for the falling edge is slow, and when the gm ratio is small. Since the threshold voltage is high, the response time for the falling edge of the input waveform is fast, but the response time for the rising edge is slow. Therefore, this gm ratio is restricted by operating speed and power supply margin. Here, if you want to speed up the response time of the input waveform, it is necessary to take a large gm ratio, which lowers the thread 1 - lumi pressure and increases noise in devices with large GND inductance, so the low-level input voltage Vtb standard There were cases in which malfunctions occurred due to unsatisfactory conditions.

FIG. 3 is a circuit diagram showing an example of a conventional input circuit having a hysteresis characteristic. In Fig. 3, the load transistor Q is a depletion type transistor Q.
1 and an enhancement type transistor Q2 which is a driving transistor.
An enhancement type transistor Q is connected to the output terminal Nl of
It is connected to the output terminal N2 of the anti-phase E/D inverter 2, which is constituted by the double-channel transistor Qs of No. 3 and the enhancement transistor Q6, thereby forming an input circuit having hysteresis characteristics.

To explain the operation of this circuit, when the input terminal level changes from "0" to 11m, when the input terminal terminal level is below the threshold voltage of transistor Q2, transistor Q3 turns off. The output terminal N1 of the E/D inverter 11 is at the "1" level.

When the level of the input terminal A rises and begins to exceed the threshold voltage of the transistor Qz, the level of the output terminal Nl of the E/D inverter E1 begins to fall, and the level of the input terminal A further increases.
becomes high, and the output terminal N1 of the E/D inverter It becomes high.
level exceeds the threshold of the reverse phase E/D inverter It.
When the voltage drops below the voltage level, the output terminal N2 becomes ``1'', transistor Q3 is turned on, and the level of the output terminal N1 of the E/D inverter I1 is rapidly lowered to completely 0''.

Next, when the level of input terminal A changes from II, 1" to 10", the operation will be such that the level of input terminal 1,000 is sufficiently '1'.
“When the level is at the output terminal N of the E/D imperta
1 is 10", and even if the level of the input terminal A starts to decrease, when it is below the threshold voltage of the E/D inverter 2, the transistor Q3 is turned on.
Meanwhile, the level of the output terminal Ns of the E/D inverter 1 remains at wO''.The level of the input terminal A further decreases, and the level of the output terminal N1 of the E/D inverter 1 rises. When the threshold voltage of the E/D insulator 2 is exceeded and the level of N2 becomes '0', the transistor Q3 is turned off and the output terminal N of the E/D insulator 1 is turned off.
1 suddenly becomes '1'.

This characteristic is shown in FIG. 4, which shows that the hysteresis loose area is a dead band and is correspondingly resistant to noise.

Further, it is desirable that the transistor Q3 shown in FIG. 3 has such a capability that the gm ratio of the transistor Q1 and the transistor Q2 of the E/D inverter 1 does not differ greatly.

[Problem that the invention seeks to solve]

The problem with the circuit in Figure i is that the transistors Qz and Q
If the capacity becomes larger than necessary due to variations in the characteristics of a, as shown in Figure 5, the low level side of the hysteresis loop becomes too low, and the low level input voltage VI
This may not meet the L standard and may cause malfunction.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks and to improve the enhancement type transistor Q2. To provide an input circuit having a hysteresis characteristic in which the allowable range of input information does not change easily when the QsO capability becomes larger than necessary or when the characteristics of a depleted silane transistor Ql change.

[Means for solving problems]

In the input circuit of the present invention, the drain of the third enhancement type transistor is connected to the output terminal of the 10th E/D inverter which is composed of the first transistor of the depletion layer type and the @2 transistor of the enhancement type. The source of the third transistor is connected to the drain of the fourth depressing transistor whose gate and source are connected to a reference potential, and the gate is
The 20th E has the same configuration as the D inverter and operates in opposite phase.
It is connected to the output end of the /D inverter and has hysteresis characteristics.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In Fig. 1, the difference from the conventional circuit shown in Fig. 3 is that the source of transistor Q3, which is a feedback circuit, is connected to the GND ground, and the drain of transistor Q4, which is a deep drain type, is connected to the gate of transistor Q4. The source is G
This means that it is grounded to ND.

According to such a configuration, even if the capabilities of the transistors Qz and Qs become larger than necessary due to variations, the transistor Q3 is suppressed by the transistor Q4, so the hysteresis shown in FIG. 5 can be avoided. It doesn't become a loop. Furthermore, the transistor Q4 has the function of adjusting the E/D inverter IfOgm ratio even when the characteristics of the transistor Q1 vary, especially when the input information is "'O".
It is possible to provide an input circuit that has hysteresis characteristics, a wide noise margin, and a tolerance range that does not easily change when .・〔
[Effects of the Invention] As described in detail above, according to the present invention, by the above-mentioned means, an input circuit having a hysteresis characteristic in which the allowable range of input information does not easily change regardless of manufacturing variations in the ability of the constituent transistors can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is an I/
Figure 3 is a circuit diagram showing an example of a D-inverter, and Figure 4 is a circuit diagram showing an example of a conventional input circuit. FIG. 5 is a diagram showing its operating characteristics. A...Input terminal, GND...Reference potential, 11. Is..., E/D inverter, N
s, Nz...Output end, Ql. Qa, Qs...Vipure rough type transistor, Qz, Qx, Qs...Enhancement type transistor, vCC...Power supply.

Claims (1)

[Claims] The drain of a third enhancement-type transistor is connected to the output terminal of a first E/D inverter including a first depletion-type transistor and a second enhancement-type transistor, and the third transistor The source of the E/D inverter is connected to the drain of a depletion type fourth transistor whose gate and source are connected to a reference potential, and the gate of the second E/D inverter has the same configuration as the first E/D inverter and operates in opposite phase. An input circuit characterized by being connected to the output end of a D-inverter and having hysteresis characteristics.