JPS61161556A - Information processor - Google Patents

Abstract

PURPOSE:To investigate easily a program bug hard to be resolved by setting a debugging interrupt to stop an operating part if an instruction execution address does not coincide with an address group set from the external as the result of comparison. CONSTITUTION:In the program debugging mode, contents of an operand address register 11 which instructs execution and contents of a designated address register 12 where an operand address designated preliminarily from the external is stored are compared with each other by a comparing circuit 13. If both operand addresses coincide with each other, debugging interrupt is reported to a service supporting device interface part 14. The service supporting device interface part 14 reports it to a service supporting device 30. A comparing circuit 32 of the service supporting device 30 compares the execution address from an interface control part 31 with an instruction address group from an input device 40, and debugging interrupt is set to stop the operating part if the execution address does not coincide with any instruction address.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus equipped with a function for debugging a program for a logical device.・ (Conventional technology) In general, in information processing equipment, the proportion of software in the information processing field tends to increase, and improving program reliability and ensuring quality have become even more important issues. There is.

The program debug function provided in conventional information processing is achieved by interrupting a specific address immediately before execution or immediately before a specific address is stored.

(Problem to be solved by the invention) However, some bugs included in the program may cause data to be destroyed, resulting in a program interrupt occurring unexpectedly. . In such a case, the program bug can be investigated to a certain extent by using the program bug function provided by the prior art. However, when the value of data destruction varies, it takes a lot of time to investigate program bugs, resulting in very low efficiency.

An object of the present invention is to set all the ninth instruction addresses for writing data in the data destruction area, and to bring the operation unit into a halt state for writing data from instruction addresses other than those set. The object of the present invention is to provide an information processing device configured to solve the above problems and improve the efficiency of program debugging.

(Means for Solving the Problems) An information processing device according to the present invention includes a central processing unit and a service support device.

The central processing unit has an operand address register for holding an operand address, a specified address register for storing an externally specified address, and a register for comparing the contents of the operand address register with the contents of the specified address register. The first comparison circuit includes four comparison circuits, and the output of the first comparison circuit can be sent to the service support device.

The service support device includes a group of debugging registers to which arbitrary values can be set from the outside, and a register for comparing the output sent from the first comparison circuit of the central processing unit with the output of the aforementioned group of debugging registers. A second comparison circuit is provided, and when the output of the second comparison circuit indicates a mismatch, execution calculations can be stopped as a debugging interrupt.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. The information processing device shown in FIG. 1 includes a central processing unit 10, a service support device (SVP) ao, and an input device 40. The central processing unit 10 includes an operand address register 11, a specified address register 12 for storing an address specified from the outside,
It consists of a first comparison circuit 13 for comparing the contents of both registers 11 and 12, and a service support device interface section 14. The signal line 15 is a clock stop signal line for instructing the arithmetic unit (not shown) to stop the clock signal when the comparison results match, and the signal line 16 is a debug interrupt signal line for instructing a debug interrupt. The signal line 17 is a clock start signal line for starting the clock of the calculation section, and the signal line 20 is an interface signal line for connecting the service support device interface section 14 to the service support device 30. The service support device 30 includes an interface control section 31,
It consists of a second comparison circuit 32 and a group of debugging registers 33 for storing externally specified addresses.

The second comparison circuit 32 compares the output of the interface control section 31 and the contents of the debugging register group 33.

Next, the operation of the above embodiment will be explained in detail with reference to FIG.

In the program debug mode, the comparator circuit 13 compares the contents of the operand address register 11 for instructing execution with the contents of the specified address register 12 for storing a t-operand address designated in advance from the outside.

When both operand addresses match, the clock stop signal line 15f is turned on and the debug interrupt signal line 16 is turned on to instruct the clock signal of the arithmetic section (not shown) to be stopped, so that the service support device interface section 14 of the debug interrupt. Upon receiving the debug interrupt, the service support device interface section 14 notifies the interface control 11s31 of the service support device 30 via the interface signal line 20 of the above. In the service support device 30, the comparison circuit 32 compares the next execution instruction address sent from the interface control unit 31 with the contents of the debugging register group 33, which stores a group of instruction addresses that have been previously supplied from the input device 40. do. As a result of the comparison, if there is a match between the two, the clock start signal line 17 is turned on in order to start the clock of the arithmetic unit via the interface signal line 20. As a result of the comparison, if there is no match, a debug interrupt is generated and the arithmetic unit is stopped, allowing efficient debugging.

(Effects of the Invention) As described above, the present invention is configured such that if the comparison result between the instruction execution address and a group of addresses set from the outside does not match, a debug interrupt is issued and the operation unit is stopped. This has the effect of making it easier to investigate program bugs, which have been difficult to understand.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. 10...Central processing unit 30...Service support device 40...Input device 11, input device, operand address register 12...Specification address register 13.32...Comparison circuit 14...Service support device interface Part 31・
・1 interface control unit 33...Debug register group 15 to 17.20...Signal line

Claims (1)

[Claims] an operand address register for holding an operand address, a specified address register for storing an externally specified address, and a first comparison for comparing the contents of the operand address register with the contents of the specified address register. said first comprising a circuit;
a central processing unit that can send out the output of the first comparison circuit in the central processing unit, a group of debugging registers that can set arbitrary values from the outside, and an output that is sent out from the first comparison circuit in the central processing unit. a second comparison circuit for comparing the output of the debugging register group;
An information processing device comprising: a service support device capable of stopping execution of calculations as a debug interrupt when the outputs of the second comparison circuits do not match.