JPS61161052A - Line monitor device - Google Patents

Abstract

PURPOSE:To make easy the calculation of transfer efficiency, etc., by detecting a special pattern in transfer data, and counting and displaying the number of the patterns. CONSTITUTION:Each time the effective frame is inputted a special pattern is detected, 1 is outputted from a condition changing circuit 25, this is latched at a latch circuit and supplied to 7 segment display 27. The 7 segment display 27 displays the number in accordance with the number of the input pulses. Namely, since the number of 1 frame of the transfer data is displayed, an observer can easily calculate a transfer efficiency, etc., of the information transferred between the devices.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a line monitoring device that monitors data transferred on a synchronous interface connecting two devices, and in particular, when the transferred data is an HDLC or 5DLC type frame. The present invention relates to a circuit for counting and displaying the number of transferred I frames containing valid information when the present invention is configured as follows.

Summary of the Invention The present invention is a line monitoring device that monitors data transferred on an interface connecting two devices, and detects a specific pattern in the transferred data to detect frames containing valid information. It is designed to count and display the number of pieces.

Prior Art Conventionally, a line monitor device for monitoring transfer data having an HDLC or 5DLC frame structure as shown in FIG. 4 uses an 8-bit flag pattern (synchronization pattern).
The device is composed of a circuit for detecting the data, a memory for accumulating data on the interface, a display circuit for displaying the contents of the memory, a display control section, and the like. The data transferred on the interface is once stored in memory, and then its contents are displayed on one display circuit.

Although the conventional device described above is useful for knowing the details of the transferred data, it has the disadvantage that the circuit size is large and it is expensive. In addition, in many cases, the line monitor simply needs to know the number of frames (I frames) containing valid information that are transferred through the interface L, without knowing the contents of the transferred data. Conventionally, the data on the display circuit had to be analyzed and the number of frames had to be counted, which was time-consuming and extremely inconvenient.

Problems to be Solved by the Invention The present invention solves the above-mentioned conventional drawbacks, and detects a specific pattern in transferred data and counts and displays the number, thereby detecting the number of effective I frames with a simple device. It is intended to display.

Structure of the Invention The line monitoring device of the present invention includes: a pattern detection circuit that detects a specific bit pattern indicating that data transmitted on a data line of an interface cable connecting two devices includes valid information; The present invention is characterized by comprising a display circuit that counts and displays the number of pulses output by the detection circuit.

Embodiments of the invention Next, the invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

That is, the connectors 11 and 16 are connected by a cable 12 and branched to an information frame counting circuit 14 by a single branch cable 13. The connectors 11 and 16 are inserted and connected in series to an interface cable connecting two devices.The zero branch cable 13 includes at least a data line and a clock line. Information frame counting circuit 1
4 monitors the signal pattern of the data line H, and every time a specific bit pattern is detected, it outputs a pulse and supplies it to the display circuit 15, and the display circuit 15 counts the output pulses of the information frame counting circuit 14. and display.

FIG. 2 is a block diagram showing a detailed configuration example of the information frame counting circuit I4. That is, a signal obtained by inverting the synchronous clock 22 twice by the inverting circuits 23 and 29 is input to the clock terminal GK, and the signal D is output at the rising edge of the synchronous clock 22.
A latch circuit 24 latches the human input data 21 input to the terminal, and the Q output of the latch circuit 24 is input to the input terminal A5, and the output is 0 depending on the state of the input terminals A to A4 and the input of the input terminal A. and a state transition circuit 25 that transitions between states of ° to 05.

A latch circuit 26 that latches the output 0° to o5 of the state transition circuit 25 according to the rising edge of a signal obtained by inverting the synchronous clock 22 by an inverting circuit 23, and the Q5 output of the latch circuit 26 are input, and the number is counted and displayed. It consists of a 7-segment display 27.

Output terminals Q and ~Q4 of the latch circuit 26 are connected to input terminals A and ~A4 of the state transition circuit 25, respectively,
The reset terminal of the seven segment display 27 is grounded through a switch 28. Closing switch 28 resets seven segment display 27.

Next, the operation of this embodiment will be explained. Input data 2
1 is latched in the latch circuit 24 at every rise of the synchronous clock 22, and the Q output of the latch circuit 24 is output to the state transition circuit 2.
It is input to the input terminal A5 of No. 5. The state transition circuit 25 is 5
Depending on the states of input terminals A0 to A4 and the input to input terminal A5 at that time, the states of outputs 0° to 05 are changed as shown in FIG. The input terminal is supplied to ~D5, and the latch circuit 2
B is the output O0~0. The outputs are each latched and outputted from the Q6 to Q5 outputs.

FIG. 3 is a diagram showing the state transition of the state transition circuit 25.
The numbers (or symbols) written inside the O mark in the figure represent the logical states of 0 to A4 to the input terminal of the state transition circuit 25 in hexadecimal notation.

It also shows that when the left side signal written above each arrow is input to the input terminal A5, the right side signal is outputted to the output 05, and the state changes according to the arrow. In other words.

Outputs the hexadecimal number shown within the 0 mark at the end of the arrow 0° ~ 04
This is latched by the latch circuit 26 and becomes the next input state of the input terminals A, ~A4 of the state transition circuit 25.

For example, HDLC type or 5DLC as shown in Figure 4.
Let us consider the case where the data of the frame structure of the type is input sequentially from ■ to . In the same figure, the bit pattern from ■ to ■ is “”0111111011
0000000” or “0111111010000
o o o o” is an I that contains valid information.
This is a necessary and sufficient condition for it to be a frame.

Now, the initial state of the input terminals A0 to A4 of the state transition circuit 25 is 00, and when data "O" is input to the input terminal A5, the state changes to 01, and when "1" is input next, the state changes to 02. Transition. Similarly, the state of the state transition circuit 25 sequentially changes. Therefore, the input data is “”011111L0
110000000” or “01111110100
000000", when the last data "0°" is input, "1" is output from 05 of the state transition circuit 25, and the state returns to the initial state. When the pattern is other than the above, the state changes depending on the state at that time or returns to the initial state. In these cases, "0" is output at 05. That is, in this embodiment, the state transition circuit 25 and the latch circuit 26 constitute a specific pattern detection circuit. Note that after the above pattern is recognized, the initial state O
Return to step O and prepare for the next pattern detection.

Therefore, in this embodiment, each time a valid frame is input, the above-mentioned specific pattern is detected and the state transition circuit 25 outputs "l", which is latched by the latch circuit 2B and displayed on the 7-segment display 27. Supplied. 7 segment display 27.

Displays the number according to the number of input pulses. That is, the number of Eframes of the transferred data is displayed. Therefore, an observer can easily calculate the transfer efficiency of information transferred between devices.

Effects of the Invention As described above, the present invention is configured to detect a specific pattern of data transferred between devices and display the number of data transferred, so that transferred data can be easily monitored with a simple circuit. , r frames can be counted. This is convenient for calculating the transfer efficiency of effective information.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a detailed configuration example of the information frame counting circuit of the above embodiment, and FIG. 3 is a diagram showing state transition of the state transition circuit. , FIG. 4 is a diagram showing the structure of an I frame containing valid information. In the figure, 11: connector, 12: cable, 13:
Branch cable, 14: Information frame counting circuit, 15: Display circuit, 21: Input data, 22: Synchronous clock, 23
: inversion circuit, 24: latch circuit, 25: state transition circuit,
26: Latch circuit, 27: 7 segment display.

Claims (1)

[Claims] a pattern detection circuit that detects a specific bit pattern indicating that data transmitted on a data line of an interface cable connecting two devices contains valid information;
A line monitoring device comprising: a display circuit that counts and displays the number of pulses output by the pattern detection circuit.