JPS61160156A - Fault detecting system of processor - Google Patents

Abstract

PURPOSE:To execute concentrically diagnosis operation at the time of low load by making a processor read out the contents of a function register when a process control mechanism detects that all processes are in the waiting state and processing and collating test data on the basis of the read contents. CONSTITUTION:A memory 3 stores the test data for detecting a fault of the processor 1, a program to be executed by the processor 1, process control information related to the states of processes constituting the program, the order of execution, etc., an OS or the like. The process is started by an interruption due to a keying request from a console unit 4, data transfer request or the like from a magnetic disk device 5 or a communication control device 6 or the generation of a service request event such as a request from another process. However, the process is kept at the waiting status until the events required for the processing of the service request are completely prepared. When the process control mechanism detects that all the processes are in the waiting status, the processor 1 reads out the contents of the function register 2 to process and collate the test data on the basis of the contents.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application in CTl1 Field of the Invention The present invention relates to a processor fault detection method that detects a fault in the processor by appropriately operating the internal functions of the processor.

(Prior Art) Conventionally, failure detection methods for this type of processor include a microprocessor, a memory for storing a program running on the microprocessor, a monitoring timer for time monitoring, and a microprocessor diagnostic system. It is equipped with functions and I/registers that give internal circuit operation commands,
By preparing data corresponding to the contents of this function register in memory, having the microprocessor read the contents of the function register by interrupting the watchdog timer, and processing and collating the data prepared in memory according to this contents. A system that detects failures in microprocessors is known (4!
9455).

(Problems to be Solved by the Invention) In such a conventional system, the first problem is that since the monitoring tie i is required, the amount of hardware increases accordingly. In addition, regardless of the processor load status, if there is an interrupt from the monitoring timer, diagnostic operations using internal functions will be executed immediately.
The second problem is that it causes a decrease in processing speed.

In systems that perform processing where prompt response is important, such as e:, IJ real-time control, process control, etc., if normal processing is interrupted unnecessarily by an interrupt, problems may occur in normal processing. .

Therefore, an object of the present invention is to perform diagnostic operations in a concentrated manner when the load on the processor is low, so that normal processing is not hindered even in an information processing system where prompt response is important. An object of the present invention is to provide a processor failure detection method that enables reduction of hardware amount.

(Means for Solving the Problem) To round it off, the method of the present invention is activated by the occurrence of a service request event, but remains in a standby state until the events necessary to process the request occur. A processor on which a program that operates in units of processes runs; a memory for storing at least the program, test data, and process management information; a process monitoring mechanism that monitors the entire state of the process based on the process management information; and a processor for diagnosing the processor. When the process management mechanism detects that all processes are in a standby state, it makes the processor read the contents of the function register and processes the test data based on the contents. This feature is characterized in that the processor failure detection operation is performed by comparing the information.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, in this embodiment, a processor 1, a function register 2, a memory 3, a console 4, a magnetic disk device 5, and a communication control device 6 are interconnected via a bus 7t.

The memory 3 stores test data for detecting failures in the processor 1, a program executed by the processor 1, process management information regarding the status and execution order of processes constituting this program, O8, and the like. The process is activated by the occurrence of a service request event such as an interrupt due to a key-in request from the console 4, a data transfer request from the magnetic disk drive 51, or a data transfer request from the communication control device 6, or a request from another process.

However, it remains in a standby state until all the events necessary to process the service request occur. Examples of such events include, for example, in the case of a key-in request, when key-in of two data is required, the key-in of two data is completed, or when the processing result of another process is required, the processing is completed, etc. is possible. Further, even if all the events necessary for the above processing occur, if the processor 1 is executing another process, that process cannot be executed immediately and the processor 1 enters a ready-response state. In the end, the process has three states: running, waiting, and ready (in that order).

The process management information is information regarding the display of which of these three states each process is in, the execution order of the processes, etc., and is constantly monitored by the process management mechanism, which is a part of 08.

Figure 2 is a flowchart of the normal processing in this embodiment, and the third
Each figure shows a flowchart of interrupt processing.

The operation of this embodiment will be described below along these flowcharts.

First, when the power of the information processing system shown in Fig. 1 is turned on, the process management mechanism initializes the process management information (step ■ in Fig. 2), and by reading the process management information, performs the process as described above. Check whether there is a process in a ready state (step ■).

The immediate state is issued by an interrupt process as shown in FIG. That is, when a service request event such as a key-in request from the console 4 or a data transfer request from the magnetic disk device 52 or the communication control device 6 occurs, the process management mechanism starts the process by reading the process management information. After checking whether the conditions for processing the service request are satisfied, in other words, whether the events necessary for processing the service request as described above have been met, the process is put into a ready state. Such an interrupt may occur between any other steps except between step 2 and step 2 in FIG.

Readiness can also be created by other processes. That is, when the process executed in step (2) completes the process requested by another process, the process being executed notifies the process management mechanism of the completion of the process. Furthermore, when a process being executed requests processing to another process, it notifies the process management mechanism of the processing request. When one of these notifications is received, the process management information is used to check whether the necessary events have occurred to start the requesting process, and if it is found that the requesting process can be started, the requesting process is placed in a ready state. It is to make it.

If there is only one process in the ready state in step (■), the process management mechanism sets the process management information of that process, or if there are multiple processes, in the execution state according to the execution order determined based on the process management information (step (■)) , the processing of the process is executed (step ■). And on continuing to run this process.

For example, when an event occurs that requires waiting for the result of another unexecuted process or the occurrence of a new interrupt, the process is put into a standby state and the process returns to step (2).

Now, in step ■, there is no process in the ready state.
In other words, if all the processes are in the standby state, the process management mechanism causes the function register 2t-processor 1 to read (step 2).

The function register 2 is preloaded with data for diagnosing the processor 1t from the memory 3, and based on this data, the processor 1 appropriately selects and reads the test data stored in the memory 3 and performs the diagnosis. Execute (step ■).

The test data consists of input data and output data], and after processing the input data based on the contents of the function register 2, the processor 1 can perform self-diagnosis by comparing the processing results with the output data. There is. Since the contents of the function register 2 can be updated by the processor 1, it is also possible to execute a plurality of diagnoses in succession.

That is, when the diagnosis based on the predetermined contents of the function register 2 is completed, the process moves to step (2) and the processing flow shown in FIG. During this time, I'm going to get some fun.

By updating the recorder 2t, it becomes possible to diagnose the contents that are leaking each time.

If the results of such diagnosis are all normal, the process returns to step ■; however, if an abnormality is found, fault detection processing is performed (step ■), and an alarm is generated, such as by lighting a lamp on the console 4. Occur.

In addition, in this example, as shown in FIG.
Although the function register 2 is provided separately from the memory 3, this is for the convenience of explanation.A) It is more natural to implement the function register 2 in a predetermined area of the memory 3, and the present invention It should be noted that this also includes such embodiments.

(Effects) According to the present invention, as explained above, since the diagnostic operation is performed only when all processes are in the standby state, normal processing can be performed even in an information processing system where prompt response is important. Since there is no need for a monitoring timer, the amount of hardware can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining this embodiment. 1...Processor% 2...Function register, 3...Memory, 4...
・Operation console, 5...Magnetic disk device, 6...
...Communication control device, 7...Communication line, 8...
...Bus line.

Claims (1)

[Scope of Claims] At least a processor running a program that operates in units of processes that are activated upon the occurrence of a service request event but remain in a standby state until the events necessary to process the request occur; a memory for storing the program, test data, and process management information; a process monitoring mechanism for monitoring the state of the process based on the process management information; and a memory for setting internal circuit operation instructions for diagnosing the processor. and a function register, and when the process management mechanism detects that all the processes are in the standby state, it causes the processor to read the contents of the function register and processes and collates the test data based on the contents. A fault detection method for a processor, characterized in that a fault detection operation for the processor is performed by: