JPS61158226A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPS61158226A
JPS61158226A JP27981884A JP27981884A JPS61158226A JP S61158226 A JPS61158226 A JP S61158226A JP 27981884 A JP27981884 A JP 27981884A JP 27981884 A JP27981884 A JP 27981884A JP S61158226 A JPS61158226 A JP S61158226A
Authority
JP
Japan
Prior art keywords
speed
low
highway
pcm
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27981884A
Other languages
Japanese (ja)
Inventor
Keiji Yoshino
芳野 敬二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27981884A priority Critical patent/JPS61158226A/en
Publication of JPS61158226A publication Critical patent/JPS61158226A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To transmit and receive high-speed signals through an existing inexpensive low-speed transmission line by distributing the signals of a high-speed PCM highway to plural low-speed PCM highways and then multiplexing them again onto the high-speed PCM highway. CONSTITUTION:The signals on a highway of 6.3Mbps are distributed to four highways of 1.544Mbps by a distributing circuit (DMUX)22. The data stream of each highway is sent via a low-speed PCM highway 23, 27 and a transmission line of 1.544Mbps like a low-speed PCM communication circuit 25. The transmitted signal is received by a low-speed DTI26 and undergoes the multi-frame synchronizing through a buffer memory circuit which absorbs the differences caused among frame numbers of four transmission lines. Then the data stream is restored to the original signal stream of 6.3Mbps by a multiplexing circuit (MUX)28.

Description

【発明の詳細な説明】 (技術分野) 本発明は複数の電子交換機間の高速データの送受信方式
に関し、具体的には内部伝送速度が例えば6.3Mbp
s という高速の信号を扱う電子交換機間の送受信方式
に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a high-speed data transmission/reception system between a plurality of electronic exchanges, and specifically, the present invention relates to a system for transmitting and receiving high-speed data between a plurality of electronic exchanges, and specifically, the present invention relates to a method for transmitting and receiving high-speed data between a plurality of electronic exchanges, and specifically, the present invention relates to a method for transmitting and receiving high-speed data between a plurality of electronic exchanges.
This paper relates to a transmission/reception system between electronic exchanges that handles high-speed signals called s.

(従来技術) この種のデータ伝送に際しては、従来、送受速度が6.
3 Mbpa (マイクロビット/秒)であれば伝送路
も6.3 Mbpsあるいはそれ以上の高速の伝送路を
通して送受しなければならなかった。このような伝送路
は一般の通信網においてあまり普及しておらず、−次群
の1.544 Mbpsの伝送路が使用できればより経
済的に伝送路を構成することができる。
(Prior Art) Conventionally, in this type of data transmission, the sending/receiving speed is 6.
At 3 Mbpa (microbits per second), data had to be sent and received through a high-speed transmission line of 6.3 Mbps or higher. Such transmission lines are not very popular in general communication networks, and if a 1.544 Mbps transmission line in the -order group can be used, the transmission line can be constructed more economically.

(発明の目的) 本発明は上述の問題に鑑みてなされたものであって、6
.3 Mbpsの信号の伝送に際し、既存の1、544
 Mbpsの伝送路を使用して信号の送受を行うことの
できる経済的なデータ伝送方式を提供することを目的と
するものである。
(Object of the invention) The present invention has been made in view of the above-mentioned problems.
.. When transmitting 3 Mbps signals, the existing 1,544
The purpose of this invention is to provide an economical data transmission system that can send and receive signals using an Mbps transmission path.

(発明の構成) 本発明に係るデータ伝送方式は、複数の電子交換機間の
データ伝送において、高速のデータストリームをのせる
高速PCMハイウェイ、前記高速PCMハイウェイ上の
信号を複数の低速PCMノhイウエイに分配する手段、
および低速PCM信号を送信する手段をそれぞれ送信側
に設け、低速PCM信号を受信する手段、低速PCMノ
hイウエイからフレーム信号を検出し複数の低速PCM
ハイウエイの信号を、マルチフレーム同期をとった後、
高速のPCMハイウェイ上に多重化する手段、および高
速のPCMハイウェイをそれぞれ受信側に設けたもので
あって、例えば6.3 Mbps 、 96 CHのP
CMハイウェイのデータを4本の1.544 Mbps
のPCMハイウェイに各々24CH毎分配して送信し、
受信側でこれらを多重化し、もとの6.3M b p 
sのPCMハイウェイのデータとして受信するようにし
たものである。
(Structure of the Invention) In data transmission between a plurality of electronic exchanges, a data transmission system according to the present invention includes a high-speed PCM highway carrying a high-speed data stream, and a signal on the high-speed PCM highway being transferred to a plurality of low-speed PCM networks. means of distributing to;
and means for transmitting low-speed PCM signals are provided on the transmitting side, and means for receiving low-speed PCM signals is provided on the transmitting side, and means for detecting frame signals from the low-speed PCM way and transmitting multiple low-speed PCM signals.
After multi-frame synchronization of highway signals,
A means for multiplexing on a high-speed PCM highway and a high-speed PCM highway are provided on the receiving side, for example, 6.3 Mbps, 96 CH P.
4 CM Highway data at 1.544 Mbps
Each 24 channels are distributed and transmitted to the PCM highway of
These are multiplexed on the receiving side and the original 6.3Mbp
The data is received as PCM highway data of s.

(発明の好適な実施形態) 以下、本発明を、図面を参照しながら、実施例について
説明する。
(Preferred Embodiments of the Invention) Hereinafter, the present invention will be described with reference to the drawings.

第3図は従来方式による伝送システムを示したものであ
って、内部のビットレートに対応した速度の伝送路で伝
送する場合の例である。高速タイムスイッチである電子
交換機の時分割スイッチ10の出力は、96CH多重化
され、6.3MbpsのP CMハイウェイ11につな
がっている。このデータは高速のデータ転送インタフェ
ース装置(以下DTIと称する)12により6.31V
ll)psあるいはそれ以上高速の伝送路の高速PCM
通信回路13を経て受信高速DT114に伝送される。
FIG. 3 shows a conventional transmission system, and is an example of a case where data is transmitted through a transmission line whose speed corresponds to the internal bit rate. The output of the time division switch 10 of the electronic exchange, which is a high speed time switch, is multiplexed into 96 channels and connected to the PCM highway 11 of 6.3 Mbps. This data is converted to 6.31V by a high-speed data transfer interface device (hereinafter referred to as DTI) 12.
ll) High-speed PCM of ps or faster transmission line
The signal is transmitted to the receiving high-speed DT 114 via the communication circuit 13.

第1図は本発明の1実施例に係る伝送システムを示した
図であって、高速のデータを複数のデータ伝送路に分割
して伝送する場合を示したものである。また第2図は本
発明に係る受信部をより詳細に示したブロック図である
。第1図によれば6.3Mbpsのハイウェイ上の信号
は分配回路(DMUX)22により、4本の1.544
 Mbpsの信号に展開される。各々のデータストリー
ムは低速PCMハイウェイ23.27および低速PCM
通信回線25の如き1.、544 Mbpsの伝送路を
経て送られる。受信側においてはこnを多重化回路(M
UX)28 VCより、もとの6.3Mbpsに多重化
する。第2図を参照してこの受信側の部分を詳細に説明
すれば、1.544 Mbpsの伝送路からきた信号は
低速DTI 26により受信される。その出力はバッフ
ァメモリ回路(BUF) 3oに貯えられる。同一伝送
路の両端にあるDTI間で1フレ一ム同期はとるものの
、マルチフレーム構成の場合、4本の伝送路によりフレ
ーム番号のずれが生じる場合がある。これを吸収するだ
めの回路がバッファメモリ回路30である。壕だフレー
ム番号を識別する回路がフレーム番号検出回路(FD)
31である。このようにして4本の伝送路におけるマル
チフレームの同期をとった後、多重化回路(MUX)2
8に送り、6.3Mbpsの信号ストリームを復元する
FIG. 1 is a diagram showing a transmission system according to an embodiment of the present invention, in which high-speed data is divided into a plurality of data transmission paths and transmitted. Further, FIG. 2 is a block diagram showing the receiving section according to the present invention in more detail. According to FIG. 1, the signal on the highway of 6.3 Mbps is transmitted through four 1.544
It is developed into a Mbps signal. Each data stream is a low speed PCM highway 23.27 and a low speed PCM
1. such as communication line 25; , 544 Mbps. On the receiving side, a multiplexing circuit (M
UX) Multiplex to the original 6.3 Mbps from 28 VC. To explain the receiving side part in detail with reference to FIG. 2, the signal coming from the 1.544 Mbps transmission line is received by the low speed DTI 26. Its output is stored in a buffer memory circuit (BUF) 3o. Although one frame synchronization is achieved between DTIs at both ends of the same transmission path, in the case of a multi-frame configuration, a shift in frame number may occur due to the four transmission paths. The buffer memory circuit 30 is a circuit designed to absorb this. The circuit that identifies the frame number is the frame number detection circuit (FD).
It is 31. After synchronizing the multiframes on the four transmission lines in this way, the multiplexing circuit (MUX 2)
8 to recover the 6.3 Mbps signal stream.

(発明の効果) 本発明の伝送方式によれば、6.3M1)psの信号を
伝送するに当り、高価な6.3Mbpsの伝送路を新設
することなく既存1.544 Mbpsの伝送路を使用
して送受するため、経済的なデータ伝送が可能になる効
果がある。
(Effect of the invention) According to the transmission method of the present invention, when transmitting a 6.3 M1) ps signal, an existing 1.544 Mbps transmission line can be used without constructing a new expensive 6.3 Mbps transmission line. This has the effect of making economical data transmission possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の1実施例に係る伝送システムを示l−
た概略図、第2図は本発明に係る伝送システムの受信部
をより詳細に示したブロック図、第3図は従来方式によ
る伝送システムを示した概略図である。 10・・・電子交換機の時分割スイッチ、11.15・
・・高速P CIVIハイウェイ、12.14・・・高
速データ転送インタフェース装置、 13・・・高速PCM通信回路、 22・・・分配回路、 23.27・・・低速1) CMハイウェイ、24.2
6・・・低速データ転送インタフェース装置、 25・・・低速PCM通信回線、 28・・・多重化回路。 30・・・バッファメモリ回路、 31・・・フレーム番号検出回路。
FIG. 1 shows a transmission system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing in more detail the receiving section of the transmission system according to the present invention, and FIG. 3 is a schematic diagram showing a conventional transmission system. 10... Time division switch of electronic exchange, 11.15.
...High-speed PC CIVI Highway, 12.14... High-speed data transfer interface device, 13... High-speed PCM communication circuit, 22... Distribution circuit, 23.27... Low-speed 1) CM Highway, 24.2
6...Low speed data transfer interface device, 25...Low speed PCM communication line, 28... Multiplexing circuit. 30... Buffer memory circuit, 31... Frame number detection circuit.

Claims (1)

【特許請求の範囲】[Claims] 複数の電子交換機間のデータ伝送方式において、高速の
データストリームをのせる高速PCMハイウエイ、前記
高速PCMハイウエイ上の信号を複数の低速PCMハイ
ウエイに分配する手段、および低速PCM信号を送信す
る手段をそれぞれ送信側に設け、低速PCM信号を受信
する手段、低速PCMハイウエイからフレーム信号を検
出し複数の低速PCMハイウエイ上の信号を、マルチフ
レーム同期をとつた後、高速のPCMハイウエイ上に多
重化する手段、および高速のPCMハイウエイをそれぞ
れ受信側に設けたことを特徴とするデータ伝送方式。
In a data transmission system between a plurality of electronic exchanges, a high-speed PCM highway carrying a high-speed data stream, means for distributing a signal on the high-speed PCM highway to a plurality of low-speed PCM highways, and means for transmitting a low-speed PCM signal are each provided. A means provided on the transmitting side for receiving a low-speed PCM signal, a means for detecting a frame signal from a low-speed PCM highway, and multiplexing the signals on a plurality of low-speed PCM highways onto a high-speed PCM highway after multi-frame synchronization is achieved. , and a high-speed PCM highway are provided on the receiving side.
JP27981884A 1984-12-28 1984-12-28 Data transmission system Pending JPS61158226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27981884A JPS61158226A (en) 1984-12-28 1984-12-28 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27981884A JPS61158226A (en) 1984-12-28 1984-12-28 Data transmission system

Publications (1)

Publication Number Publication Date
JPS61158226A true JPS61158226A (en) 1986-07-17

Family

ID=17616339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27981884A Pending JPS61158226A (en) 1984-12-28 1984-12-28 Data transmission system

Country Status (1)

Country Link
JP (1) JPS61158226A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032193A (en) * 1997-03-20 2000-02-29 Niobrara Research And Development Corporation Computer system having virtual circuit address altered by local computer to switch to different physical data link to increase data transmission bandwidth

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032193A (en) * 1997-03-20 2000-02-29 Niobrara Research And Development Corporation Computer system having virtual circuit address altered by local computer to switch to different physical data link to increase data transmission bandwidth

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