JP2833938B2 - Digital line termination equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital line terminal.

[0002]

2. Description of the Related Art Conventionally, two types of interfaces in a digital line termination device, a Y interface and an I interface, are known, and have no alarm processing unit (part for performing ALM conversion (degeneration / pseudo transfer)). Therefore, it is not possible to multiplex signals of a plurality of lines of the Y interface system and connect them to the lines of the I interface system, or to divide signals of the I interface system and connect them to the plurality of lines of the Y interface system. Was.

[0003]

The above-mentioned conventional digital line termination device has a problem that a plurality of Y-interface lines and one I-interface line cannot mutually enter (mutual data communication).

[0004] The present invention has been made in view of the above-mentioned conventional circumstances, and accordingly, an object of the present invention is to provide a novel digital line terminating apparatus which can solve the above-mentioned problems inherent in the prior art. Is to do.

[0005]

In order to achieve the above object, a digital line terminal according to the present invention comprises an I-interface frame synchronizing unit, an I-interface frame pattern insertion unit, an I-interface alarm detection unit, and an I-interface alarm detecting unit. An interface alarm insertion unit, a clock transfer unit from the I interface clock to the device clock, a clock transfer unit from the device clock to the I interface clock, and data division for dividing the I interface data into each line of the Y interface system And a data multiplexing unit for multiplexing each line data of the Y interface system to an I interface system line, a Y interface system alarm detecting unit for one of the Y interface system lines, and a Y unit.
An interface alarm insertion unit, a clock transfer unit from the internal clock to the Y interface clock, a clock transfer unit from the Y interface clock to the internal clock, a Y interface frame synchronization unit, and Y
An interface frame pattern insertion unit, a Y interface alarm detection unit, a Y interface alarm insertion unit, and a clock transfer unit for switching from the internal clock to the Y interface clock of the other one of the Y interface lines. A clock transfer unit for converting the Y interface system clock to the internal clock, a Y interface system frame synchronization unit, and a Y interface system frame pattern insertion unit. ALM conversion (degeneration / pseudo-transfer) is performed in which the output of the alarm detection unit of each line is input to the alarm insertion unit for each Y interface line and the alarm insertion unit for the I interface system.

[0006]

Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Referring to FIG. 1, the frame synchronization unit 1
The interface-side line synchronizes the input data with the frame via the line 21, the I-interface alarm detection unit 2 classifies the I-interface alarm and the data via the line 22, and outputs the I-interface alarm to the line 23.
Is transferred to the alarm processing unit 60 via the
The clock is transferred to the in-device clock transfer unit 3 through the interface, and the phase is switched from the clock extracted from the I interface data to the in-device clock.

The data dividing unit 4 divides the data via the line 25 into one of the lines of the Y interface system, and the clock transfer unit 5 of one of the lines of the Y interface system transmits the data to the line 26. , The phase is switched from the internal clock to the clock of one of the lines of the Y interface system.

One alarm insertion unit 6 in each line of the Y interface system transfers data of one line in each line via a line 27, and transmits one data line in each line of the Y interface system via a line 28. The alarm of the line is transferred from the alarm processing unit 60, and the data is transferred to the data in each of the Y interface system lines.
The alarm of one line is included, and the frame pattern insertion unit 7 of one line in each Y interface system frame pattern inserts the frame pattern into the data of one line in each Y interface system line via the line 29. Then, the data and the Y interface alarm are sent out to one of the Y interface lines via the line 30.

Similarly, the clock transfer unit 8 of the other one of the Y interface lines is connected to the line 31.
The phase is changed from the clock in the device to the clock of one other line in each line of the Y interface system via the line, and the other one alarm insertion unit 9 in each line of the Y interface system is connected via the line 32 Of the other one line of the Y interface system is transferred from the alarm processing unit 60 via the line 33 to the data of the other one of the lines of the Y interface system. Include an alarm for one line.

A frame pattern insertion unit 10 for inserting a Y interface frame pattern into one of the other lines in each line is provided with a frame pattern into the data of the other one line in each of the Y interface lines via the line 34. And sends out data and a Y interface alarm to one of the other Y interface lines via the line 35.

The synchronizer 11 for one of the lines in the Y interface frame synchronizes the input data with the frame from one of the lines in the Y interface via the line 41. One
The alarm detection unit 12 for one line performs alarm and data classification for one line among each line of the Y interface system via the line 42.

The alarm of one of the lines in the Y interface system is transferred to the alarm processing unit 60 via the line 43, and the data is transferred to the clock transfer unit 13 in the device, where the data is transferred via the line 44. The phase is switched from the clock extracted from the data of one of the lines of the Y interface system to the internal clock.

Similarly, the synchronizing unit 14 of the other one of the lines of the Y interface frame causes the other one of the lines of the Y interface frame to connect to the line 46.
Synchronizes the input data with each other through the interface, and detects the alarm of the other one of the lines in the Y interface system.
5, the alarm and data of one of the other lines in the Y interface system are separated through the line 47.

Other 1 in each line of Y interface system
The alarm of one line is transferred to the alarm processing unit 60 via the line 48, and the data is transferred to the clock transfer unit 16 to the internal clock via the line 49, where the other one of the lines in the Y interface system is connected. The phase is switched from the clock extracted from the data of one line to the internal clock.

The data multiplexing unit 17 multiplexes data of each line via the lines 41 and 50, and the I interface system clock transfer unit 18 converts the internal clock from the device clock to the I interface system clock via the line 51. Is performed.

The I-interface alarm insertion unit 19 transfers data via the line 52, transfers the I-interface alarm from the alarm processing unit 60 via the line 53, and incorporates the I-interface alarm into the data. The interface frame pattern insertion unit 20 inserts an I interface frame pattern into data via the line 54,
The data and the I interface alarm are sent to the I interface via the line 55.

FIG. 2 is a block diagram showing an embodiment of the alarm processing section 60 in FIG.

The operation in the alarm processing unit of one of the lines of the Y interface system will be described.

When an input line disconnection or out-of-synchronization detection unit (hereinafter referred to as a TE REC unit 61) in the direction from the terminal side to a DSU (digital line terminator) is detected, the terminal side → DSU via a line 71. The transfer is performed by a failure-time transfer unit in the direction (hereinafter, referred to as a TE SEND transfer unit 67).

When an input line disconnection or out-of-synchronization detection unit (hereinafter referred to as a LINE SEND detection unit 63) in the direction from the subscriber side to the DSU detects the input line, the DS
Failure during the transfer portion between U~DSU (D CE N OT R EA
(DY: hereinafter, referred to as a DNR transfer unit 68).

On the network side of the user / network interface, a portion for detecting that the layer 1 capability toward the terminal has been changed (1.5 M A LARM I NDICA)
TION S IGNAL: below, when detected by the called a 1.5M AIS detecting section 64), via a line 73 D
The data is transferred by the NR transfer unit 68.

When a 1.5M logical path out-of-synchronization detection unit (hereinafter referred to as a 1.5M REC detection unit 65) detects the 1.5M logical path out-of-synchronism, it is transferred by a DNR transfer unit 68 via a line 74.

On the network side of the user / network interface, when a part for detecting that the layer 1 capability in the subscriber direction is lost (hereinafter referred to as a 1.5M BAIS detection unit 66) is detected. , Via the line 75 at the DNR transfer unit 68.

The data terminal device is a state when the transfer of the disorder or or unavailable (DTE U NCONTROLLED
N OT R EADY: below, to send the always "0" (referred to as the time of normal) in the referred to as UNR transfer unit).

A portion ( S STATUS: hereinafter, referred to as an S transfer portion) for transmitting whether or not the DTE is communicating is always transmitting "1" (meaning that communication is in progress). Terminal side → D
When a failure detection unit in the SU direction (hereinafter, referred to as a TE SEND detection unit 62) detects the failure, the TE
1.5M A at REC detection, TE SEND detection
When IS is detected, transfer unit when 1.5M REC is detected (hereinafter referred to as K
x transfer unit 69).

In the same manner as described above, the alarm processing for the other lines in each line of the Y interface system is also performed.

[0029]

As described above, according to the present invention,
An effect is obtained in which the Y-line multi-channel line and the I-interface line are connected to the digital line terminating device to allow mutual entry (mutual data communication).

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of an alarm processing unit shown in FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... I interface system frame synchronization part 2 ... I interface system alarm detection part 3 ... Clock switching part in apparatus 4 ... Data division part 5 ... Y interface system Clock switching part to one one line among each line 6 ... Y interface system Alarm insertion unit for one line in each line 7... Frame insertion unit for one line in each line of Y interface system 8. Clock switching unit for one other line in each line of Y interface system 9. Alarm insertion unit for one other line in each interface line 10 Frame insertion unit for one other line in each Y interface line 11 Frame synchronization unit for one line in each Y interface line 12 Alarm detection unit for one line in each line of Y interface system 13 ... One time in each line Clock switching unit within the device 14 ... Frame synchronization unit of one other line in each line of Y interface system 15 ... Alarm detection unit of one other line in each line of Y interface system 16 ... One other line of each line of Y interface system Clock switching unit 17 in the apparatus 17 data multiplexing unit 18 switching unit to I interface system clock 19 ... I interface system alarm insertion unit 20 ... I interface system frame pattern insertion unit 21 ... I interface line-I interface system frame synchronization Inter-unit line 22 ... I-interface system frame synchronization unit-I-interface system alarm detection unit line 23 ... I-interface system alarm detection unit-alarm processing unit line 24 ... I-interface system alarm detection unit-in-device clock transfer unit line 25: Clock transfer unit in the device-data Line between divisional units 26 ... Line between clock transfer units of one line in each line of data division unit-Y interface system 27 ... Clock transfer unit of one line in each line of Y interface system-between each line of Y interface system 1
Line between two alarm insertion units 28 ... Alarm processing unit-Y interface system One in each line
Line between alarm insertion units of two lines 29 ... Alarm insertion unit of one line in each Y interface system-portion for inserting Y interface frame pattern into one line in each line 30 ... Y interface system frame pattern A part to be inserted into one line among each line-Y interface system One line among each line 31 ... Data division unit-Y interface system Line between clock transfer units of one other line among each line 32 ... Y interface system Clock interchanging unit-line between alarm insertion units of one other line in each line of Y interface system 33 ... Alarm processing unit-line between alarm insertion units of one other line in each line of Y interface system 34 ... Y interface system The alarm insertion part of one other line in the line-the Y interface frame pattern Part to be inserted into one line 35 ... Part to insert Y interface frame pattern into one other line in each line-One other line in each Y interface line 41 ... One in each Y interface line Line-Y
Line between synchronous units of one line in each interface system frame pattern line 42... Line between the synchronous unit of one line in each line of Y interface system frame pattern and the alarm detection unit of one line in each Y interface system line 43: a line between the alarm detection unit and the alarm processing unit of one of the Y interface lines 44: an alarm detection unit of one of the lines in the Y interface system and the line between the clock transfer units 45 within the device Line between clock transfer unit and data multiplexing unit 46 ... Line between data multiplexing unit and I interface system clock transfer unit 47 ... Line between I interface system clock transfer unit and I interface system alarm insertion unit 48 ... Alarm processing unit- Line between I interface alarm insertion units 49 ... I interface alarm insertion unit-I interface system Line between frame pattern insertion units 50 ... I interface system frame pattern insertion unit-I interface system line 60 ... Alarm processing unit 61 ... TE REC detection unit 62 ... TE SEND detection unit 63 ... LINE SEND detection unit 64 ... 1.5M AIS detection unit 65 1.5 M REC detection unit 66 1.5 M BAIS detection unit 67 TE SEND transfer unit 68 DNR transfer unit 69 Kx transfer unit 71 TE REC-TE SEND line 72 72 LINE SEND-DNR line 73 ... 1.5M AIS-DNR line 74 ... 1.5M REC-DNR line 75 ... 1.5M BAIS-DNR line 76 ... TE SEND-Kx line

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-271552 (JP, A) JP-A-5-153186 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 29/10 H04J 3/12 H04L 12/02 H04L 7/00

Claims (1)

(57) [Claims] 1. An I-interface frame synchronizing unit and I
Interface system frame pattern insertion unit, I interface system alarm detection unit, I interface system alarm insertion unit, and I
A clock transfer unit for switching from the interface clock to the internal clock, a clock transfer unit for converting the internal clock to the I interface clock, a data dividing unit for dividing the I interface data into each Y interface line, and each Y interface line A data multiplexing unit for multiplexing data to an I-interface line, a Y-interface alarm detection unit and a Y-interface alarm insertion unit in one of the Y-interface lines, and an internal clock to a Y-interface clock. A clock transfer unit, a clock transfer unit from the Y interface clock to the internal clock, a Y interface frame synchronization unit, and a Y interface frame pattern insertion unit. Interface alarm detection unit, Y interface alarm insertion unit, clock transfer unit from internal clock to Y interface clock, clock transfer unit from Y interface clock to internal clock, Y interface frame synchronization unit, Y interface System frame pattern insertion unit, and the alarm processing unit outputs the output of the I interface system alarm detection unit and the output of the alarm detection unit of each Y interface system line to the Y interface system line. A digital line termination device for performing ALM conversion (degeneration / pseudo-transfer) input to an insertion unit.