JPS61156920A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To attain a compact A/D converter by providing a reference voltage source in common to plural comparators and connecting sequentially the reference voltage source to the plural comparators to decrease the A/D converting time. CONSTITUTION:The D/A converter 15 is provided in common to the two comparators 1, 2, the D/A converter 15 receives a prescribed voltage VC to apply D/A conversion to a digital signal supplied from sequential comparison registers 16A, 16B via a multiplexer 18. Input signals A, B and a reference voltage Vref are inputted alternately to the comparators 1, 2, and when the input signal is larger, a low level signal is outputted and when the input signal is smaller, a high level signal is outputted. The contents of each bit of the sequential comparison registers 16A, 16B are decided in order from the high order to the low order based on the result of comparison in the comparators 1, 2 and a digital signal in matching with the input signal A finally remains in the registers. Then the size of the entire A/D converter or the area is decreased and the converting time is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an A/D (analog/digital) conversion device.

[Technical Background of the Invention and Problems with the Background Art] Conventionally, when a plurality of analog signals are A/D converted at the same time, the same number of A/D converters as the signals are required. For this reason, there is a problem that the Δ/D conversion device becomes large and, when integrated into an IC, its area becomes large. Also, when multiple signals are Δ/D converted by one A/D converter, the area of the A/D converter can be small, but the signals must be A/D converted one by one. Therefore, there is a drawback that the conversion time becomes long.

[Purpose of the invention]

The purpose of the present invention is to shorten the A/D conversion time and to
In order to make the conversion device compact, that is, to make it into an IC, the objective is to reduce its area.

[Summary of the invention]

The A/D conversion device of the present invention includes a plurality of chopper type comparators respectively corresponding to a plurality of input signals, a reference voltage source is provided in common for the plurality of comparators, and a reference voltage source is provided between the plurality of comparators. It is designed to connect sequentially.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention.

The A/D converter of this embodiment has two input signals A.

Chopper type comparators 1 and 2 are provided corresponding to input signal voltages A and B, respectively. This chopper type comparator is basically used for example in U.S. Pat.
676.702 and has an inverter 9.10, a capacitor 11.12, and switches 3 to 8, but in the comparator of this embodiment, switch 4
, 5.7 and switches 3.6.8 are alternately opened and closed. That is, the switches 4.5.7 are not shown in FIG.
is closed when clock signal φ1 is at a high level, while switches 3 and 6.8 are closed when clock signal φ1 is at a low level.

A D/A (digital/analog) converter 15 is provided in common for the two comparators 1.2.
The converter 15 has a constant voltage ■. and converts a digital signal supplied via a multiplexer 18 from successive approximation registers 16A and 16B, which will be described later, to a digital signal, and its output is a reference voltage V. f is alternately supplied to capacitors 11 and 12 of comparators 1 and 2 via switches 4 and 6, respectively. That is, when the reference voltage is to be supplied to the comparator 1, the contents of the successive approximation register 16A are supplied to the D/A converter by the multiplexer 18,
The A-converted voltage becomes the reference voltage. On the other hand, when the reference voltage should be supplied to the comparator 2, the multiplexer 18
The contents of the successive approximation register 16B are supplied to the D/A converter, and the result of D/A conversion becomes the base ts lightning voltage.

Comparator 1.2 alternately inputs input signals A and B and reference voltage vref, and when the input signal is larger, it outputs a low level (
When the input signal is smaller, it outputs a high level signal (“1” level). That is, as shown in FIG. 2, each comparator 1 takes in the reference voltage Vref when the clock signal φ1 is at a high level. At this time, the switch 7 is in the closed state, so the inverter 9 is short-circuited, and the capacitor 11 is connected to the reference voltage
charged to ref. The above operation is called autoze-O.

Next, when the clock signal φ1 becomes low level, the input signal A
is input. At this time, since the switch is open, the inverter 9 resumes its function. That is, if the input signal A is higher than the charging voltage of the capacitor 11, the output of the inverter 9 becomes "0", and if the input signal A is lower, the output of the inverter 9 becomes "1". in this way,
The comparison is performed when the clock signal φ1 is at a low level.

Comparator 2 also operates similarly to comparator 1. However, the comparator 2 performs autozero when the clock signal φ1 is at a low level, and performs the comparison when the clock signal φ1 is at a high level.

Control circuits 17A and 17B each receive the output of comparator 1.2, and successive approximation register 6A.

16B. That is, based on the comparison result in the comparator 1.2, the successive approximation registers 16A, 16
The contents of each bit of B are determined in order from the higher order to the lower order. This point will be discussed in detail below. In the successive approximation register, at the start of conversion, its MSB is set to "1" and all other bits are set to rOJ. As a result, the maximum voltage □ is generated from the D/A converter. Then, if the output of the comparator is O (that is, if the input signal is stronger, the next bit, that is, the second bit, with the MSB set to "1") is set to "1" by 16 degrees. As a result, D/ The A converter generates the maximum negative voltage. Conversely, if the input signal is smaller, the MSB is set to rOJ and the second bit is set to "1". As a result, the maximum voltage □ is generated from the D/A converter. As a result of the comparison immediately after setting the second bit to "1", if the input signal is larger, the third bit is set to "1" with the second bit set to "1", and if the - universal signal is smaller, the input signal is set to "1". 2
Set the bit to "0" and the third bit to "1". Thereafter, the value of each bit is determined in the same manner up to the LSB.

By doing this, at the end (when the above operation reaches the LSB), the digital signal that matches input signal A remains in the register. This digital signal is read out as a result of A/D conversion.

According to the above embodiment, one reference voltage source, that is, one D/A converter is sufficient for two comparators, and the size and area of the entire A/D converter is reduced.

Furthermore, the conversion time is almost the same as when two reference voltage sources are used.

In the above embodiment, a D/A converter is used as the reference voltage source, but other sources may be used.

Further, in the above embodiment, the reference voltage source is provided in common for two chopper type comparators, but it may be provided in common for three or more chopper type comparators.

For example, FIG. 3 shows the configuration of the comparator section in the case where one reference voltage source is provided in common for three chopper type comparators. As shown in the figure, switches 3A to 3G, 4Δ... for selectively inputting input signals A, B, C and reference voltage Vref
Switch 7 that shorts 4C and inverters 9A to 9C
A to 7C are not shown in FIG. 4 and are three-phase clock signals φ1. φ2
．． Closed when φ3 is at high level. Switches 4A to 4C and switches 7A to 7C as in the case of Fig. 1
When the capacitor 11A~ is closed, the reference voltage vref
11C, and when the switches 3A to 3C are closed, the input signals A to C are captured and compared.

[Effects of the Invention] As described above, according to the present invention, a common reference voltage source is provided for a plurality of comparators, so that the device becomes smaller and, when integrated into an IC, the area becomes smaller. Furthermore, there is an advantage that the conversion time is shorter than when a plurality of signals are sequentially A/D converted by one A/D converter.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing one embodiment of the A/D conversion device of the present invention, Fig. 2 is a time chart showing the operation of the device of Fig. 1, and Fig. 3 is a comparison of other embodiments of the present invention. FIG. 4 is a time chart showing a clock signal used to control the switch in FIG. 3. 1.1A to 1C92... Comparator, 3 to 8... Switch, 9.10... Inverter, 11.12... Capacitor, 15... D/A converter, 16A, 16B...
・Successive approximation register, 17A, 17B...control circuit,
18...Maru f-brexa. Applicant's agent Kiyoshi Inomata Figure 1 Figure 2 Comparison 8 → Mu-Kai 4 paddles (4 stops + 4 paddles ←-----3rd
Figure ■! f Figure 4 p3

Claims (1)

[Claims] 1. In an A/D converter that simultaneously A/D converts a plurality of input signals, an A/D converter is provided corresponding to each of the plurality of input signals and alternately receives the corresponding input signal and a reference voltage. A chopper-type comparator that compares both of them by using a plurality of chopper-type comparators; and a reference voltage source that is provided in common to the plurality of chopper-type comparators and sequentially supplies a reference voltage to the plurality of chopper-type comparators.
/D conversion device. 2. The reference voltage source is provided in common to the two chopper comparators, and when one chopper comparator receives a corresponding input signal, it supplies the reference voltage to the other chopper comparator; 2. The apparatus of claim 1, wherein a reference voltage is provided to said one chopper comparator when said other chopper comparator receives a corresponding input signal. 3. The reference voltage source includes a D/A converter, a plurality of successive approximation registers are provided corresponding to the comparators, and the value of each bit is determined from the highest order according to the comparison result in the corresponding comparator. 3. The apparatus according to claim 1, wherein the contents of the plurality of successive approximation registers are sequentially determined and selectively supplied to the D/A converter via a multiplexer.