JPS61156839A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61156839A JPS61156839A JP59276777A JP27677784A JPS61156839A JP S61156839 A JPS61156839 A JP S61156839A JP 59276777 A JP59276777 A JP 59276777A JP 27677784 A JP27677784 A JP 27677784A JP S61156839 A JPS61156839 A JP S61156839A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- semiconductor device
- chip
- coordinates
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ウェハを個々忙分割したチップが外装容器白
和組立てられた半導体装置に関し、さらに詳述すればウ
ェハ上のチップ座標に対応する表示マークを外装容器上
に施した半導体装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device in which chips obtained by dividing a wafer into individual chips are assembled in an outer package. This invention relates to a semiconductor device in which a display mark is provided on an outer container.
半導体装置は、半導体ウエノSに半導体装置の中枢機能
をはたすチップを形成するウエノ・プロセスと、当該チ
ップ1個を部品として外装容器に組立てる組立プロセス
と、組立の完了した当該装置のテスト、分類2品質保証
を行うテスト工程を経て製作されている。第2図はウェ
ハプロセスの完了した段階のウェハ1と、その上に整然
と形成されたチップ2を示している。また、第3図は第
2図のチップ群の中から1個のチップ2を使用して外装
容器としてのパッケージ3内に組立てた半導体装置4を
示している。なお、第2図中、5はリード導体、6はこ
の各リード導体6とチップ2の各電極とを接続する配線
ワイヤ〜である。Semiconductor devices are manufactured using the Ueno process, in which a chip that performs the core functions of the semiconductor device is formed on the semiconductor Ueno S, the assembly process in which the chip is assembled into an outer container as a component, and the testing and classification of the device after the assembly is completed. It is manufactured through a testing process to ensure quality. FIG. 2 shows the wafer 1 at the completed stage of the wafer process and the chips 2 formed on it in an orderly manner. Further, FIG. 3 shows a semiconductor device 4 assembled in a package 3 as an outer container using one chip 2 from the chip group shown in FIG. In FIG. 2, 5 is a lead conductor, and 6 is a wiring wire connecting each lead conductor 6 and each electrode of the chip 2.
ところで、通常、半導体装置の製造工程忙おいては、ウ
ェハプロセスの完了後各チップの電気特性がテストされ
、設定された基準に合格するチップのみが組立てられて
いる。しかし、ウェハプロセス完了段階でのテストで合
格となったチップが使用されて組立てられた半導体装置
でも組立て段階での特性変化9組立て工程での欠陥の発
生、ウェハ段階では充分なテストができにくい等の問題
があり、最終工程で再度テストを行なっている実情であ
る。By the way, normally, during the busy manufacturing process of semiconductor devices, the electrical characteristics of each chip are tested after the wafer process is completed, and only chips that pass set standards are assembled. However, even if semiconductor devices are assembled using chips that passed the test at the completion stage of the wafer process, characteristics change during the assembly stage. Due to this problem, the test is being conducted again in the final process.
本発明は、このような事情に鑑みてなされたもので、半
導体装置の製造プロセス特にウェハプロセスの有効な手
がかシを与えることのできる半導体装置を提供するもの
である。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that can provide an effective basis for the semiconductor device manufacturing process, particularly the wafer process.
本発明による半導体装置は、ウェハ上に形成されるチッ
プ群の座標に対応する表示を外装容器上に施したことを
特徴とするものである。A semiconductor device according to the present invention is characterized in that a display corresponding to the coordinates of a group of chips formed on a wafer is provided on an outer container.
本発明においては、半導体装置の最終的な特性をウェハ
上のチップ座標にフィードバックでき、ウニ八面上の特
性分布図等として利用することにより、ウェハプロセス
の制御の精度の良し悪しや問題点の抽出、特性改善等の
目的に有効な手がかりを与えることが可能になる。In the present invention, the final characteristics of the semiconductor device can be fed back to the chip coordinates on the wafer, and by using it as a characteristic distribution map on the eight surfaces, it is possible to check the precision of wafer process control and identify problems. It becomes possible to provide effective clues for purposes such as extraction and characteristic improvement.
以下、本発明を図面に示す実施例に基いて説明する。 The present invention will be explained below based on embodiments shown in the drawings.
第1図は本発明の一実施例による半導体装置の平面図で
ある。この実施例では、ウェハプロセスの完了した第2
図に示すウェハ1を個々のチップ2に分割すべき水平お
よび垂直方向の分割ライン11.12をそれぞれ座標軸
とし、この任意のXY座標Tに位置するチップ2をパッ
ケージ3内に組立てたうえ、このパッケージ3上に、第
1図に示すごと(abなる表示マーク8を上記座標T。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. In this example, the second
The horizontal and vertical dividing lines 11 and 12 for dividing the wafer 1 into individual chips 2 shown in the figure are used as coordinate axes, and the chips 2 located at the arbitrary XY coordinates T are assembled in the package 3, and On the package 3, place a mark 8 (ab) at the above coordinates T as shown in FIG.
XY値に対する表示として設けたものである。This is provided as a display for XY values.
ここで、かかる表示を具体的に行う手段としては、ウェ
ハ1を個々のチップ2に分割し、そのチップを順次組立
てに供して行く段階においてウェハ1上のチップ2のX
Y座標値と組立てに供された順序を制御装置iiに記憶
せしめ、半導体装置形成の最終段階でこの制御装置内に
記憶された上記内容を引き出し、abなる表示を行なわ
せることが考えられる。Here, as a means for specifically performing such display, the wafer 1 is divided into individual chips 2, and the chips 2 on the wafer 1 are
It is conceivable that the Y coordinate value and the order of assembly are stored in the control device ii, and at the final stage of semiconductor device formation, the above-mentioned contents stored in the control device are retrieved and displayed as ab.
しかして、組立プロセス、テストプロセスは、通常、半
導体装置は多数個で構成されるロット単位に扱われて加
工が進捗される。このため、ウェハ上のチップ座標は乱
れてしまう。対応をつけようとすると、慎重でぼう大な
実験手法をもって行う必要があり、多量を行うのは極め
て困難である。In the assembly process and test process, semiconductor devices are usually processed in lots each consisting of a large number of semiconductor devices. Therefore, the chip coordinates on the wafer are disturbed. Attempting to respond requires careful and extensive experimental methods, and it is extremely difficult to do so in large quantities.
上記した本発明を適用すれば、第1図のabで例示した
表示マーク8でもって簡単にウェハ1上のチップ座標に
展開しなおすことができ、量産を進めながら特に余分な
手間をかけることなしにデータの蓄積が可能となる。ま
た、第1図のabなる表示は自動的に当該表示マーク8
を読み取る装置を追加すれば、はぼ完全自動の形で半導
体装置の最終特性や必要な段階での特性をウェハ上のチ
ップ座標にフィードバック可能となる。If the present invention described above is applied, it is possible to easily re-deploy the chip coordinates on the wafer 1 using the display mark 8 illustrated as ab in FIG. 1, without requiring any extra effort while proceeding with mass production. It becomes possible to accumulate data. Also, the display ab in Fig. 1 is automatically indicated by the corresponding display mark 8.
By adding a device that reads , it becomes possible to feed back the final characteristics of semiconductor devices and the characteristics at necessary stages to the chip coordinates on the wafer in a completely automatic manner.
なお、上記実施例では1ウエハ上のチップ座標につき説
明したが、複数のウェハが存するときはウニへ間の区分
をするための表示を追加することも可能である。In the above embodiment, the chip coordinates on one wafer have been described, but when a plurality of wafers exist, it is also possible to add a display to distinguish between the wafers.
さらに、組立プロセス以降の加工要素を新たに加えてこ
れをab−cなどと表示することも可能で。Furthermore, it is also possible to add new processing elements after the assembly process and display them as ab-c, etc.
情報果状機能はいくらでも拡大できる。Information functions can be expanded to any extent.
以上のように2本発明によれば、半導体装置上に施され
た表示から半導体装置の量産を実行しつつウェハ上のチ
ップ座標対応に特性がフィードバックでき、これ等のフ
ィードバックされる多量の有効データを分析、解析、J
I埋することにより、半導体装置の歩留2品質、特性の
向上ならびに改善が可能になる効果がある。As described above, according to two aspects of the present invention, characteristics can be fed back to chip coordinates on a wafer while mass-producing semiconductor devices from displays made on the semiconductor devices, and a large amount of valid data is fed back. Analyze, Analyze, J
I-burying has the effect of making it possible to improve the yield, quality, and characteristics of semiconductor devices.
第1図は本発明の一実施例による半導体装置の平面図、
第2図はチップ形成が完了した通常のウェハの平面図、
第3図は同じく通常の半導体装置の一部切欠斜視図であ
る。
1・・・ψウェハ、2−・・・チップ、3・・・・パッ
ケージ、4・・・・半導体装置、5・・・・リード導体
、6・・・・配線ワイヤ、7・・・・ウェハ上のチップ
座標、8・・・・表示マーク。
代 理 人 大 岩 増 雄第 1
図
8:蔦示ン−7
第 2 図
第3図
を
手続補正書(自発)
2、発明の名称
半導体装置
3、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目2番3号名
称 (601)三菱電機株式会社代表者片山仁八部
4、代理人
5、補正の対象
(2)同書同頁8行の「リード導体6」を「リード導体
5」と補正する。
以 上FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention;
Figure 2 is a plan view of a normal wafer on which chip formation has been completed;
FIG. 3 is a partially cutaway perspective view of a conventional semiconductor device. 1... ψ wafer, 2-... chip, 3... package, 4... semiconductor device, 5... lead conductor, 6... wiring wire, 7... Chip coordinates on the wafer, 8...display mark. Agent Masu Oiwa 1st
Figure 8: Tsuta Show-7 Figure 2 Procedural amendment to Figure 3 (voluntary) 2. Name of the invention Semiconductor device 3. Relationship with the person making the amendment Patent applicant address 2-chome Marunouchi, Chiyoda-ku, Tokyo No. 2 No. 3 Name Title (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent 5, Subject of amendment (2) Amended "Lead conductor 6" in line 8 of the same page of the same book to "Lead conductor 5" do. that's all
Claims (1)
半導体装置において、前記ウェハ上のチップ位置座標に
対応する表示マークを前記外装容器上に設けたことを特
徴とする半導体装置。1. A semiconductor device in which chips obtained by dividing a wafer into individual chips are assembled in an outer container, characterized in that a display mark corresponding to the chip position coordinates on the wafer is provided on the outer container.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59276777A JPS61156839A (en) | 1984-12-28 | 1984-12-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59276777A JPS61156839A (en) | 1984-12-28 | 1984-12-28 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61156839A true JPS61156839A (en) | 1986-07-16 |
Family
ID=17574210
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59276777A Pending JPS61156839A (en) | 1984-12-28 | 1984-12-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61156839A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0390447U (en) * | 1989-12-28 | 1991-09-13 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5735332A (en) * | 1980-08-12 | 1982-02-25 | Nec Corp | Semiconductor device |
JPS5771151A (en) * | 1980-10-22 | 1982-05-01 | Nec Corp | Pakage for semiconductor device |
-
1984
- 1984-12-28 JP JP59276777A patent/JPS61156839A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5735332A (en) * | 1980-08-12 | 1982-02-25 | Nec Corp | Semiconductor device |
JPS5771151A (en) * | 1980-10-22 | 1982-05-01 | Nec Corp | Pakage for semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0390447U (en) * | 1989-12-28 | 1991-09-13 |
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