JPH01286441A - Layout design system for analog ic - Google Patents

Abstract

PURPOSE:To enable the connection between external terminals by using short wiring, restrain redundant wirings, and reduce wiring regions between blocks, by arranging external terminals in a block, and effectively utilizing the space in the block for wirings between the external terminals. CONSTITUTION:The coordinate 11 of a position on a block boundary side and a wiring layer (leading-out wiring layer) connected with an external terminal are designated as input information to the external terminal of a block. The external terminal is situated inside a position on the designated block boundary side. In an automatic wiring process between blocks, block external terminals 8 are designated so as to be capable of wiring between two terminals which form a pair and have the same potential. The two terminals are connected by using only one bent wiring layer 9, and wiring is performed by effectively utilizing wiring regions which are not yet used in the block.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an analog IC layout design method [Prior Art] Regarding the conventional analog IC layout design method,
IEICE Study Group Report, CA386-211 No. 59
As discussed on pages 87 to 87, (1)
The external terminal of the block is located on the block boundary, (2)
In inter-block wiring, two or more wiring layers are used to connect terminals if necessary.

[Problem to be solved by the invention]

(1) Machiki's technology for automatic layout within a block processes external terminals on block boundaries in detailed layout, whereas external terminal positions are determined after a rough layout within a block. Since the rough layout results and the detailed layout results differ in the shape of the blocks, the optimal position of the block's external terminals on the chip changes, and redundant wiring occurs in the wiring process between blocks. An object of the present invention to solve this problem is to avoid redundant wiring by locating external terminals within blocks.

(2) In addition, the conventional technology for inter-block wiring used two wiring layers to connect terminals with the same potential, so vias (hereinafter referred to as through-holes) were used as relays between the two. was necessary. Since the distance between a through hole and a wire is larger than the distance between a wire and a wire, conventional methods requiring through holes require a large wiring area between blocks. An object of the present invention to solve this problem is to connect terminals of the same potential between blocks using one wiring layer, thereby reducing the wiring area between blocks.

(b) Furthermore, in the inter-block wiring process, since the empty area within the block was not used, a large amount of wiring area between the blocks was required. An object of the present invention is to reduce the wiring area between blocks by effectively using the free space within the blocks.

[Means for solving the problem] The above objectives are as follows: (1) After rough layout in the block, 1
Create a set of two external terminals that should be wired in one wiring layer, determine the position of each external terminal on the block boundary, and (2) at the time of detailed layout within the block, (a) After drawing out the wiring to the terminal position and securing a wiring path so that it will not become unwired during inter-block wiring processing, the wiring is reduced as long as the same layer as the extraction wiring continues, and the external terminal is positioned inside the block.

(b) For lead wiring to external terminals, if necessary, convert the wiring layer inside the block and process it using the designated wiring layer. (c) Determine areas that cannot be penetrated by interblock wiring processing.

(3) For inter-block wiring, wire between the two external terminals determined in (1) using the specified wiring layer so as not to invade the area determined in (2) (c).

achieved.

[Effect]

External terminals are included in the block, and wiring between blocks is
Wiring between external terminals is performed by effectively utilizing the free space within the block, making it possible to connect external terminals with short wiring lengths, suppressing redundant wiring, and reducing the wiring area between blocks. .

In addition, within the block, if possible, create a through hole on the element to convert the layer, wire to the external terminal on the specified wiring layer, and wire between the external terminals by bending the same layer. The increase in area due to holes can be suppressed, and the wiring area between blocks can be reduced.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 shows a block layout model. 1 is the boundary of the block, 2 is the cell frame, and 3 is the cell terminal covered with the first layer of AQ.

The cells are arranged at arbitrary positions within the block, and the wiring within the block connects between cell terminals and between the cell terminals and the external terminals of 4. Here, the external terminal refers to a lead-out end point of a wiring that has a connection relationship with another block, and may exist on a block boundary side or inside a block. The wiring layer is AQ first! (5) and the Aff second layer (6), both of which are connected by a through hole (7).

Any of the wiring layers can be used freely horizontally and vertically, that is, without limitation in layer direction.

FIG. 1 shows an embodiment of the present invention. In the detailed layout within the block, the wiring up to the external terminal (8) is wired using the specified wiring layer (AQ 1st wJ in the example), and the external terminals are scattered inside the block.

In inter-block wiring processing, wiring between external terminals (9
) is done by making effective use of the space within the block. Therefore, there is no redundant wiring and no special wiring area is required between blocks (10). Note that 11 is the external terminal position specified after the rough layout.

Figure 2 shows the results obtained using the conventional method. The block external terminal (12) is drawn out to the block boundary (14) according to the designated position (13) after the rough layout. All wiring between external terminals (15) is done between blocks (16), so the X of external terminals facing each other vertically as shown in the figure
If the coordinates are not the same, a wiring area is necessarily required, and if the wiring layers of the two external terminals are different, a through hole is required, which requires an even larger wiring area. Additionally, redundant wiring due to deviations in the X coordinates of external terminals is also seen.

The difference between the proposed method shown in FIG. 1 and the conventional method shown in FIG. 2 is that the proposed method performs the following three points that the conventional method does not have.

(a) Specify the wiring layer of the wiring to be drawn out to the external terminal as detailed manual information in the block 1 to 1.

(b) In the detailed block layout, after pulling out the wiring to the specified external terminal position,
Reduce as much as possible toward the cell terminal from which it is extracted.

(,) To effectively utilize free space within a block in inter-block wiring processing.

As a result, in the embodiment, there is no need to provide a wiring area between blocks, and redundant wiring does not occur.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the wiring area between blocks can be reduced compared to the conventional method.
Chip area can be reduced. This contributes to reducing chip design costs and improving yield.

[Brief explanation of the drawing]

FIG. 1 is a layout symbol diagram of two blocks according to an embodiment of the present invention, FIG. 2 is a layout symbol diagram of two blocks according to the conventional method, and FIG. 3 is a symbol diagram of a block layout model. be. 1.14...Block boundary side, 2...Cell frame, 3.
...Cell terminal, 4,8.12...External terminal, 5...
AQ first layer wiring, 6... AQ second layer wiring, 7... Through hole, 9.15... Wiring between external terminals, 10.
16... Inter-block wiring area, 11.13... Specified external terminal position.

Claims (1)

[Claims] 1. In automatic layout processing within a block of an analog IC, (a) input information of the external terminal of the block includes (a) position coordinates on the block boundary side, (b) wiring connected to the external terminal (hereinafter referred to as the extraction wiring layer). (b) Incorporate an external terminal inside the specified block boundary side, and in the inter-block automatic wiring process, (c) Create a block external terminal that allows wiring between two terminals with the same potential in a pair. (d) connecting the above two terminals using a single wiring layer using bending; and (e) effectively utilizing an unused area within the block for wiring. method.