JPS61156820A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To allow the gettering of damaging impurities and lattice distortions in the epitaxial growth process by implanting selectively ionized Si atoms onto the surface of a semiconductor substrate to form dislocation regions on the substrate surface and applying heat-treatment prior to the process. CONSTITUTION:By depositing a BSG film 7 on the surface of a wafer 1 which has been partially implanted with ionized Si atoms through a diffusion window 4, and applying heat-treatment to the wafer 1, a P<+> type diffusion region 8 is formed due to boron diffusion from the film 7 and, at the same time, a disloca tion region 6' is formed in the portion where Si ions have been implanted. The dislocation region 6' absorbs damaging impurities 5 remaining in the wafer 1 by virtue of gettering effect of the region 6' so that a wafer free from defects in its crystalline structure is produced. Accordingly heat-treatment at about 1,000 deg.C, which has been separately applied as adopted in the conventional method that uses a PSG film, is omitted to facilitate the manufacture of semicon ductor devices having shallow junctions such as high speed and high frequency transistors.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, for suppressing generation of harmful impurities such as lattice strain, lattice defects, and IJium in an active region. The present invention relates to a method of manufacturing a semiconductor device with an improved gettering process.

[Technical background of the invention and its problems]

BACKGROUND ART Semiconductor devices, particularly semiconductor integrated circuits, are often contaminated with harmful impurities such as heavy metals and carbon dioxide during or before and after the manufacturing process.

If these harmful impurities, lattice strains, or defects are present in the active region of the device, problems such as deterioration of reverse breakdown voltage, decrease in current amplification factor, and increase in noise figure occur, making it impossible to obtain a normal semiconductor device. For this reason, conventionally a method has been adopted in which a phosphorous-doped glass film (PSG film) is formed on the front and back surfaces of a silicon substrate, and heat treatment is performed at approximately 1000°C to take advantage of the harmful impurity suction effect of PSG. It had been.

However, the conventional method of gettering using the PSG film described above has the following problems.

■ Heat treatment at around 1000°C is required to suck out harmful impurities such as heavy metals and carbon from PEG, so it is suitable for semiconductor devices that require shallow junctions such as miniaturized elements, high speed/high frequency elements, etc. cannot be applied.

(2) At the same time as the effect of sucking out harmful impurities, highly concentrated phosphorus also diffuses to the back surface of the silicon substrate, and an outward diffusion phenomenon of the phosphorus occurs in the next process.

If the above-mentioned problems are to be alleviated, the conditions for forming the PSG film will be restricted depending on the type of semiconductor integrated circuit, resulting in the inconvenience that it will be difficult to obtain a semiconductor device with electrically high performance. .

[Purpose of the invention]

The present invention eliminates the need for separate pickling using a PSG film at around 1000°C as in conventional methods, and can remove harmful impurities and lattice distortion through heat treatment during the process. A method for manufacturing an excellent semiconductor device can be provided.

[Summary of the invention]

The present invention includes a step of selectively implanting silicon atoms into the surface of a semiconductor substrate before an epitaxial process to form a dislocation region on the surface of the substrate, and a step of performing heat treatment to bitter harmful impurities in the active region of the semiconductor substrate. It is characterized by having the following.

[Embodiments of the invention]

Hereinafter, an example in which the present invention is applied to manufacturing an epitaxial wafer used in a bipolar IC will be described with reference to FIGS. 1(,) to (d).

Machining: After doping a p-type silicon substrate (p-type silicon wafer) with an n-type impurity, such as antimony, to form an n-medium diffusion layer 2, thermal oxidation treatment is performed to form a thick oxide film 3 on the surface of the wafer 1. did.

Subsequently, the oxide film 3 was selectively removed using photoetching technology to open a diffusion window 4 for forming an element isolation region (
FIG. 1(a) (Illustrated). In addition, 5 in the figure is a harmful impurity present in Kueh 1.

Next, silicon atoms were accelerated at a voltage of 50 ksV.

Ions were implanted into the surface of the wafer 1 through one diffusion window 4 at a dose of 5 x 103 to form a strained layer 6 of excess Si (
Figure (b) shown).

Next, all over? After depositing a ron-doped glass film (BSG film) 7, heat treatment was performed. At this time, BSGS2O2 boron was diffused into the surface of the wafer 1 through the diffusion window 4, and a p-type diffusion region 8 was formed.

At the same time, in the diffusion region 8, movement of dislocations due to excess St in the strained layer 6 occurs, and the strained layer 6 that existed at room temperature
Some residual stress is released.

In this process of movement of dislocations and partial release of residual stress,
As shown in FIG. 6(c), the harmful impurity 5 is absorbed into the dislocation region 6' and is bittened. As a result, a good wafer with no crystal defects is produced.

Next, after completely removing the BAG film 7 and the oxide film 3, epitaxial growth was performed to form a silicon epitaxial layer 9 on the sea urchin 1.

In this heat treatment step, the n-medium type diffusion layer 2 and the p-type natural diffusion region 8 on the surface of the wafer 1 diffuse to the engineered taxial layer side, and the n-medium type buried layer 10. P medium-sized element isolation regions 11 were formed near the interface between the wafer 1 and the epitaxial layer 9 (as shown in FIG. 2D).

It should be noted that during this heat treatment step, residual stress continued to be released, and harmful impurities contained in the epitaxial layer 9 were absorbed into the dislocation region 6'.

According to the present invention, silicon atoms are ion-implanted into the surface of the wafer 1 through the diffusion window 4, BSGS2O2 product is performed, and then heat treatment is performed to produce BSGS2O2.
At the same time as forming the p+ type diffusion region 8 by melon diffusion,
A dislocation region 6' is formed in the silicon ion implanted area, and the harmful impurities 5 in the wafer 1 can be absorbed by the bitter effect of the dislocation region 6', making it possible to produce a wafer free of crystal defects. Therefore, it is possible to omit a separate heat treatment of about 1000° C., which is required in the conventional method using a PSG film, and the method is suitable for manufacturing semiconductor devices having shallow junctions such as high-speed, high-frequency transistors. Further, in the conventional method using a PSG film, a high concentration of phosphorus is also diffused on the back surface of the wafer, which causes a problem of outward diffusion of phosphorus in the next step, but the method of the present invention has no such concern.

In fact, the epitaxial wafer obtained in this example was subjected to the steps up to emitter formation, various insulating films were removed, and then wet oxidation was performed at 1100°C to a thickness of 1.
After forming an oxide film of 0000X, the oxide film was completely removed and crystal defects were exposed using a light etching method.
Observed.

As a result, stacking faults were observed in the epitaxial wafer without pickling, whereas in this example, the epitaxial wafer was equivalent to a conventional epitaxial wafer in which gettering was performed using a PSG film, and no stacking faults were observed at all. Ta.

In addition, lateral P''P) transistors were manufactured using the epitaxial wafer obtained in this example, an epitaxial wafer obtained by gettering with a PSG film (comparative example), and an epitaxial wafer without gettering (conventional example). The noise characteristics of these transistors with respect to frequency were investigated. As a result, the characteristic diagram shown in Fig. 2 was obtained. In Fig. 2, A is the frequency-noise characteristic line of the present example, and B is the comparative example. C is the same characteristic line of the conventional example.

As is clear from FIG. 2, the pnp transistor of this embodiment has significantly improved noise in the low frequency region,
4 It can be seen that the noise has decreased.

〔Effect of the invention〕

As described in detail above, according to the present invention, unlike the conventional method, PS
Harmful impurities and lattice distortions can be gettered in the heat treatment process during the process without the need for gettering at around 1000°C by the G film, resulting in highly integrated semiconductors with shallow junctions and excellent electrical performance. A method for effectively manufacturing the device can be provided.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process of epitaxial wafers in Examples of the present invention, and FIG. 2 is PNPs manufactured from epitaxial wafers obtained in Examples, Comparative Examples, and Conventional Examples. It is a frequency-noise characteristic diagram in a transistor. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate (wafer), 4... Diffusion window for forming an element isolation region, 5... Harmful impurities, 6'...
Dislocation region, 7...BSG film, 9...Silicon epitaxial layer, n+ type buried layer, 11...p+ type element isolation region. Applicant's agent Patent attorney Takeshi Suzue Disciple 1 Figure

Claims (2)

[Claims] (1) A step of selectively implanting silicon atoms into the surface of the semiconductor substrate before the epitaxial process to form a dislocation region on the surface of the substrate, and a heat treatment to eliminate harmful impurities in the active region of the semiconductor substrate into the dislocation region. A method for manufacturing a semiconductor device, comprising the step of gettering. (2) The manufacturing method according to claim 1, wherein the heat treatment for gettering the harmful impurities is also performed by another heat treatment in the manufacturing process of the semiconductor device.