JPS61156777A - Semiconductor light-receiving element - Google Patents
Semiconductor light-receiving elementInfo
- Publication number
- JPS61156777A JPS61156777A JP59274464A JP27446484A JPS61156777A JP S61156777 A JPS61156777 A JP S61156777A JP 59274464 A JP59274464 A JP 59274464A JP 27446484 A JP27446484 A JP 27446484A JP S61156777 A JPS61156777 A JP S61156777A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- multiplying
- region
- type
- band gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 239000012535 impurity Substances 0.000 abstract description 13
- 230000005684 electric field Effects 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 6
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000031700 light absorption Effects 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000007791 liquid phase Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 101150054880 NASP gene Proteins 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アバランシェ・フォト・ダイオード（ａｖａ
ｌａｎｃｈｅ ｐｈｏｔｏ ｄｉｏｄｅ：ＡＰＤ）
と呼ばれる半導体受光素子の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to an avalanche photodiode (AVA).
lunch photo diode (APD)
The present invention relates to improvements in semiconductor light-receiving elements called .
第４図は従来の埋め込み型ＡＰＤを表す要部切断側面図
である。FIG. 4 is a cutaway side view of essential parts of a conventional implantable APD.
図に於いて、１はｎ＋型１ｎＰ基板、２はｎ型ＩｎＰバ
ッファ層、３はエネルギ・ハンド・ギャップが０．７
（ｅＶ）であるようにしたｎ型ＧａＩｎＡｓ光吸収層
、４はエネルギ・ハンド・ギャップが０．９ ［ｅＶ）
であるようにしたｎ型ＧａＩｎＡｓ光吸収層、５はｎ型
１ｎＰ増倍層、６はｎ型１ｎＰガード・リング層、７は
ｐ１型受光領域、ｈνは入射光をそれぞれ示している。In the figure, 1 is an n+ type 1nP substrate, 2 is an n-type InP buffer layer, and 3 is an energy hand gap of 0.7.
(eV) n-type GaInAs light absorption layer, 4 has an energy hand gap of 0.9 [eV]
5 is an n-type 1nP multiplication layer, 6 is an n-type 1nP guard ring layer, 7 is a p1-type light receiving region, and hv is incident light.
このＡＰＤでは、増倍層５及び受光領域７とで生成され
るｐｎ接合に充分深い逆バイアス電圧を印加した状態で
光ｈνが入射すると、該ｐｎ接合に発生した電子がアバ
ランシェ増倍される。In this APD, when light hv is incident on the pn junction formed by the multiplication layer 5 and the light receiving region 7 with a sufficiently deep reverse bias voltage applied, the electrons generated in the pn junction are avalanche multiplied.
現在、このようなＡＰＤを高感度にする為、低雑音化す
る研究・開発が進められている。Currently, research and development is underway to reduce noise in order to make such APDs more sensitive.
このＡＰＤに於ける雑音は、ｐ＋型１ｎＰ受光領域７の
直下に存在するｎ型１ｎＰ増倍層５の一部である増倍領
域でアバランシェ増倍が起きるときに発生する。Noise in this APD is generated when avalanche multiplication occurs in a multiplication region that is a part of the n-type 1nP multiplication layer 5 that exists directly under the p+-type 1nP light-receiving region 7.
通常、前記のような雑音の発生を抑制する為には、前記
増倍領域の不純物濃度を低下させることに依り、ｐｎ接
合に於ける最大電界を低減することが行われている。Normally, in order to suppress the generation of noise as described above, the maximum electric field in the pn junction is reduced by lowering the impurity concentration in the multiplication region.
ＡＰＤを低雑音化する為に前記増倍領域の不純物濃度を
低下させてｐｎ接合を低電界化した場合には、前記増倍
領域で消費される電圧が増大し、全体として著しい耐圧
の上昇、即ち、ブレイク・ダウン電圧の上昇を招来する
ので、ガード・リング効果が損なわれるし、また、動作
電圧が高くなる為、信頼性も悪化することになる。In order to reduce the noise of the APD, when the impurity concentration in the multiplication region is lowered to lower the electric field of the pn junction, the voltage consumed in the multiplication region increases, resulting in a significant increase in breakdown voltage as a whole. That is, this causes an increase in the breakdown voltage, which impairs the guard ring effect, and also increases the operating voltage, which deteriorates reliability.
本発明は、構造に若干の改変を加えるのみで、低雑音で
あって且つ増倍領域のブレイク・ダウン電圧が充分に低
い半導体受光素子を得られるようにする。The present invention makes it possible to obtain a semiconductor light-receiving element with low noise and sufficiently low breakdown voltage in the multiplication region by only making slight modifications to the structure.
本発明一実施例を説明する為の図である第１図を借りて
説明すると、ｐ＋型型光光領域７直下に在る増倍領域が
、記号５Ａで指示されたエネルギ・バンド・ギャップが
１．３４ （ｅＶ）であるｎ型１ｎＰ増倍層５の一部分
と、好ましくはエネルギ・バンド・ギャップが１．１〜
１．３ （ｅＶ）であるｎ型Ｇａ１ｎＡｓＰ増倍層８と
から成っている。Referring to FIG. 1, which is a diagram for explaining one embodiment of the present invention, the multiplication region located directly under the p+ type optical region 7 has an energy band gap indicated by symbol 5A. 1.34 (eV) and a portion of the n-type 1nP multiplication layer 5 whose energy band gap is preferably 1.1 to
1.3 (eV) and an n-type Ga1nAsP multiplication layer 8.
前記手段に依れば、増倍領域には、ＩｎＰ増倍層５に於
ける一部分５Ａの外にＩｎＰ増倍層５が有しているエネ
ルギ・バンド・ギャップよりも小さく且つ１ 〔μｍ〕
帯の光を透過し得るそれを有するＧａ１ｎＡｓＰ増倍層
８が存在している為、その増倍領域に於けるブレイク・
ダウン電圧を低下させることができる。According to the above means, the multiplication region has an energy band gap smaller than the energy band gap that the InP multiplication layer 5 has outside the portion 5A of the InP multiplication layer 5 and 1 [μm].
Since there is a Ga1nAsP multiplication layer 8 that can transmit light in the band, there is a break in the multiplication region.
Down voltage can be reduced.
従って、ＩｎＰ増倍層５に於ける不純物濃度を低下させ
てｐｎ接合を低電界化することに依り、増倍雑音の低減
を図っても、ブレイク・ダウン電圧が上昇してガード・
リング効果が失われるようなことはな（、また、特にＩ
ｎＰ増倍層５の不純物濃度を低下させてｐｎ接合の低電
界化を図るようなことをしなくても、増倍領域が２層に
なっていて厚いので、ｐｎ接合は自然に低電界化され、
低雑音になる。Therefore, even if the multiplication noise is reduced by lowering the impurity concentration in the InP multiplication layer 5 and lowering the electric field of the pn junction, the breakdown voltage increases and the guard
The ring effect will not be lost (and especially if
Even if you do not lower the impurity concentration of the nP multiplication layer 5 to lower the electric field of the pn junction, the multiplication region has two layers and is thick, so the pn junction can naturally lower the electric field. is,
The noise will be low.
第１図は本発明一実施例の要部切断側面図であり、第４
図に関して説明した部分と同部分は同記号で指示しであ
る。FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention, and FIG.
The same parts as those described with respect to the figures are indicated by the same symbols.
本実施例が第４図に見られる従来例と相違する点は、ｐ
＋型型光光領域７直下に在るエネルギ・ハンド・ギャッ
プが１．３４ （ｅＶ）であるｎ型ＩｎＰ増倍層５から
なる増倍領域にエネルギ・バンド・ギヤツブが１．１〜
１．３ （ｅＶ）である厚さ約４０００ Ｃ人〕程度の
ｎ型Ｇａ１ｎＡｓＰ増倍層８を介挿したことである。The difference between this embodiment and the conventional example shown in FIG.
An energy band gap of 1.1 to 1.1 to a multiplication region consisting of an n-type InP multiplication layer 5 with an energy hand gap of 1.34 (eV) located directly below the +-type optical region 7
1.3 (eV) and a thickness of approximately 4,000 C] was inserted.
このようにすると、従来と同様に、ｎ型１ｎＰ増倍層５
の不純物濃度、従って、一部分５Ａのそれを低下させる
ことに依り低雑音化を図った場合であっても、エネルギ
・バンド・ギャップが小さいｎ型ＧａｆｎＡｓＰ増倍層
８が存在していることがら増倍領域の耐圧は小さく維持
することが可能であり、半導体受光素子は正常な動作を
することができる。In this way, as in the conventional case, the n-type 1nP multiplication layer 5
Even if noise reduction is achieved by lowering the impurity concentration of 5A, the impurity concentration of 5A is increased due to the presence of the n-type GafnAsP multiplication layer 8 with a small energy band gap. The breakdown voltage in the double region can be kept low, and the semiconductor light receiving element can operate normally.
また、第４図に見られるような従来例に於ける増倍領域
は、ｐ＋型型光光領域７ｎ型１ｎＰ増倍層５とで生成さ
れるｐｎ接合の下側に在る極薄い範囲にあるが、前記本
発明一実施例に於けるような構成にした場合の増倍領域
は、ｎ型１ｎＰ増倍層５の一部分５Ａとｎ型Ｇａ１ｎＡ
ｓＰ増倍層８とで構成されて厚くなっているので、ｎ型
１ｎＰ増倍層５の不純物濃度を特に低下させな（ても、
ｐｎ接合に於ける電界は自然に低下して増倍雑音も低減
されることになる。In addition, the multiplication region in the conventional example as shown in FIG. However, when configured as in the embodiment of the present invention, the multiplication region consists of a portion 5A of the n-type 1nP multiplication layer 5 and the n-type Ga1nA.
Since it is composed of the sP multiplication layer 8 and is thick, the impurity concentration of the n-type 1nP multiplication layer 5 is not particularly reduced (even if
The electric field at the pn junction will naturally drop and the multiplication noise will also be reduced.
第２図は第１図に関して説明した実施例を測定すること
に依って得られた過剰雑音対増倍率の関係を表す線図で
ある。FIG. 2 is a diagram illustrating the relationship between excess noise and multiplication factor obtained by measuring the embodiment described with respect to FIG.
図では、縦軸には過剰雑音係数Ｆを、横軸には増倍率Ｍ
をそれぞれ採ってあり、また、測定光波長λ＝１．３
Ｃμｍ〕、正孔に対する電子のイオン化率比に＝α／β
〜０．４である。In the figure, the vertical axis represents the excess noise factor F, and the horizontal axis represents the multiplication factor M.
are taken respectively, and the measurement light wavelength λ=1.3
Cμm], the ionization rate ratio of electrons to holes = α/β
~0.4.
図から判るように、増倍率Ｍが１０の場合、過剰雑音係
数は５であり、極めて低い値になっている。As can be seen from the figure, when the multiplication factor M is 10, the excess noise factor is 5, which is an extremely low value.
第３図は同じく第１図に関して説明した実施例を測定す
ることに依って得られた素子耐圧（増倍領域のブレイク
・ダウン電圧）対増倍領域不純物濃度の関係を表す線図
である。FIG. 3 is a diagram showing the relationship between the element breakdown voltage (breakdown voltage of the multiplication region) and the impurity concentration of the multiplication region, which was also obtained by measuring the embodiment described in connection with FIG.
図では、縦軸には素子耐圧を、横軸には増倍領域不純物
濃度をそれぞれ採ってあり、Ａは本発明一実施例の特性
線、Ｂはｎ型Ｇａ１ｎＡｓＰ増倍層がないものの特性線
を示している。In the figure, the vertical axis shows the device breakdown voltage, and the horizontal axis shows the impurity concentration in the multiplication region, where A is the characteristic line of one embodiment of the present invention, and B is the characteristic line without the n-type Ga1nAsP multiplication layer. It shows.
図から判るように、素子耐圧はＧａｌｎＡｓＰ増倍層が
ないもの（特性線Ｂ）に比較すると１５（Ｖ）以上も低
く維持されている。As can be seen from the figure, the device breakdown voltage is maintained lower by more than 15 (V) compared to the device without the GalnAsP multiplication layer (characteristic line B).
第１図に見られる本発明一実施例を製造する工程は第４
図に見られる従来例を製造する場合と比較して殆ど変わ
りなく、唯、ｎ型Ｇａ１ｎＡｓＰ増倍層８を成長させる
工程が余分になるだけである。The process of manufacturing one embodiment of the present invention shown in FIG.
There is almost no difference compared to the case of manufacturing the conventional example shown in the figure, except that the step of growing the n-type Ga1nAsP multiplication layer 8 is added.
即ち、液相エピタキシャル成長（ｌｉｑｕｉｄｐｈａｓ
ｅ ｅｐｉｔａｘｙ：ＬＰＥ）法を適用することに依
り、ｎ＋髪型ＩｎＰ基板ｌ上ｎ型■ｎＰバッファ層２、
エネルギ・バンド・ギャップが０．７ （ｅＶ）である
ｎ型ＱａｌｎＡｓ光吸収層３、エネルギ・バンド・ギャ
ップが０． ９ （ｅ■〕であるｎ型Ｇａ１ｎＡｓ光吸
収層４、ｎ型ＬｎＰ増倍層５、ｎ型Ｇａ［ｎＡｓＰ増倍
層８、ｎ型１ｎＰ増倍層５を順に成長させ、次いで、受
光領域形成予定部分を適当にマスクしてから、エツチン
グ法或いはメルト・バンク法を適用することに依り、表
面からｎ型ＧａＩｎＡｓＰ増倍層８の下側に在るｎ型１
ｎＰ増倍層５の所定深さに到達するメサを形成し、次い
で、メサを形成する為に除去した部分にｎ型１ｎＰガー
ド・リング層を選択成長させ、次いで、拡散法或いはイ
オン注入法など適宜の技法を適用してｐ＋型型光光領域
形成する。That is, liquid phase epitaxial growth (liquidphase epitaxial growth)
By applying the e epitaxy (LPE) method, an n-type nP buffer layer 2 on an n+ hairstyle InP substrate l,
The n-type QalnAs light absorption layer 3 has an energy band gap of 0.7 (eV) and an energy band gap of 0.7 (eV). 9 (e■), an n-type Ga1nAs light absorption layer 4, an n-type LnP multiplication layer 5, an n-type Ga[nAsP multiplication layer 8, and an n-type 1nP multiplication layer 5] are grown in order, and then a light-receiving region is formed. After appropriately masking the planned portion, by applying an etching method or a melt bank method, the n-type 1 under the n-type GaInAsP multiplication layer 8 is removed from the surface.
A mesa reaching a predetermined depth of the nP multiplication layer 5 is formed, and then an n-type 1nP guard ring layer is selectively grown in the portion removed to form the mesa, and then a diffusion method, ion implantation method, etc. A p+ type optical region is formed by applying an appropriate technique.
この後、通常の技法を適用して保護膜や電極を形成して
完成する。Thereafter, a protective film and electrodes are formed using conventional techniques to complete the process.
本発明に依る半導体受光素子では、−導電型受光領域の
直下に形成され所定のエネルギ・ハンド・ギャップを有
する反対導電型増倍層及び該反対導電型増倍層に於ける
エネルギ・バンド・ギャップより小さいそれを有する反
対導電型増倍層を積層して構成された増倍領域を有して
なる構造になっている。In the semiconductor light-receiving device according to the present invention, there is provided a multiplication layer of opposite conductivity type formed immediately below the light-receiving region of conductivity type and having a predetermined energy hand gap, and an energy band gap in the multiplication layer of opposite conductivity type. It has a structure including a multiplication region formed by laminating multiplication layers of opposite conductivity type each having a smaller size.
このような構造を採っていることから、増倍領域の一部
をなすＩｎＰ層の不純物濃度を低減してｐｎ接合に於け
る電界を低下させることに依り低雑音化を図っても、該
ＩｎＰ層よりエネルギ・バンド・ギャップが小さいＧａ
ｌｎＡｓＰ層の存在に依りブレイク・ダウン電圧は低く
維持することができるから、良好なガード・リング効果
を奏することが可能であり、半導体受光素子は常に正常
な動作をする。また、特にＩｎＰ層の不純物濃度を低減
してｐｎ接合に於ける電界を低下させるようなことをし
なくても、実効の増倍領域が従来のものに比較して厚く
なっているので、自然発生的にｐｎ接合は低電界化され
て低雑音にすることができる。Because of this structure, even if noise reduction is achieved by reducing the impurity concentration of the InP layer that forms part of the multiplication region and lowering the electric field at the pn junction, the InP Ga has a smaller energy band gap than the Ga layer.
Since the breakdown voltage can be maintained low due to the presence of the lnAsP layer, a good guard ring effect can be achieved, and the semiconductor photodetector always operates normally. In addition, even without reducing the impurity concentration of the InP layer to lower the electric field at the pn junction, the effective multiplication region is thicker than that of the conventional one, so it can be used naturally. Generatively, the pn junction can have a low electric field and thus low noise.
第１図は本発明一実施例の要部切断側面図、第２図は第
１図に見られる半導体受光素子の過剰雑音係数対増倍率
の関係を示す線図、第３図は同じ（第１図に見られる半
導体受光素子の素子耐圧対増倍領域不純物濃度の関係を
示す線図、第４図は従来例の要部切断側面図をそれぞれ
表している。
図に於いて、■はｎ＋型ｒｎＰ基板、２はｎ型ＩｎＰバ
ッファ層、３はエネルギ・ハンド・ギャップが０．７
（ｅＶ）であるようにしたｎ型ＧａＩｎＡｓ光吸収層、
４はエネルギ・ハンド・ギャップが０．９ （ｅＶ）で
あるようにしたｎ型ＧａＩｎＡｓ光吸収層、５はｎ型１
ｎＰ増倍層、６はｎ型ＩｎＰガード・リング層、７はｐ
”型受光領域、８はｎ型Ｇａ１ｎＡｓＰ増倍層、ｈνは
入射光をそれぞれ示している。
特許出願人 富士通株式会社
代理人弁理士 拍 谷 昭 司
代理人弁理士 渡 邊 弘 −
第１図
第２図
増倍率ＭFIG. 1 is a cross-sectional side view of essential parts of an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between excess noise coefficient and multiplication factor of the semiconductor photodetector shown in FIG. 1, and FIG. Fig. 1 is a diagram showing the relationship between the device breakdown voltage and the impurity concentration in the multiplication region of the semiconductor photodetector, and Fig. 4 is a cross-sectional side view of the main part of the conventional example. Type rnP substrate, 2 is n-type InP buffer layer, 3 is energy hand gap 0.7
(eV), an n-type GaInAs light absorption layer,
4 is an n-type GaInAs light absorption layer with an energy hand gap of 0.9 (eV), 5 is an n-type 1
nP multiplication layer, 6 is n-type InP guard ring layer, 7 is p
" type light-receiving area, 8 indicates an n-type Ga1nAsP multiplication layer, and hν indicates incident light. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Akira Utoya Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 2 Multiplication factor M
Claims (1)
ンド・ギャップを有する反対導電型増倍層及び該反対導
電型増倍層に於けるエネルギ・バンド・ギャップより小
さいそれを有する反対導電型増倍層を積層して構成され
た増倍領域を有してなることを特徴とする半導体受光素
子。An opposite conductivity type multiplication layer formed directly under one conductivity type light-receiving region and having a predetermined energy band gap, and an opposite conductivity type multiplication layer having an energy band gap smaller than that of the opposite conductivity type multiplication layer. A semiconductor light-receiving device characterized by having a multiplication region formed by stacking double layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59274464A JPS61156777A (en) | 1984-12-28 | 1984-12-28 | Semiconductor light-receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59274464A JPS61156777A (en) | 1984-12-28 | 1984-12-28 | Semiconductor light-receiving element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61156777A true JPS61156777A (en) | 1986-07-16 |
Family
ID=17542045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59274464A Pending JPS61156777A (en) | 1984-12-28 | 1984-12-28 | Semiconductor light-receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61156777A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5157473A (en) * | 1990-04-11 | 1992-10-20 | Kabushiki Kaisha Toshiba | Avalanche photodiode having guard ring |
| US5552616A (en) * | 1993-03-19 | 1996-09-03 | Fujitsu Limited | Semiconductor light detecting device with groove |
-
1984
- 1984-12-28 JP JP59274464A patent/JPS61156777A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5157473A (en) * | 1990-04-11 | 1992-10-20 | Kabushiki Kaisha Toshiba | Avalanche photodiode having guard ring |
| US5552616A (en) * | 1993-03-19 | 1996-09-03 | Fujitsu Limited | Semiconductor light detecting device with groove |
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