JPS61156768A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61156768A
JPS61156768A JP28067484A JP28067484A JPS61156768A JP S61156768 A JPS61156768 A JP S61156768A JP 28067484 A JP28067484 A JP 28067484A JP 28067484 A JP28067484 A JP 28067484A JP S61156768 A JPS61156768 A JP S61156768A
Authority
JP
Japan
Prior art keywords
ring
plate
electrode
groove
projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28067484A
Other languages
Japanese (ja)
Inventor
Tsunatoyo Yajima
矢島 維豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP28067484A priority Critical patent/JPS61156768A/en
Publication of JPS61156768A publication Critical patent/JPS61156768A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To make alignment easier by a method wherein rings made of high molecular material are formed of two rings to be assembled together at specified position while one ring and the other ring are provided with projection respectively to be inserted into the recession on the side of holding plate and the side of electrode plate. CONSTITUTION:A groove 17 is made on the side of a circular holding silicon plate 11 within a container while a polyethylene tetrafluoride ring 8 with a projection 81 to be inserted into the groove 17 is fixed to the holding plate 11. Besides, another groove 24 is made on the side of a circular cathode electrode 2 while another polyethylene tetrafluoride ring 9 with another projection 91 to be inserted into the groove 24 is fixed to the holding plate 11. Moreover the rings 8 and 9 may be aligned by means of inserting another projection 92 into a recession 82. In such a constitution, a thyristor element 1 with centrally asymmetrical and complicated electrode shape may be assembled within a shorter time improving the alignment precision.

Description

【発明の詳細な説明】[Detailed description of the invention] 【発明の属する技術分野】[Technical field to which the invention pertains]

本発明は、大口径サイリスタあるいはGTOサイリスタ
など、半導体素体の表面に、中心点に対して非対称の形
状を有する電極が形成され、その電極形状に対して同様
に中心点に対して非対称の形状を有する接続電極板が接
触している半導体装置に関する。
In the present invention, an electrode having an asymmetrical shape with respect to the center point is formed on the surface of a semiconductor element such as a large diameter thyristor or a GTO thyristor, and the electrode shape is also asymmetrical with respect to the center point. The present invention relates to a semiconductor device in which connection electrode plates having a contact electrode plate are in contact with each other.

【従来技術とその問題点】[Prior art and its problems]

第2図は、増幅ゲート構造の平形サイリスタを示し、+
8)図に上面図で示したサイリスクエレメント1は円形
のシリコン板11の下面がモリブデンなどからなる円形
の支持ll112の上にろう付けされており、シリコン
板11の上面にはアルミニ6ムからなる周囲が円形のカ
ソード電極13の中心部に四つの突出部を有する同様に
アルミニウムからなる補助カソード電極14が位置し、
さらにその中心部に円形のやはりアルミニウムからなる
ゲート電極15が存在する。一方、山)図に下面図で示
したカソード電極板2は、中心部に貫通孔21と補助カ
ソード電極14の突出部の輪郭よりやや大きい輪郭を持
つ凹部22が形成されている。補助カソード電極14が
電極板2と接触すると、カソード電極15に短絡される
ため増幅ゲート構造の効果がなくなるので、電極板2と
エレメントlとは補助カソード電極14の上に貫通孔2
1と凹部22が来るように位置合わせして重ねる必要が
ある。この位置合わせは、例えば第3図に示すようにエ
レメント1とカソード電極板2がセラミック環3とそれ
に薄い金属環6を介して結合されるアノード端子4.カ
ソード端子5からなる容器内にポリ四弗化エチレンリン
グ30と共に収容する際、アノード端子4に形成された
ピン穴31と支持板12に形成されたピン穴16にピン
32を挿入し、カソード端子5に形成されたピン穴32
とカソード電極2に形成されたピン穴23にビン34を
挿入することによって行われた。なおゲート電極15に
は、貫通孔21内に絶縁環35と共に収容されるゲート
ばね36を接触させる。しかし、エレメントにおけるピ
ン穴16の位置は、シリコン板11と子5の金属環6と
セラミック環3上の金属板7との溶接は、その都度位置
決めをして行わねばならず非常に手間がかかり、また溶
接の際の位置ずれを防ぐためには非常に大きな注意をは
らう必要があり、量産向きでないという欠点があった。
Figure 2 shows a flat thyristor with an amplification gate structure, +
8) In the silicon element 1 shown in the top view in the figure, the lower surface of a circular silicon plate 11 is brazed onto a circular support 112 made of molybdenum or the like, and the upper surface of the silicon plate 11 is made of aluminum 6 mm. An auxiliary cathode electrode 14 similarly made of aluminum and having four protrusions is located at the center of the cathode electrode 13 having a circular circumference.
Further, in the center thereof, there is a circular gate electrode 15 also made of aluminum. On the other hand, the cathode electrode plate 2 shown in the bottom view in the top view has a through hole 21 and a recess 22 having an outline slightly larger than the outline of the protrusion of the auxiliary cathode electrode 14 in the center. When the auxiliary cathode electrode 14 comes into contact with the electrode plate 2, it is short-circuited to the cathode electrode 15, which eliminates the effect of the amplification gate structure.
It is necessary to align and overlap so that 1 and recess 22 are aligned. This positioning is achieved by, for example, as shown in FIG. 3, an anode terminal 4. The element 1 and the cathode electrode plate 2 are connected to a ceramic ring 3 via a thin metal ring 6. When housing the cathode terminal 5 together with the polytetrafluoroethylene ring 30 in a container, the pin 32 is inserted into the pin hole 31 formed in the anode terminal 4 and the pin hole 16 formed in the support plate 12, and the cathode terminal Pin hole 32 formed in 5
This was done by inserting a bottle 34 into a pin hole 23 formed in the cathode electrode 2. Note that a gate spring 36 housed in the through hole 21 together with the insulating ring 35 is brought into contact with the gate electrode 15 . However, the position of the pin hole 16 in the element must be determined each time welding between the silicon plate 11, the metal ring 6 of the child 5, and the metal plate 7 on the ceramic ring 3, which is very time-consuming. Moreover, it is necessary to take great care to prevent positional deviation during welding, and it has the disadvantage that it is not suitable for mass production.

【発明の目的】[Purpose of the invention]

本発明は、上述の欠点を除去して半導体素体の表面の中
心非対称の形状を有する電極と中心非対称の形状を有す
る接触電極板との位置合わせか、容、器の端子と絶縁体
との固定の際の位置合わせを必要とすることなく精度よ
く行われる半導体装置を提供することを目的とする。
The present invention eliminates the above-mentioned drawbacks and improves alignment between an electrode having a centrally asymmetrical shape on the surface of a semiconductor body and a contact electrode plate having a centrally asymmetrical shape, and alignment between a container, a terminal of a container, and an insulator. It is an object of the present invention to provide a semiconductor device that can be precisely aligned without requiring alignment during fixing.

【発明の要点】[Key points of the invention]

本発明は、絶縁環とそれに結合された両金属端子体とか
らなる容器の中に支持板に固着された半導体素体、その
電極に接触する接続電極板ならびに半導体素体および接
続電極板を囲む絶縁性高分子材料環が収容さるものにお
いて、高分子材料環が互いに所定の相対位置において係
合可能の二つの部分よりなり、その一つの部分は半導体
素体支持板側面に半導体素体固着後形成された凹部に挿
入される凸部を有し、他の一つの部分は接続電極板側面
に形成された凹部に挿入さる凸部を有することによって
上述の目的を達成する。
The present invention surrounds a semiconductor element fixed to a support plate, a connecting electrode plate that contacts the electrodes, and the semiconductor element and the connecting electrode plate in a container consisting of an insulating ring and both metal terminal bodies coupled thereto. In the case where the insulating polymer material ring is housed, the polymer material ring consists of two parts that can be engaged with each other at a predetermined relative position, and one of the parts is attached to the side surface of the semiconductor element support plate after the semiconductor element is fixed. The above object is achieved by having a protrusion inserted into the recess formed in the connecting electrode plate, and the other part having a protrusion inserted into the recess formed on the side surface of the connection electrode plate.

【発明の実施例】[Embodiments of the invention]

第1図は、本発明の一実施例の平形サイリスタを示し、
第3図と共通の部分には同一の符号を付している。セラ
ミック環3とその両端面に固着された金属板7と金属環
6を介して結合されるアノード端子4.カソード端子5
からなる容器の中にサイリスクエレメント1.カソード
電極板2が収容されている0円形支持板11の側面には
直径の両端に溝17が加工されていて、その溝に嵌入す
る突起81を有するポリ四弗化エチレンリング8が取り
付けられ、円形のカソード電極板2の側面には直径の両
端に溝24が加工され、その溝に嵌入する突起91を有
するポリ四弗化エチレンリング9が取り付けられている
。第4図および第5図はリング9および8.の詳細を示
し、リング9は突起91の反対側に突出部92を有し、
リング8の突起81の上部に形成された凹部82に嵌入
することによりリング8および9の両者は位置決めされ
ている。 第1図に示す平形サイリスクの組立は、シリコン板11
を支持板12とアルミニウムを用いてろう付けした後、
シリコン板11の表面の電極パターンに合わせて溝17
を加工し、ポリ四弗化エチレンリング8を突起81によ
り取り付ける。これによりリング8の凹部82はシリコ
ン板11の表面の電極パター加工しておけば、この電極
板に取り付けられるポリ四弗化エチレンリング9の突出
部92は電極板2の凹部のパターンに対して位置決めさ
れる。従って両リング89を凹部82と突出部92によ
り組み合わせることによつて、電極板2の凹部22のパ
ターンをサイリスクエレメントlの補助カソード電極1
4のパターンと正確に位置合わせすることができる。 アノード端子4−およびカソード端子5は、この位置合
わせには無関係となるから、絶縁環3との金属環6.金
属板7との溶接の際には円周方向の位置合わせの必要が
なくなる。
FIG. 1 shows a flat thyristor according to an embodiment of the present invention,
Components common to those in FIG. 3 are given the same reference numerals. An anode terminal 4 connected to the ceramic ring 3 and a metal plate 7 fixed to both end faces thereof via the metal ring 6. Cathode terminal 5
Place the cyrisk element in a container consisting of 1. A groove 17 is machined at both ends of the diameter on the side surface of the circular support plate 11 in which the cathode electrode plate 2 is housed, and a polytetrafluoroethylene ring 8 having a protrusion 81 that fits into the groove is attached. Grooves 24 are machined at both ends of the diameter of the side surface of the circular cathode electrode plate 2, and a polytetrafluoroethylene ring 9 having a protrusion 91 that fits into the groove is attached. 4 and 5 show rings 9 and 8. , the ring 9 has a protrusion 92 on the opposite side of the protrusion 91;
Both rings 8 and 9 are positioned by fitting into a recess 82 formed at the top of a protrusion 81 of ring 8. The assembly of the flat silicon risk shown in FIG.
After brazing with the support plate 12 using aluminum,
Grooves 17 are formed in accordance with the electrode pattern on the surface of the silicon plate 11.
is processed, and a polytetrafluoroethylene ring 8 is attached using a protrusion 81. As a result, if the concave portion 82 of the ring 8 is processed into an electrode pattern on the surface of the silicon plate 11, the protruding portion 92 of the polytetrafluoroethylene ring 9 attached to this electrode plate will correspond to the pattern of the concave portion of the electrode plate 2. Positioned. Therefore, by combining both rings 89 with the recesses 82 and protrusions 92, the pattern of the recesses 22 of the electrode plate 2 can be changed to the auxiliary cathode electrode 1 of the thyrisk element l.
It can be accurately aligned with pattern 4. Since the anode terminal 4- and the cathode terminal 5 are unrelated to this alignment, the metal ring 6- is connected to the insulating ring 3. There is no need for positioning in the circumferential direction when welding with the metal plate 7.

【発明の効果】【Effect of the invention】

本発明によれば、!器内の半導体エレメントとその表面
の電極に接触する接続電極板と容器との間に配置される
絶縁性高分子材料環を部分し、−方の部分はエレメント
の半4体素体支持板と電極パターンに関して位置決めし
て取り付けることができ、他方の部分は接続電極板の形
状に関して位置決めして取り付けることができ、画部分
は位置決めして組合わせることができるので、各部の位
置合わせが容易でかつ確実な作業で行われ、測定器、治
具は一切不要である。このため、中心非対称の複雑な電
極形状を有する増幅ゲート構造のサイリスタの組立て時
間は半減し、位置合わせ精度も±0,2fiから±0.
1 mと半減することができた。
According to the invention! The insulating polymer material ring is placed between the container and the connecting electrode plate that contacts the semiconductor element in the device and the electrode on its surface. The other part can be positioned and attached with respect to the electrode pattern, the other part can be positioned and attached with respect to the shape of the connecting electrode plate, and the image part can be positioned and combined, making it easy to align each part. It is a reliable process, and no measuring instruments or jigs are required. Therefore, the assembly time of a thyristor with an amplification gate structure having a center-asymmetric and complex electrode shape is halved, and the alignment accuracy is improved from ±0.2fi to ±0.2fi.
We were able to reduce the distance by half to 1 m.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の増幅ゲート構造を有する平
形サイリスクの断面図、第2図は増幅ゲート構造サイリ
スクを示し、(Mlはエレメントの上面図、伽)はカソ
ード電極板の下面図、第3図は従来の増幅ゲート構造の
平形サイリスタの断面図、第4図は本発明の一実施例に
おける一方のポリ四弗化エチレンリング、第5図は他方
のポリ四弗化エチレンリングを示し、いずれもtalが
断面図、伽)が平面図である。 l:サイリスクエレメント、11:シリコン板、12テ
支持板、17;溝、2:カソード電極板、22:凹部、
24:溝:3:セラミック環、4ニアノード端子、5:
カソード端子、6:金属環、8,9:ポリ四弗化エチレ
ンリング、81:突起、82:凹部、91:突起、92
:突出部。 フ” 才 1 目 包)(b) t z 日 で3 口 第4図 (b) 75図
FIG. 1 is a cross-sectional view of a flat silice having an amplification gate structure according to an embodiment of the present invention, FIG. 2 shows a silice with an amplification gate structure, and (Ml is a top view of the element, 佽) is a bottom view of a cathode electrode plate. , Fig. 3 is a sectional view of a flat thyristor with a conventional amplification gate structure, Fig. 4 shows one polytetrafluoroethylene ring in an embodiment of the present invention, and Fig. 5 shows the other polytetrafluoroethylene ring. In both cases, tal is a cross-sectional view, and tal is a plan view. l: silice element, 11: silicon plate, 12 support plate, 17: groove, 2: cathode electrode plate, 22: recess,
24: Groove: 3: Ceramic ring, 4 near node terminal, 5:
Cathode terminal, 6: Metal ring, 8, 9: Polytetrafluoroethylene ring, 81: Projection, 82: Recess, 91: Projection, 92
: Protrusion. Figure 4 (b) Figure 75

Claims (1)

【特許請求の範囲】[Claims] 1)絶縁環とそれに結合された両金属端子体とからなる
容器の中に支持板に固着された半導体素体、該半導体素
体表面の電極に接触する接続電極板ならびに半導体素体
および接続電極板を囲む絶縁性高分子材料環が収容され
るものにおいて、高分子材料環が互いに所定の相対位置
において係合可能な二つの部分よりなり、その一つの部
分は半導体素体支持板側面に半導体素体固着後形成され
た凹部に挿入される凸部を有し、他の一つの部分は接続
電極板側面に形成された凹部に挿入される凸部を有する
ことを特徴とする半導体装置。
1) A semiconductor element fixed to a support plate in a container consisting of an insulating ring and both metal terminal bodies bonded thereto, a connecting electrode plate in contact with an electrode on the surface of the semiconductor element, and the semiconductor element and the connecting electrode. In the case where an insulating polymeric material ring surrounding the plate is accommodated, the polymeric material ring consists of two parts that can be engaged with each other at a predetermined relative position, one of which is attached to the side surface of the semiconductor element support plate. 1. A semiconductor device having a convex portion inserted into a concave portion formed after the element body is fixed, and another portion having a convex portion inserted into a concave portion formed on a side surface of a connection electrode plate.
JP28067484A 1984-12-27 1984-12-27 Semiconductor device Pending JPS61156768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28067484A JPS61156768A (en) 1984-12-27 1984-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28067484A JPS61156768A (en) 1984-12-27 1984-12-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61156768A true JPS61156768A (en) 1986-07-16

Family

ID=17628346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28067484A Pending JPS61156768A (en) 1984-12-27 1984-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61156768A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03149880A (en) * 1989-11-06 1991-06-26 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03149880A (en) * 1989-11-06 1991-06-26 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

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