JPS6115448A - Receiver - Google Patents

Abstract

PURPOSE:To detect a signal from a demodulation output under a low S/N by sampling a signal 1-bit by several samples and comparing the bit series with a code from a code generator without forming a bit synchronizing signal. CONSTITUTION:The output of an FSK demodulating circuit 10 is sampled by a sampling device 22 not by signal one bit length but by, e.g., 8 samples. A data outputted from the sampler 22 is inputted sequentially to a shift register 24, 8 data are extracted from the register 24 at the interval of 8 samples and inputted to a comparator 21. The comparator 21 compares a code to be compared and collated every input of one sample with an input signal string and as the result of the comparison, if majority or over is coincident, it is decided that the signal is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a receiving device that can be used for data communication.

Conventional configurations and their problems In recent years, mobile communication services such as pagers and car telephones have become popular. In this mobile communication, a transmitting/receiving device is used that performs data communication to connect a line using an identification number such as a dial number of the own station or a partner station.

A conventional transmitting/receiving device will be described below with reference to the drawings. FIG. 1 is a block diagram of a conventional transmitting/receiving device. In FIG. 1, ■ indicates a transmitting device, and ■ indicates a receiving device. The transmitting device I includes an input device 1, an encoder 2, an FSK modulation circuit 3, a transmitting circuit 4, and a transmitting antenna 6. On the other hand, the receiving device ■ has a receiving antenna 6, a high frequency amplification circuit 7,
It has a frequency conversion circuit 8, an intermediate/frequency amplification circuit 9, an FSK demodulation circuit 1q, a synchronization signal generation circuit 11, a signal detection circuit 12, and an output circuit 13. The operation of the transmitting/receiving device configured as above will be described below. When information is input by operating an input device 1 consisting of a keypad or the like, the encoder 2 generates information corresponding to the input information. The logic signal generated by the encoder 2 is sent to the FS by the modulation circuit 3,
The logic “1”.

The frequency information is converted into frequency information corresponding to "0''. This frequency information is converted to a high frequency by the transmitting circuit 4, amplified, and transmitted as an electromagnetic wave from the transmitting antenna 6. Next, the receiving device (2) will be explained. Receiving antenna 6 is selectively amplified by a high frequency amplification circuit 7, and converted to an intermediate frequency by a frequency conversion circuit 8.The signal converted to this intermediate frequency is further selectively amplified by an intermediate frequency amplification circuit 9.Then, FSK demodulation is performed. The circuit 1o demodulates the FSK modulated signal and outputs it as a logic signal.If there is no modulation signal, the demodulated output converted to logic "1" and logic "0" becomes a random signal appearing due to noise. If there is a signal, a 2-bit synchronization signal is generated in the synchronization signal generation circuit 11, and this synchronization signal is used to generate the signal detection circuit 1.
2, the signal is detected. The operation of the synchronizing signal generating circuit 11 will be further explained using FIG. 2. Figure 2a
sends an information bit after sending one bit of information. By doing this, as shown in Figure 2, on the receiving side, for example, the oscillator 14 with a frequency 16 times that of the bit synchronization signal is activated, and the frequency divider 16 is reset at the falling edge of the start bit. , the signal frequency-divided to 1/16 is used as a bit synchronization signal. A low-pass filter 16 is installed at the signal input to prevent small whisker-like logic signals caused by noise.
Then, when the divider 16 is reset, the timer 17 measures the 1-bit length time so that it will not be reset again due to fluctuations in the input signal, and the reset input of the frequency divider 16 is controlled by the gate 18. This prevents the synchronization signal generation circuit 11 from malfunctioning even if some noise is superimposed in one bit period. Based on the bit synchronization signal obtained in this way, the signal detection circuit 12 detects the signal. FIG. 3 shows a method for detecting this signal. FIG. 3a shows a demodulated signal, and FIG. 3a shows a bit synchronization signal.

In response to the start bit, the synchronization signal generating circuit 11 generates a bit synchronization signal of one cycle with a time length of one bit.

Since the rising edge of this bit synchronous signal is located exactly at the midpoint of one pit of the signal, the signal marked Q of the demodulated signal in FIG. 3a is input at the rising edge of this bit synchronous signal. In this way, the input signal is stored in the shift register 19 in the signal detector 11 as shown in FIG.
A comparator 21 compares the code to see if it matches the code generated by the code generator 2o having a preset code configuration, and if they match, the output device 13 outputs this code.

The transmitting/receiving device configured as described above requires a synchronization signal generation circuit that generates a bit synchronization signal.

In order to generate a synchronization signal for this bit, even if the input signal is in a random state due to noise, it is reset at the falling edge of the signal to create a synchronization signal, so when the signal is input, the start bit can be accurately determined. In order to capture this, the S/N ratio after demodulation must be guaranteed to some extent.

In addition, when generating a bit synchronization signal, the fall of the signal within the time length of one bit is controlled by the gate 18, but if the signal fluctuates due to noise at the rise of this bit synchronization signal, the input signal may be affected. This will result in the wrong data being imported. Therefore, the level of information decoding was reduced, and there was a limit to the distance that could be communicated.

OBJECTS OF THE INVENTION An object of the present invention is to provide a reception method that enables signal detection from demodulated output even under a low S/N ratio without creating a bit synchronization signal, and that can reduce false detections due to noise. The goal is to provide equipment.

Structure of the Invention A receiving device according to the present invention includes a sampler that samples a demodulated logic signal at certain time intervals to determine whether the received signal matches a logic signal with a preset code configuration; A clock generator that gives sampling timing to a sampler, a shift register that inputs a logic signal from the sampler that is sampled at the timing of the clock generator, and a code having a preset code configuration. The code generator includes a code generator that generates a code, and a comparator that compares the value of the shift register with the code generated by the code generator. According to this configuration, a plurality of samples are sampled at equal intervals from the time length of one bit of the signal, one sample is taken out at an interval for each time length of one bit of the signal, and this bit sequence is sent to the code generator by the comparator. By comparing the code generated by This makes it possible to detect signals. Since there is no need to generate a bit synchronization signal, it is possible to detect signals even from demodulated signals with a low S/N ratio, and therefore the communicable distance can be extended. In addition, since multiple samples are taken from a 1-bit signal and all of them are tested, even if short-term noise exists, its influence is small, and false detection of signals due to noise can be reduced. .

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 6 shows a block diagram of a receiving device in an embodiment of the present invention. The receiving device includes a receiving antenna 6, a high frequency amplification circuit 7, a frequency conversion circuit 8, an intermediate frequency amplification circuit 9,
FIK demodulation circuit 10, sampler 22, clock generator 2
3. Shift register 24, code generator 20, comparator 21
, has an output device 13. Components having the same functions as the conventional examples shown in FIGS. 1 and 4 are given the same numbers.

The operation of the receiving apparatus according to an embodiment of the present invention configured as described above will be described below. Receiving antenna 6
The operations from F8 to demodulation circuit 1o are the same as in the conventional case. The logic signal output from the FSK demodulation circuit 1° is sampled by a sampler 22. The timing of this sampling is determined by the clock generator 23. The clock of the clock generator 23 allows several samples to be sampled in one pit length of the signal. For example, if eight samples are to be sampled for one bit length of the signal, the sampler 22 will output data at eight samples/bit.

The data that can be output from the sampler 22 is sequentially input to the shift register 24. If one signal word has 8 bits, eight pieces of data are taken out from the shift register 24 at eight sample intervals and input to the comparator 21. The comparator 21 compares the code to be compared and matched with the input signal string every time one sample is input. The code waiting on the receiving side,
For example, when you input your own station's identification number, in order to check whether it is a signal sequence that happened to be generated by noise, for example, 8 samples per 1 bit of the signal are sampled, so you can compare them. If the results match more than half, it is determined that a signal has been detected. This will be explained in more detail using FIG. 6. Assume that the code currently waiting is ``10101010'', and that this is output from the code generator 2o. Assume that a certain sample is input to the shift register 19, and when it is output to the comparator 21 every 8 samples, it is a waiting signal sequence. At this time, the sample at position tl in FIG. 6 can be regarded as the a priori sample value of the final bit of the code to be verified. The comparator 21 cycles back and compares the edges 8 times until the sample at position 11 is transferred to position t2. For example, if the signal sequence is present over the majority, it is determined that a signal has been detected. judge. If a signal can be detected in this way, it will be meaningless to compare the data remaining in this shift register 19 with the data that is subsequently inputted with the next code.
The data in the shift register 19 will not be updated until all the data in the shift register 19 is discarded or until the data at position t2 is shifted to position t5 at this timing. If it is shifted to the position of t5, at this time, the 8-san sample of tl will be shifted to the position of t2, and then the sample will be shifted to the position of t4.
Comparison and verification are repeated eight times until the sample at t6 reaches t6, and the signal is detected. These operations are repeated to detect all signals. Once the timing of the signal can be detected as described above, the signal detection is repeated after waiting for the data in the shift register 19 to be updated to new data. Here, if a shift of one sample occurs due to noise etc. when detecting the first data, and if this is used as the signal detection timing to continue updating the shift register 19, all signal detection times until the last signal is detected. In this case, a deviation of one sample is propagated.

In order to prevent this initial deviation due to noise from affecting the next signal detection, the shift register 19 should be used during the period from the first signal detection to the data replacement for the next signal detection. It is sufficient to perform the comparison operation several times before and after. That is, the timing deviation can be absorbed by increasing the eight times of comparison and verification by one or two times each before and after. The results of the comparison and verification are outputted through the output devices 1 and 3.

As described above, according to the present embodiment, the demodulated signal is sampled in multiple samples corresponding to the length of one bit of the signal, and the entire signal is compared and inspected while being shifted little by little in time. Signal synchronization is uniform because the most probable one is selected, such as being able to detect a sign with a majority of the bits indicating whether it indicates “'1” or logical “0°”. Since the signal is detected while looking at the entire input data, there is no need to generate a bit synchronization signal, and the S/N is low.
Signals can also be detected from the demodulated output of the ratio. Also,
Since erroneous signal detection due to noise is reduced, communication distance can be extended.

In this embodiment, the code generated by the code generator 2Q has been described as having a preset code structure, but if one word of the signal is made up of 8 bits, for example, using 8 bits, only one It is also possible to specify that the MSB of the 8 bits must always be logic "1". In short, when transmitting information, it is only necessary to set as many numbers as necessary depending on the type of information; for example, a pager only needs to have an identification number for calling its own station.

Next, other embodiments of the present invention will be described with reference to the drawings. The present embodiment is further configured to enable signal detection even with a demodulated output having a low modulation ratio. FIG. 7 shows an example of a transmission signal in another embodiment of the present invention. FIG. 7a shows a transmission signal that repeatedly sends the same signal so that the reception side can add the received signals. FIG. 7 shows one period of a signal that is repeatedly sent. This one-cycle signal contains a synchronization signal so that synchronization can be achieved on the receiving side after addition processing. FIG. 8 shows a block diagram of a receiving device in another embodiment of the present invention. Blocks with the same functions as those in the embodiment of FIG. 6 are given the same numbers. The receiving device in this embodiment includes a receiving antenna 6, a high frequency amplification circuit 7, a frequency conversion circuit 8, an intermediate frequency amplification circuit 9, and an ysx demodulation circuit 1o.
, MU/D converter 25, storage device 26 for addition, adder 2
7. Timing generator 28 for addition, switch 29 for switching storage device for addition, level determiner 30. It has a shift register group 31, a shift register changeover switch 32, a synchronization signal detector 33, a comparator changeover switch 34, a comparator 21, a code generator 2o, and an output device 13. Here, an adder 27, a timing generator 28 for addition, a switch 29 for switching the storage device for addition, and a level determination device 30.
．． The shift register group 31, shift register changeover switch 32, synchronization signal detector 33, comparator changeover switch 34, comparator 21, and code generator 2o are configured by a microcomputer 36. Next, the operation will be explained. The operation from the receiving antenna 6 to the FSX demodulation circuit 10 is the same as in the conventional case. In order to add the outputs of the FSX demodulation circuit 1o, the A/D converter 25 converts them into digital quantities. Addition is performed in duplicate as shown in FIG. 9 so that it can be determined no matter what timing the signal is input. In FIG. 9, a is an input signal sequence and the same signal is sent repeatedly. Here, the number of repetitions is assumed to be N times. A timing generator 28 generates timing for addition that matches one cycle of the signal. This timing is shown in FIG.

FIGS. 9c to 9f show how the adder 27 performs addition with 76% overlap, for example, in accordance with this timing. The number of additions is N, which is the same as the number of times the signal is sent out. FIG. are shown respectively. By adding the same input signals overlappingly in this way, it becomes possible to detect the signal from the result of addition somewhere, even if the start of the signal is not known. In order to take out the data in the storage device 28 that has been added N times in the adder 27, the switch 32 is turned on. The added result is converted into a logic signal by a level determiner 30 via a switch 29. This logic signal is the result of addition of data of one word length each in the storage device 26, and is transferred by a shift register changeover switch 32 to a shift register group 31 in which shift registers of one word length are arranged in parallel as many times as the number of samples in one bit. I can't switch, so I input one sample at a time. If 1 bit is 8 samples and 1 word is 8 bits, the shift register group 31 consists of 8 8-pit shift registers arranged in parallel.

In order to compare the data in each shift register with the data in the code generator 20 using the comparator 21, the sending timing on the transmitting side and the addition timing do not necessarily match, so each shift register The data within is not necessarily arranged in the order sent by the sender. Therefore, the data in this shift register group 31 must be arranged in the order in which it was sent on the transmitting side. Since redundant addition processing is performed so that it can be determined no matter what timing the signal is input, the signal is composed of a synchronization signal and information for synchronizing on the receiving side, as shown in FIG. Therefore,
After the received data is transferred to the shift register group 31,
In order to find this synchronization signal, the shift register group 31
The data in the shift register is rotated by one bit as shown in FIG. 1, and the synchronizing signal is checked by the synchronizing signal detector 33 from the state of the shift register as shown in FIG. 1o.

If this synchronization signal does not exist in the shift register, or if two or more synchronization signals exist, it can be determined that it is due to noise or that the addition period spans two signals. If the synchronization signal can be detected by the synchronization signal detector 33 in the shift register group 31, the remaining information data is compared with the code of the code generator 20 by the comparator 21 as shown in FIG. All shift registers are sequentially inspected using the shift register changeover switch 34,
The most probable result is output from the output device 13.

By performing redundant addition processing, there is no need to independently provide a signal indicating the start of the transmission signal, and white noise can be suppressed in proportion to the square root of the number of additions.
Furthermore, the communicable distance can be expanded.

Effects of the Invention As is clear from the above explanation, the present invention takes a plurality of samples at equal intervals from the time of one bit of the signal, creates data for one word of the signal at intervals of one bit time length, and generates a code by generating data for one word of the signal. The system performs a comparative test on the entire signal while shifting the code slightly in time with the code generated by the receiver, and selects and outputs the most likely code, so there is no need to create a synchronization signal for each bit on the receiving side. It is also resistant to noise and can detect signals even from demodulated signals with a low S/N ratio. As a result, the communication distance can be dramatically extended.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional transmitting/receiving device, Fig. 2 is a functional explanatory diagram of the synchronizing signal generation circuit of the same device, Fig. 3 is an explanatory diagram of a signal detection method using a synchronizing signal of the same device, and Fig. 4 is the same. FIG. 6 is a block diagram of a receiving device in an embodiment of the present invention; FIG. 6 is a functional diagram of a shift register and a comparator in an embodiment of the present invention; FIG. The figure is an explanatory diagram of a transmission signal in another embodiment of the present invention,
FIG. 8 is a block diagram of a receiving device in another embodiment of the present invention, FIG. 9 is a functional explanatory diagram of an adder in another embodiment of the present invention, and FIG. 10 is a shift diagram in another embodiment of the present invention. FIG. 2 is a functional explanatory diagram of a register and a synchronization signal detector. 1...Input device, 2...Encoder, 3
...FSK modulation circuit, 4...Transmission circuit, 6...Transmission antenna, 6...Reception antenna, 7...High frequency amplification circuit , 8...
・Frequency conversion circuit, 9... intermediate frequency amplification circuit,
1o...FSK demodulation circuit, 11...Synchronization signal generation circuit, 12...Signal detection circuit, 13
...... Output device 4.14... Oscillator, 1
6... Frequency divider, 16... Low pass filter, 17... Timer, 18... Gate, 19... Shift Register, 20...
...Code generator, 21...Comparator, 22...
... Sampling device, 23 ... Parameter four-wheel generator, 24
...°・Shift register, 26...Mom/D
Converter, 26...Storage device, 27...
Adder, 28... Timing generator, 29...
...Additional storage device changeover switch, 3o...
...Level judger, 31...Shift register,
32...Shift register changeover switch, 3
3... Synchronous signal detector, 34... Comparator switch, 36... Microcomputer - 0 Agent's name Patent attorney Toshio Nakao and 1 other person 1st plan 1111-------------■----J L-11-----------------Person 111''■ Figure 5 7G Section 9th drawing Listen

Claims (1)

[Claims] a sampler that samples a demodulated logic signal at certain fixed time intervals; a clock generator that provides sampling timing to the sampler; and a sampler that samples at the timing of the clock generator. a shift register that inputs a logic signal from the device, a code generator that generates a code with a preset code configuration, and a comparator that compares the value of the shift register with the code generated by the code generator. A plurality of samples are sampled at equal intervals from the 1-bit time length of the signal, one sample is taken out at an interval of each 1-bit time length, and a comparator compares the sample with the code generated by the code generator. , the signal is detected by shifting this by one sample within each bit and repeating the comparison and inspection for all samples to check whether the code matches the code of a preset code configuration. Features of the receiving device.