JPS61154310A

JPS61154310A - Delay circuit

Info

Publication number: JPS61154310A
Application number: JP59273844A
Authority: JP
Inventors: Taiji Ishiai; 泰司石合
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1984-12-27
Filing date: 1984-12-27
Publication date: 1986-07-14

Abstract

PURPOSE:To make the trailing time delay unchanged against a short pulse width input and a high frequency input by connecting a base of a transistor (TR) to an inverting circuit input via a resistor and providing a capacitor charged by the TR between an output of the inverse circuit and common. CONSTITUTION:When the level of the input of the inverter 7 goes to L, a TR 8 is turned on and the capacitor 18 is charged rapidly via the TR 8. When the level of the input of the inverter 7 goes to H, the TR 8 is turned off and the potential at an output terminal 9 falls down along with the discharge curve having a time constant decided by the capacitor 10 and a resistor 11. Since the capacitor is charged momentarily by the TR, the trailing time delay is unchanged against the short pulse width input or the high frequency input.

Description

【発明の詳細な説明】（産業上の利用分野）本発明は、パルスの立ち下りの時間遅れを作る遅延回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a delay circuit that creates a time delay in the falling edge of a pulse.

（従来例の構成とその問題点）第１図に、従来例として、コンデンサと抵抗器を用いた
遅延回路を示す。同図において、インバータ１への入力
がロウレベルのとき、インバータ１の出力はハイレベル
になり、抵抗器２、ダイオード３を介してコンデンサ４
が充電される。インバータ１の入力がハイレベルになる
と、インバータ１の出力はローレベルになるが、出力端
５の電位はコンデンサ４と抵抗器６によってきまる時定
数の放電曲線で降下する。これにより出力端５の電位が
、論理回路のスレシュホルトレベル以下となるまでに、
時間遅れが発生するにの従来の回路では、インバータ１への入力のロウレベル
の時間が短くなると、コンデンサ４が十分充電されなく
なり１時間遅れが短くなる。さらに、ローレベルの時間
が短くなると、出力端５の電位がスレシュホルトレベル
を越えないということが生じる。このように、入力の周
波数が高くなった場合には、遅延回路として十分機能し
なくなる欠点があった。(Constitution of Conventional Example and Its Problems) FIG. 1 shows a delay circuit using a capacitor and a resistor as a conventional example. In the figure, when the input to inverter 1 is at low level, the output of inverter 1 is at high level and is connected to capacitor 4 via resistor 2 and diode 3.
is charged. When the input of the inverter 1 becomes a high level, the output of the inverter 1 becomes a low level, but the potential of the output terminal 5 falls according to a discharge curve with a time constant determined by the capacitor 4 and the resistor 6. As a result, by the time the potential at the output terminal 5 becomes below the threshold level of the logic circuit,
In the conventional circuit in which a time delay occurs, when the time period during which the input to the inverter 1 is at a low level becomes shorter, the capacitor 4 is not sufficiently charged, and the one hour delay becomes shorter. Furthermore, if the low level time becomes shorter, the potential at the output end 5 will not exceed the threshold level. As described above, when the input frequency becomes high, there is a drawback that the delay circuit does not function sufficiently.

（発明の目的）本発明の目的は、従来の欠点を解消し、短いパルス幅の
入力や、周波数の高い入力に対しても。(Objective of the Invention) The object of the present invention is to eliminate the drawbacks of the conventional technology, and to apply it even to short pulse width inputs and high frequency inputs.

時間遅れの変わらない遅延回路を提供することである。It is an object of the present invention to provide a delay circuit whose time delay does not change.

（発明の構成）本発明の遅延回路は、反転回路の入力に抵抗器を介して
、トランジスタのベースが接続され、反転回路の出力と
接地間に、前記トランジスタで充電されるコンデンサが
接続されたものである。(Structure of the Invention) In the delay circuit of the present invention, a base of a transistor is connected to an input of an inverting circuit via a resistor, and a capacitor charged by the transistor is connected between an output of the inverting circuit and ground. It is something.

（実施例の説明）本発明の一実施例を第２図に基づいて説明する。(Explanation of Examples) An embodiment of the present invention will be described based on FIG. 2.

第２図は本発明の回路図である。同図において、インバ
ータ７への入力がローレベルになると、トランジスタ８
がオン状態になり、コンデンサ１０はトランジスタ８を
介して急速に充電される。インバータ７への入力がハイ
レベルになると、トランジスタ８はオフ状態になり、出
力端９の電位は、コンデンサ１０と抵抗器１１とで決ま
る時定数の放電曲線に従って降下する。すなわちコンデ
ンサの充電がトランジスタによって瞬時に行なわれるた
め。FIG. 2 is a circuit diagram of the present invention. In the figure, when the input to inverter 7 becomes low level, transistor 8
is turned on, and capacitor 10 is rapidly charged via transistor 8. When the input to the inverter 7 becomes high level, the transistor 8 is turned off, and the potential at the output terminal 9 falls according to a discharge curve with a time constant determined by the capacitor 10 and the resistor 11. In other words, the capacitor is charged instantly by the transistor.

短いパルス幅の入力や、高い周波数の入力に対しても、
立ち下りの時間遅れが変わらなくなる。Even for short pulse width inputs and high frequency inputs,
The fall time delay will not change.

（発明の効果）本発明によれば、短いパルス幅の入力や、高い周波数の
入力に対しても、立ち下りの時間遅れ量が変わらない反
転回路が得られる効果がある。(Effects of the Invention) According to the present invention, an inverting circuit can be obtained in which the falling time delay amount does not change even when inputting a short pulse width or inputting a high frequency.

[Brief explanation of drawings]

第１図は従来の反転遅延回路の回路図、第２図は本発明
の一実施例による遅延回路の回路図である。１．７・・・インバータ、２，６．１１・・・抵抗器、
３・・・ダイオード、４，１０・・・コンデンサ、５，
９・・・出力端、８・・・トランジスタ。FIG. 1 is a circuit diagram of a conventional inverting delay circuit, and FIG. 2 is a circuit diagram of a delay circuit according to an embodiment of the present invention. 1.7...Inverter, 2,6.11...Resistor,
3... Diode, 4, 10... Capacitor, 5,
9...Output end, 8...Transistor.

Claims

[Claims]

A delay circuit characterized in that a base of a transistor is connected to an input of an inverting circuit via a resistor, and a capacitor charged by the transistor is connected between an output of the inverting circuit and ground.