JPS61154266A - Graphic processing circuit - Google Patents

Abstract

PURPOSE:To output a smeared graphic form in a short time by print or display by outputting an OR signal between a read signal of the 1st picture memory and a read signal of the 2nd picture memory obtained via a toggle circuit. CONSTITUTION:The 1st picture memory 5 storing a line drawing (b) except the smeared part as binary data at each picture element, the 2nd picture memory 6 storing a linear drawing (c) representing the profile of the smeared part as binary data at each picture element, and converters 7, 8 converting the data at, e.g., 16 picture elements read in parallel from the 1st picture memory 5 and the 2nd picture memory 6 respectively in parallel to serial data and outputting the result are provided. Further, a JK flip-flop 9 used as a toggle circuit inverting the output by using a read signal obtained through the read of the picture memory 6 by raster scanning and an OR circuit 10 outputting the OR between the read signal obtained from the 1st picture memory 5 by raster scanning and the output of the toggle circuit 9 are provided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is characterized in that one figure is divided into 1" and "" for each pixel arranged in a grid pattern.
The present invention relates to a graphic processing circuit included in a graphic output device that outputs a binary signal of 0'' by binary display or printing.

For example, various electronic computers are equipped with so-called dot-type printing devices such as laser printers, which are used to output not only single characters but also complex figures such as bar graphs and pie charts. The easiest way to make a part stand out is to fill in the area and print it.

In such a case, the line figure to be printed, the outline of the range to be filled, etc. are provided to the figure output device as output information.

Note that this information is obtained by line analysis of the outline of a line figure or a filled range (hereinafter, it is given as starting point coordinates and ending point coordinates for each line segment, that is, vector data).

At this time, it is desirable that the filled figure be output in a short time.

[Conventional technology]

FIG. 4 is a schematic block diagram of a conventional example of a graphic processing circuit provided in a laser printer for the above-mentioned purpose.

In the figure, ■ is generally referred to as a bitmap memory, and stores print information to be finally printed as a dot pattern on the recording paper as binary data of "1" or "0" for each dot (pixel) 9 For example, 4096 x It is a 4096 bit image memory (RMM).

2 is a first unit, that is, a central processing unit (CPU); 3 is a first writing unit that converts a line figure given in the form of vector data from the central processing unit 2 into binary data and writes it into the image memory 1; , 4 is a second writing unit that performs writing to fill in the filling range given from the central processing bag W2.

With the above configuration, the print information given from the central processing unit 2 is simply developed on the image memory 1 in the form of a dot pattern to be finally printed on the recording paper, and then read by raster scanning. For example, it is output (printed) on recording paper as a black and white dot pattern with a density of 240 dots per inch.

[Problem that the invention seeks to solve]

In the configuration described above, after the line figure is written on the image memory 1 by the first writing rest section 3, the image memory 1 is accessed again and writing for filling is performed, so it takes a long time to fill. Therefore, there is a problem in that it takes a long time to print.

[Means for solving problems]

The graphic processing circuit according to the present invention processes the first graphic 2 times for each pixel.
A first image memory that stores the figure as value data, a second image memory that stores the second figure as binary data for each pixel, and a read signal obtained by reading the second image memory by raster scanning. The above problem can be solved by comprising a toggle circuit that inverts the output, and an OR circuit that outputs the logical sum of the read signal obtained by reading the first image memory by raster scanning and the output of the toggle circuit. This is an attempt to eliminate this point.

[Effect]

That is, two image memories are provided, and a line figure is written in the first image memory, and a line figure indicating the outline of the filled area is written in the second image memory.

The first image memory and the second image memory are simultaneously read by raster scanning using the same readout signal, and the read signal of the first image memory and the read signal of the second image memory obtained through the toggle circuit are read. It is designed to output the logical sum of 1 image memory, and there is no need to write data for filling in one image memory. Therefore, figures with filling can be output in a short time by printing or displaying. .

〔Example〕

The gist of the present invention will be specifically explained below by referring to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG.
The first image memory (BMM-1) stores value data.
), 6 is a second image memory (BR
M-2), 7 and 8 are converters (P/S) that serially convert data for each 16 pixels read in parallel from the first image memory 5 and second image memory 6, respectively, and output the serial data. , 9 is a JK flip-flop (JK-FF) used as a toggle circuit that inverts the output according to a read signal obtained by reading the second image memory 6 by raster scanning, and 10 is a JK flip-flop (JK-FF) used for raster scanning the first image memory 5. This is a logical sum circuit that outputs the logical sum of the read signal obtained by scanning and the output of the toggle circuit 9.

To explain the case of printing a figure (hunting indicates a filled area) as shown in FIG. A line shape with the filled part removed from the shape,
In addition, as shown in FIG. 2(e), the second image memory 6 contains
Stores each line figure indicating the outline of the filled area.

At this time, by accessing the first image memory 5 and the second image memory 6 using exactly the same address, when writing the line figure in FIG. 2 (bl) to the first image memory 5, the common The line figure of part fc) can be written into the second image memory 6 at the same time.

When the line figures written in the first image memory 5 and the second image memory 6 as described above are simultaneously read by raster scanning, bit string data synchronized with the clock signal CL is generated from the converter 7 and the converter 8, respectively. is output.

FIG. 3 is a diagram illustrating the relationship between the storage content (a) of the second image memory 6 and the output (bl) of the JK flip-flop 9. In fal of the same figure, each square represents a pixel.

The hunted portions indicate "1" pixels forming the line figure, and the white sections indicate O'' pixels forming the background.

The output of the converter 8 is commonly input to the J terminal and the terminal of the JK flip-flop 9, and when the converter 8 outputs bit string data indicated by the arrow N in FIG. 3 (11), for example, The output of the JK flip-flop 9 changes like a mountain.

The OR circuit 10 outputs the read signal of the first image memory 5 in accordance with the output of the JK Frisopfromp 8 when the output is "0" (ranges of ■ and ■ in FIG. 3(b)). and the range of H in the “1” state (Fig. 3 mountain)
Then, the output signal of the IK flip-flop 9 is output.

It is supplied to the output of the OR circuit 10 and a printing section (not shown),
A figure such as the 21st m (al) is printed on the recording paper by the printing unit.

〔Effect of the invention〕

As described above, according to the present invention, it is not necessary to write all the data for filling into the image memory, so a figure with a filled portion can be output in a short time.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention. FIG. 2 and FIG. 3 are explanatory diagrams of the same embodiment. FIG. 4 shows a schematic block diagram of a conventional example. In the figure. 2 is a central processing unit, and 5 is a first image memory. 6 is a second image memory, and 9 is a JK flip-flop. 10 is an OR circuit Sakae 1 Kaya 2nd (cL) (column CC) Spear 3E Tea 4〆

Claims (1)

[Claims] A first image memory stores the first figure as binary data for each pixel, a second image memory stores the second figure as binary data for each pixel, and a raster image memory stores the second figure as binary data for each pixel. a toggle circuit that inverts an output according to a read signal obtained by reading the first image memory by raster scanning; and an OR circuit that outputs a logical sum of the read signal obtained by reading the first image memory by raster scanning and the output of the toggle circuit. A graphic processing circuit comprising: