JPS60140387A - Graphic generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to a graphic generator, and more particularly to a graphic generator that uses a small page memory and has multiple functions through switching use.

Prior Art In thermal plotters, electrostatic pronotators, laser printers, etc. that print in a raster scan format, and CI (i) display devices that display in a raster scan format,
In order to output data, it is common to arrange the data two-dimensionally to form columns and rows, which correspond to main scanning (horizontal) and sub-scanning (vertical) of raster scanning.

By the way, when creating new characters by overlaying two pieces of text information, inserting text information into an image, or inserting text information into a figure such as a graph, it is necessary to overlay the image information. page memory.”
I need to get into it. To implement such an overlay, it is necessary to prepare multiple pieces of output data for the same 1ζC, and if two-level overlay is allowed at any position, the page memory will eventually be 2 Double the capacity is required.

On the other hand, l/2 line spacing (
IIJP Line Iecd), PLU (
Partial Line Up), P L l) (
Since functions such as Part :al Inc Down require doubling the resolution in the row direction, the capacity of the page memory also needs to be doubled.

Some CItT display devices use bitmap memory as page memory to control character display positions in dot units, but as the dot density increases, such as in laser printers, the capacity of the bitmap memory increases. Since it becomes extremely large, it is disadvantageous in terms of both cost and processing speed. Therefore, it is required to minimize the capacity of the page memory and provide highly functional control.

FIG. 1 is a block diagram of a conventional raster scan type graphic generator. In FIG. 1, circuitry for converting basic character codes into character patterns and obtaining raster scan data is shown. Raster scanning consists of a horizontal direction (main scanning) synchronization signal (dot clock) and a vertical direction (sub-scanning) synchronization signal (line clock). When the main scanning clock reaches a predetermined number of dots, the sub-scanning When the scanning clock advances by one line and the sub-scanning clock reaches a predetermined line, scanning of one screen ends.

As shown in FIG. 2, characters (sentences) are stored in the page memory 1 in advance in page units via a character code conversion circuit 8. However, in the page memory 1, the storage start address of the character (graphic) pattern memory 2 that corresponds to the character (graphic) code is stored as an internal code. Character pattern memory 2 stores characters (graphics) as shown in FIG. 3 in the form of a dot matrix.

The dot counter 6 is driven by the main scanning clock and controls the address a in the width (height) direction of the character matrix.
When a predetermined number of dots in the character width are completed, the character direction address counter is counted up. The character direction address counter 4 controls the character address b of the page memory l, and when the main scanning line ends, the character direction address counter 4 controls the character address b of the page memory l.
The counter 6 is reset to the initial state.

The line counter 7 is driven by the sub-scanning clock and controls the address C in the height and width directions of the character matrixff1.
tl L When a predetermined number of lines of character height are completed, the row direction address counter 5 is counted up. Row direction at 1/s counter 5 is page memory 1
Controls the 0th row address d. Since the first address of the character matrix is stored in page memory 1 specified by the character direction address and the row direction address, the character pattern is created using this output data C, character width address a, and character height address C. - Obtain the pattern data f of the storage unit of the character matrix from the memory 2, convert it to raster data g in the parallel-to-serial conversion circuit 3, and output it.

Since characters are arranged in the page memory 1 on a character-by-character and line-by-line basis, control of character arrangement is limited. In particular, recently, printers have been providing character spacing control (
Printing of provo/digital space characters, alignment at the end of the line), control of line spacing (half line feed, PLU/PLD expression), overprinting of characters, etc. are required. Such functionality is not supported by traditional page memory mapping.
Also, laser printers perform printing operations.゛1
Since the printing operation position cannot be stopped within the range of a page, the graphic generation device tends to be complicated and expensive.

The present inventor has proposed printing of proborn space characters,
Alternatively, in order to provide the end-of-line alignment function, the dot matrix is made into a small matrix at the basic 11'L position that controls the character width direction, and one character is formed by an integer multiple of the basic 111th position, and the page memory is also basic. A method of mapping in units was proposed earlier (Il'f Application 1986-1.
No. 86622 to Patent Application No. 186625, 1984, 41]
(see book).

In addition, for overlapping printing of characters, two character codes are stored at the same character position in the page memory, and the page memory, character pattern, and
Access the memory twice and write χ to the two character codes.
Wait for the corresponding character pattern, and calculate the logical sum of the two as a raster
proposed a method for dealing with data (Patent Application 1983-
(Refer to store number 33091).

Also, half line feed (II L F), and P L U
/PLD expression can be handled using the same concept as overprinting of characters, but in order to realize both functions, the page memory configuration has to be twice as large, resulting in higher costs.

Purpose The purpose of the present invention is to solve such conventional problems by providing a high-performance raster scan having an overlay function, a 1/2 line feed function, etc. without increasing the page memory capacity. An object of the present invention is to provide a shape generator.

composition Hereinafter, the configuration of the present invention will be explained using examples.

FIG. 4 is a block diagram of a graphic generator showing an embodiment of the present invention.

The device shown in FIG. 4 differs from the conventional device shown in FIG. 1 by: 1. fru point &:
r, % row direction address color/ri and line non-counter are provided, two each, and an address selection circuit 12, 14 for selecting one of these two, a count control circuit 16, and a memory access timing. In the engineering diagram, a circuit 15, a page memory output selection circuit 9, a character pattern output register 10, and an OR circuit 17 are newly provided.
The first graphic (character) code and the second graphic (character) code can be stored in the same character position.

FIG. 5 is a bit 41'4 diagram of one word of the page memory of FIG.

As shown in Figure 5, the first figure code (
Bits 0 to 7) and a second graphic code (bits 8 to 15) are stored, and both constitute 2 bytes (1 word).

Line counters 7, 3 and row direction address counters 5, 11 are each provided in two sets: main and sub.
The main counters 7 and 5 perform the same operations as conventional ones, and the sub counters 13 and 11 perform the same operation as the main counter 7.5 when overlapping printing is controlled by the count control circuit 15.
In addition, in the case of half line feed fli control, 1. It operates to count with a delay of 2 lines. These switches are selected by a selection signal input to the count control circuit 16. Within one output operation of one rask scan,
First, as the first access, the output of main rank 7゜5 is selected by the address selection circuit 14.12, and the page
The first graphic code is selected by the page memory output selection circuit 9 for the graphic code supplied to the memory 1 and the character pattern memory 2 and read from the page memory l to i:I, and this is sent to the character pattern memory 2. Give it as the address. That is, first, in FIG.
The byte data becomes the address of character pattern memory 2.

The character pattern data read from the character pattern memory 2 is temporarily held in the character pattern output register l○. The first access is to page memory 1
' and the access time of the character pattern memory 2.
controlled by

Subsequently, the second access is executed and the sub counters 13 and 11 are stored in page memory 1 and character pattern memory 2.
The second graphic code (bits 8 to 15 in FIG. 5) is read from the page memory 1 and given to the character pattern memory 2 as the start address. The character pattern data read from the character pattern memory 2 and the first character pattern data read last time and temporarily stored in the output 1/register 10 are logically ORed and subjected to parallel-to-serial conversion. Sent to circuit 3. The parallel-to-serial conversion circuit 3 converts the overlaid notation data into serial data and outputs it as raster data g.

In addition, in the case of half-line feed control, when the normal number of lines is read out from the character pattern memory 2 (after the turn data is temporarily stored in the output register 10, the turn data is moved downward by 1/2 lines) The shifted characters, patterns, and data are read out, and a logical OR is performed at the position 111 shifted by 1/2 line.

In this way, in a printer, it is almost impossible to use all the functions at the same time, so the page memo IJ
By switching and using the information in page memory 1' as necessary, a highly functional printer can be realized without increasing the capacity of page memory 1'.

In addition, in the example, a rask scanning type printer (laser
printer, thermal printer, etc.), but
Of course, it is also applicable to the raster scanning type CRT display device 1"σ.

Effects As explained above, according to the present invention, two graphic codes are stored in the same character position in the page memory, so that the page overlay function that repeatedly uses one page data ( ii) Character overlapping printing function that prints one character overlapping another character, (1
ii) P necessary for expressing scientific formulas etc. by shifting the line position by half a line
The LU7PLD printing function etc. can be selectively obtained, and moreover, it can be realized without increasing the capacity of the page memory.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional raster scan format graphic generator, Figure 2 is a diagram of data stored in the page memory in Figure 1, and Figure 3 is stored in the character pattern memory in Figure 1. FIG. 4 is a block diagram of a rask scanning type figure generator showing one embodiment of the present invention, and FIG. 5 is a diagram of one word data stored in the page memory of FIG. It is a bit structure diagram of data. 1: Page memory, 2: Character pattern memory, 3:
Parallel-to-serial conversion circuit, 4 Two-character direction address counter, 5
．． il: Row direction address counter, 6: Dot counter, 7. 13 Ni line counter, 12, 14 Ni address selection circuit, 1 every 2 count control times? S.15:
Memory access timing circuit. Patent applicant Ricoh Co., Ltd. − Representative patent attorney Masatoshi Isori

Claims (3)

[Claims] (1) It has a page memory that stores code information in units of one page and a pattern memory that stores graphic information corresponding to the code information, and the page memory and pattern memory are scanned by rask scanning. In a graphic generator that outputs graphic information by giving it as an address the information obtained by counting the synchronization signals of , two pieces of code information are stored at the same address. Temporarily stores the first graphic information read from the pattern memory in the first 1 access, using the page memory to store and one code information output from the page memory as part of the address. a register for storing the information; and a circuit for calculating the logical sum of the first graphic information held in the register and the second graphic information read out from the pattern memory in a second access using the other code information. A figure generator characterized by: (2) The pattern memory is updated by the row address from the first row address generation circuit and the row address from the second row address generation circuit, which is updated 1/2 row later than the row address. 2. A graphic generating device according to claim 1, wherein the graphic generating device is accessed. (3) The page memory outputs a first graphic code using the output of the first row address generation circuit as an address, and then outputs a second graphic code using the output of the second row address generation circuit as an address. When outputting, the output of the first row address generation circuit is used as the address, and the first. 2. The graphic generation device according to claim 1, wherein one of the two second graphic codes is selected.