JPS61154145A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the occurrence of the defects in an active element region and to reduce the probability of attachment of dust extremely, by forming a gate oxide film at the earliest stage of the manufacturing processes. CONSTITUTION:A gate osioxide film 12 is formed. Then a gate electrode 16 and an arsenic ion implanted layer 18, which is to become source and drain regions, are formed. Thereafter selective oxidation is performed. Thus a part of a polycrystalline film, which is deposited when the gate oxide film 16 is formed, is converted into a thermal oxide film 21. Element isolation is provided in this way. This method is different from the conventional method, in which an active element is exposed and formed after many processes. Crystal detects do not occur in the active element region and attachment of dust can be avoided. Therefore the troubles due to these causes can be reduced extremely.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for improving element isolation technology of a MoS type semiconductor device and reducing the occurrence of crystal defects in the element active region. It depends.

[Technical background of the invention and its problems]

Conventionally, as a method for isolating elements of an MO8 type integrated circuit, element active regions (output, drain, channel regions)
A method is adopted in which the periphery of the device is limited by an insulating film for isolation between devices, the device active region is exposed, and then a gate oxide film, a gate electrode, and source and drain regions are formed.

A typical method is the so-called selective oxidation method. Hereinafter, the case of manufacturing a MOS transistor using this method will be explained with reference to FIGS. 3(a) to 3(f).

First, for example, a thermal oxide film 2 is formed on the surface of a P-type silicon substrate 1, and then a silicon nitride film 3 is deposited on the entire surface (as shown in FIG. 3(a)).

Next, a portion of the silicon nitride film 3 is selectively etched away by photolithography to form a silicon nitride film pattern 3' corresponding to the device active region.

Subsequently, using this silicon nitride film pattern 3- as a mask, boron ions for preventing inversion are implanted to form a boron ion-implanted layer 4 (as shown in FIG. 4B). Next, thermal oxidation is performed using the silicon nitride pattern 3' as an oxidation-resistant mask to form a field oxide film 5. At the same time, boron in the boron ion-implanted layer 4 is activated to form a P-type field reversal prevention layer 6 (FIG. 3(C)).
(Illustrated).

Next, the silicon nitride pattern 3' and the thermal oxide film 2 thereunder are removed by etching to expose the active region of the device (as shown in FIG. 4D). Subsequently, thermal oxidation is performed to form a gate oxide film 7 on the surface of the element active region. Subsequently, a polycrystalline silicon film is deposited on the entire surface, impurities are introduced to lower the resistance, and then patterning is performed to form the gate electrode 8 (as shown in FIG. 2(e)). Next, using the gate electrode 8 as a mask, ions of, for example, arsenic are implanted, and then annealing is performed to form N+ type source and drain regions 9 and 10, thereby manufacturing a MOS transistor (as shown in FIG. 3(f)). These techniques have been used in many MO8 type integrated circuits in the past.

Incidentally, in recent years, with the increasing integration of chips, there is a strong demand for high reliability for each individual element.

That is, when a crystal defect occurs or dust or the like adheres to an element active region, the electrical characteristics of the individual element often deteriorate. In the case of memories, etc., redundant elements are often built in to provide alternative functions in the event that the element that should be used is defective, so reduced reliability is not so much of a problem. On the other hand, in highly integrated logic elements or two-dimensional image elements, it is difficult to create extra elements, so if one individual element becomes defective, the entire chip becomes defective. There is a problem.

The above-mentioned crystal defects occur when an oxidation process is performed with contaminants attached to the device active region during the manufacturing process, and interstitial silicon generated in the oxidation process precipitates with the contaminants as nuclei. There are many things. Therefore, it is desirable to perform the oxidation process at a stage where the substrate silicon in the element active region is exposed less frequently. This situation also applies to defects caused by particulate dust, and it is desirable that the number of times the substrate silicon in the element active region is exposed is small. However, the above-mentioned figure 3(a)
In the method shown in ~(f), after many manufacturing steps, the device active region is exposed and gate oxidation is performed, so when applied to the manufacturing of highly integrated logic devices and two-dimensional image devices, the yield is low. There was a problem of lowering the .

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned separation point, and reduces defects caused by defects in the device active region or dust that adheres during the manufacturing process, and enables highly integrated MO8 type integrated circuits. The purpose is to provide a manufacturing method with high yield.

[Summary of the invention]

The method for manufacturing a semiconductor device of the present invention includes a step of forming a gate oxide film on the surface of a semiconductor substrate of a first conductivity type, and then depositing a semiconductor layer (for example, polycrystalline silicon group) on the entire surface, and a part of the semiconductor layer. A second conductive type is formed by selectively etching away and forming a gate electrode and other semiconductor layer patterns, and ion-implanting a second conductive type impurity using the gate electrode and other semiconductor layer patterns as a mask. a step of forming an oxidation-resistant film pattern on the insulating film corresponding to the gate electrode and the source and drain regions after depositing an insulating film on the entire surface; The present invention is characterized by comprising a step of performing thermal oxidation using the oxidizable film pattern as a mask, and selectively converting the semiconductor layer pattern into an oxide film to perform element isolation.

According to such a method, the gate oxide film is formed in the earliest manufacturing process, and after the gate electrode, source, drain i region, etc. are formed, a part of the semiconductor layer deposited when forming the gate electrode is formed. Since the oxide film for element isolation is formed using the
The probability of dust adhesion is extremely reduced. therefore,
A high manufacturing yield can be obtained even when manufacturing highly integrated logic circuits, two-dimensional image elements, and the like.

[Embodiments of the invention]

Examples of the method of the present invention will be described below with reference to FIGS. 1(a) to (f) and FIG. 2.

First, a P-type silicon substrate 11 with a surface crystal orientation (100) and a diameter of 4 inches was thermally oxidized in an oxygen atmosphere, and a gate oxide film 12 with a thickness of 600 mm was formed on the surface. Next, L
After a polycrystalline silicon film 13 having a thickness of 1,500 thick was deposited over the entire surface by the PCVD method, phosphorus was doped into the polycrystalline silicon film 13 using POCl2 as a diffusion source. Subsequently, a photoresist pattern 14 is formed on the polycrystalline silicon film 13 corresponding to the element active region, and then B+ ions are implanted to prevent inversion using the photoresist pattern 14 as a mask, and boron ions are implanted into the substrate 11. layer 1
5 (as shown in FIG. 1(a)). Subsequently, after removing the photoresist pattern 14, a photoresist pattern (not shown) is formed on areas other than those corresponding to the source and drain formation regions, and then using this as a mask, the polycrystalline silicon film 13 is patterned to form a gate electrode. 16
and other polycrystalline silicon film patterns 17 were formed. This polycrystalline silicon film pattern 17 will be converted into an oxide film for element isolation in a later step.

Subsequently, after removing the photoresist pattern, As+ ions were implanted using the gate electrode 16 and the polycrystalline silicon film pattern 17 as masks to form an arsenic ion implantation layer 18 in the substrate 11 (see FIG. ).

Next, a CVD oxide film 19 with a thickness of 1,500 yen was deposited on the entire surface. Next, a film thickness of 1000 was applied to the entire surface using the CVD method.
After the silicon nitride film was deposited, patterning was performed by photolithography to form a silicon nitride film pattern 20 only on the active region of the device (as shown in FIG. 4(d)). Continuing,
Heat treatment was performed at 1000° C. in an oxygen atmosphere using the silicon nitride film pattern 20 as an oxidation-resistant mask. Through this step, the polycrystalline silicon film pattern 17 was oxidized through the CVD oxide film 19 and converted into thermal oxidation 1121, thereby achieving device isolation. At the same time, impurities in the arsenic ion implantation layer 18 and the poron ion implantation layer 15 were activated, and N+ type source and drain regions 22 and 23 were formed, as well as a P− type field inversion prevention layer 24. Next, the silicon nitride training pattern 20
was removed (as shown in Figure (e)).

Next, a contact hole was formed by selectively etching a portion of the CvD oxide film 19 and gate oxide film 12. Subsequently, an A° C.-8i film was deposited on the entire surface and then patterned to form a gate wiring 25, a source wiring 26, and a drain wiring 27. In addition, wiring 25.26.2
7 has a circuit configuration in which 10,000 FETs are arranged in parallel (as shown in FIG. 1(f) and FIG. 2).

According to such a method, gate oxidation It! is performed in the step of FIG. 1(a). 12 and further FIGS. 1(b) and (C)
After forming the arsenic ion-implanted layer 18 that will become the gate electrode 16, source and drain regions in the process, the gate oxide film 16 is selectively oxidized in the process shown in FIG.
A part of the polycrystalline silicon film deposited during formation is converted into a thermal oxide film 21 for element isolation. Therefore, unlike conventional methods, the device active region is not exposed and oxidized after going through many processes, and the occurrence of defects due to crystal defects and dust adhesion in the device active region is significantly reduced. be able to.

When actually manufacturing a device as shown in Figure 2, 1
If a crystal defect occurs in even one of the ten thousand elements in the channel region under the gate electrode, a short mode will occur and leakage current will increase when the gate voltage is set within the threshold voltage.

Taking these things into consideration, the short-circuits when the device shown in FIG. 2 is manufactured using the method of the above embodiment and the conventional method (comparative example) shown in FIGS. The table below shows the results of investigating the percentage of non-defective products that do not enter the mode. In addition,
This test evaluates the condition of the wafer and the clean room for the occurrence of crystal defects.

In both methods, to eliminate the influence of dust level,
The operation of manufacturing the devices shown in FIG. 2 on 20 wafers was performed three times during the same period.

As is clear from the above table, it can be seen that the method of the present invention can stably reduce short mode defects in the device active region.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, it is possible to reduce defects caused by defects in the device active region or dust attached during the manufacturing process, and to manufacture highly integrated MO8 type integrated circuits at a high yield. It is.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) show examples of the present invention. Figure 2 is a schematic circuit diagram of a MOS device manufactured for comparative testing, and Figures 3 (a) to (f) are cross-sectional views showing a method for manufacturing a MO8 type semiconductor device. It is a sectional view showing a manufacturing method. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Gate oxide film, 13... Polycrystalline silicon film, 14... Photoresist pattern, 15... Boron ion implantation layer, 16...
・Gate N pole, 17... polycrystalline silicon film pattern,
18... Arsenic ion implantation layer, 19... CVD oxide film, 20... Silicon nitride film pattern, 21... Thermal oxide film, 22.23... -N+ type source, drain region, 2
4... P- type field inversion prevention layer, 25... Gate wiring, 26... Source wiring, 27... Drain wiring. Applicant's representative Patent attorney Takehiko Suzue 1st m! 1 Figure 1 q Figure 2 Figure 3 Figure 3

Claims (1)

[Claims] After forming a gate oxide film on the surface of a first conductivity type semiconductor substrate, a step of depositing a semiconductor layer on the entire surface and selectively etching away a part of the semiconductor layer to form a gate electrode and other semiconductor layer patterns. a step of forming source and drain regions of a second conductivity type by ion-implanting impurities of a second conductivity type using the gate electrode and other semiconductor layer patterns as masks; and a step of depositing an insulating film over the entire surface. After that, there is a step of forming an oxidation-resistant film pattern on the insulating film corresponding to the gate electrode and the source and drain regions, and thermal oxidation is performed using the oxidation-resistant film pattern as a mask to form the semiconductor layer pattern. 1. A method of manufacturing a semiconductor device, comprising a step of selectively converting into an oxide film to perform element isolation.