JPS61154086A - Semiconductor temperature sensor - Google Patents

Semiconductor temperature sensor

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Publication number
JPS61154086A
JPS61154086A JP59277542A JP27754284A JPS61154086A JP S61154086 A JPS61154086 A JP S61154086A JP 59277542 A JP59277542 A JP 59277542A JP 27754284 A JP27754284 A JP 27754284A JP S61154086 A JPS61154086 A JP S61154086A
Authority
JP
Japan
Prior art keywords
compound semiconductor
fet
temperature
substrate
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59277542A
Other languages
Japanese (ja)
Inventor
Tsukasa Onodera
司 小野寺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59277542A priority Critical patent/JPS61154086A/en
Publication of JPS61154086A publication Critical patent/JPS61154086A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor temperature sensor having high sensivity by coating the surface of a compound semiconductor substrate, to which a field-effect transistor is formed, with an insulating material film having a thermal expansion coefficient different from a compound semiconductor in the substrate. CONSTITUTION:The title sensor detects a temperature in such a manner that a FET forming region on a compound semiconductor substrate consisting of GaAs, etc. is coated with a material having a thermal expansion coefficient different from the compound semiconductor substrate, stress depending upon a temperature is generated and the change of carrier concentration due to piezoelectric polarization generated as the result of the generation of stress is utilized. That is, a FET in which currents vary is shaped onto a GaAs(100) face as an n channel FET, the direction of channel length, the direction of drain currents, is formed conformed to the direction of the arrow, and approximately the whole region and the peripheral region of a region in which the FET 3 is shaped is coated with an SiO2 film 2 having thickness of approximately 1mum. Since the film 2 generates stressin the GaAs substrate 1 by utilizing a difference between thermal expansion coefficients, it is desirable that thickness thereof is increased comparatively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は温度検出に使用される半導体装置に関するもの
であり、特に化合物半導体に形成された電界効果トラン
ジスタ(以下、PETと略記)の熱歪による特性変化を
利用する温度センサに関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device used for temperature detection, and in particular to thermal distortion of a field effect transistor (hereinafter abbreviated as PET) formed in a compound semiconductor. The present invention relates to a temperature sensor that utilizes characteristic changes due to

温度を検出するセンサの種類は多様であるが、半導体材
料の熱特性を利用する半導体温度センサは、温度情報を
電気信号として出力するので機器制御用に広く用いられ
ている。
Although there are various types of sensors that detect temperature, semiconductor temperature sensors that utilize the thermal properties of semiconductor materials are widely used for equipment control because they output temperature information as electrical signals.

〔従来の技術と発明が解決しようとする問題点〕従来の
半導体温度センサは、半導体基板上に形成した抵抗素子
の抵抗値の変化や、トランジスタ素子の飽和電流の変化
を介して温度を検知するものが多い、原理的には半導体
基板内で熱的に励起されるキャリヤの濃度や、その易動
度の温度依存性を利用している。
[Prior art and problems to be solved by the invention] Conventional semiconductor temperature sensors detect temperature through changes in the resistance value of resistance elements formed on semiconductor substrates and changes in the saturation current of transistor elements. In principle, many of them utilize the concentration of thermally excited carriers within a semiconductor substrate and the temperature dependence of their mobility.

検知感度向上のために素子の形状や材料の選択等に工夫
が加えられているが、改善の度合には限界がある。
In order to improve detection sensitivity, improvements have been made to the shape of the element and the selection of materials, but there are limits to the degree of improvement.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は特許請求の範囲の項に記された本発明の装
置によって解決されるが、本発明は、後出の実施例によ
って要約すると、砒化ガリウム(GaAs)等の化合物
半導体基板上のFET形成領域を該化合物半導体基板と
は熱膨張係数の異なる材料で被覆して温度に依存する応
力を発生せしめ、その結果生ずる圧電分極によるキャリ
ヤ濃度の変化を利用して温度を検出する装置である。
The above-mentioned problems are solved by the device of the present invention as set forth in the claims, but the present invention can be summarized by the embodiments described below. This device covers the formation region with a material having a coefficient of thermal expansion different from that of the compound semiconductor substrate to generate temperature-dependent stress, and detects temperature by utilizing the resulting change in carrier concentration due to piezoelectric polarization.

〔作用〕[Effect]

化合物半導体結晶は外力による弾性変形を受けると圧電
分極を生ずる。このため化合物半導体基板内のキャリヤ
濃度は見掛は上皮化し、FETの特性は基板に加わる外
力の影響を受ける0本発明はこの現象を利用しており、
化学気相成長法(CVD法)等によって基板上に堆積し
た絶縁膜中の残留応力による基板表面の弾性変形を介し
て生ずる圧電分極を利用するものである。
Compound semiconductor crystals generate piezoelectric polarization when subjected to elastic deformation due to external force. For this reason, the carrier concentration within the compound semiconductor substrate appears to be epithelialized, and the characteristics of the FET are affected by external forces applied to the substrate.The present invention utilizes this phenomenon.
It utilizes piezoelectric polarization generated through elastic deformation of the substrate surface due to residual stress in an insulating film deposited on the substrate by chemical vapor deposition (CVD) or the like.

この絶縁膜中の残留応力はその堆積条件及び温度に依存
し、次式で表される。
The residual stress in this insulating film depends on its deposition conditions and temperature, and is expressed by the following equation.

σ=σ五十(α、−αr) A (T−Ta)ここで、
σは成る温度Tに於ける応力値、σえは堆積状B(温度
T4)での真性応力値、α1.α。
σ = σ50 (α, -αr) A (T-Ta) where,
σ is the stress value at the temperature T, σ is the true stress value at the stacked state B (temperature T4), α1. α.

は夫々基板及び絶縁膜の熱膨張係数、Aは定数である。are the thermal expansion coefficients of the substrate and the insulating film, respectively, and A is a constant.

一般に室温付近と300〜500℃で堆積した時の応力
値を較べると、高温の方がより大きな値をとる場合が多
い。
Generally, when stress values are compared when deposited near room temperature and at 300 to 500°C, the stress values are often larger at higher temperatures.

圧電分極及びそのFETの特性への影響は、化合物半導
体基板の結晶方位に依存している。例えば、GaAsの
(100)面基板上にドレイン電流を(011)方向に
流す向きにFETを形成し、基板に対して圧縮応力を加
えるような残留応力を持つ絶縁膜(例えばSing)で
被覆すると、FETのチャネル領域には正の電荷が誘起
される。このため、FETをnチャネルとした場合ドレ
イン電流は減少し、pチャネルとした場合ドレイン電流
は逆に増加する。またドレイン電流を(OIT)方向と
した場合、或いは基板に対し引張応力を加えるような残
留応力を持つ絶縁膜(例えばS iN 11)を用いた
場合、チャネル領域に誘起される電荷は負となる。
Piezoelectric polarization and its effect on FET characteristics depend on the crystal orientation of the compound semiconductor substrate. For example, if an FET is formed on a GaAs (100)-plane substrate with the drain current flowing in the (011) direction, and it is covered with an insulating film (for example, Sing) that has residual stress that applies compressive stress to the substrate. , positive charges are induced in the channel region of the FET. Therefore, when the FET is made into an n-channel, the drain current decreases, and when the FET is made into a p-channel, the drain current increases. Furthermore, if the drain current is in the (OIT) direction, or if an insulating film (e.g. SiN 11) with residual stress that applies tensile stress to the substrate is used, the charge induced in the channel region will be negative. .

ところで、熱励起によるキャリヤ濃度は高温はど多くな
り、易動度は若干減少する傾向を持つので、結果として
トランジスタ素子の電流値は増加する。従って圧電分極
によってチャネル領域の多数キャリヤが増大する方向に
FETを形成すれば、圧電分極によるキャリヤ濃度の増
減と、温度変化によるキャリヤ濃度の増減とが同方向に
生ずるように構成されるので、温度の変化幅に対する出
力の変化幅がより大となる。即ち、温度センサの感度を
向上させることが出来る。
Incidentally, the carrier concentration due to thermal excitation increases at high temperatures, and the mobility tends to decrease slightly, resulting in an increase in the current value of the transistor element. Therefore, if an FET is formed in the direction in which the majority carriers in the channel region increase due to piezoelectric polarization, the carrier concentration due to piezoelectric polarization increases and decreases in the same direction as the carrier concentration due to temperature changes. The range of change in output becomes larger relative to the range of change in . That is, the sensitivity of the temperature sensor can be improved.

〔実施例〕〔Example〕

〜は本発明の実施例の構造を示す平面図及び断面図であ
る。
- are a plan view and a sectional view showing the structure of an embodiment of the present invention.

本実施例に於いては、電流変化を発生ずる素子であるF
ETは、平面図(a)とそのx−x ’断面図である図
(blに示される構造を持つ、該FETはGaAs  
(10G)面上にnチャネルFETとして形成されてお
り、チャネル長方向即ちドレイン電流の方向は図(a)
に示すように(01丁〕方向に合わせて形成され、該F
ET3が形成された領域の略全域及びその周辺領域は1
μm程度の厚さを持つSing膜2で覆われている。該
皮膜は熱膨張係数の差を利用してGaAs基板l基板力
を生ぜしめるものであるから厚さを比較的大としておく
ことが望ましい、かかる構造が温度検知に効果を有する
所以を以下に述べる。
In this embodiment, F, which is an element that generates a current change,
The ET has the structure shown in the top view (a) and its x-x' cross-sectional view (bl), and the FET is made of GaAs.
It is formed as an n-channel FET on the (10G) plane, and the channel length direction, that is, the drain current direction is shown in Figure (a).
As shown in (01 block) direction, the F
Approximately the entire area where ET3 is formed and the surrounding area are 1
It is covered with a Sing film 2 having a thickness of about μm. Since this film generates a substrate force on the GaAs substrate by utilizing the difference in thermal expansion coefficient, it is desirable to make the film relatively thick.The reason why such a structure is effective for temperature detection will be described below. .

上述の如く、ドレイン電流を(OIT)方向に流すよう
形成したFETをS i Oを膜で被覆するとチャネル
内には圧電分極によって負電荷が誘起され、その温度変
化は熱励起によるキャリヤの増減と同じ傾向となる、従
って電流値の温度変化は圧電分極を利用しない従来型の
ものに比較して大きくなり、高感度の温度センサが実現
することになる。
As mentioned above, when a FET formed so that the drain current flows in the (OIT) direction is coated with a SiO film, negative charges are induced in the channel by piezoelectric polarization, and the temperature change is caused by an increase or decrease in carriers due to thermal excitation. The same tendency occurs, and therefore, the temperature change in current value becomes larger compared to a conventional type that does not utilize piezoelectric polarization, and a highly sensitive temperature sensor is realized.

本発明に於いて温度感応素子として用いられるGaAs
FET3は、ゲート長ll1m程度のショットキバリヤ
ゲートを有するFET(以下、MESFETと略記)で
あり、これの製造には、イオン注入及びアニールによる
チャネル領域4の形成後高耐熱合金であるタングステン
シリサイド(WSi)等でゲート電極5を形成し、再度
イオン注入及びアニールによりソース、ドレインN域6
.7を形成し、A u G e / A u層を蒸着合
金化することによってソース、ドレイン電極8.9を形
成する従来のセルファライン型のMESFET製造法が
、何隻不都合なしに適用される。
GaAs used as a temperature sensitive element in the present invention
The FET 3 is an FET (hereinafter abbreviated as MESFET) having a Schottky barrier gate with a gate length of approximately 11 m, and is manufactured using tungsten silicide (WSi), a highly heat-resistant alloy, after forming the channel region 4 by ion implantation and annealing. ) etc. to form the gate electrode 5, and then ion implantation and annealing again to form the source and drain N regions 6.
.. 7 and forming the source and drain electrodes 8.9 by depositing and alloying the AuGe/Au layers can be applied without any disadvantage.

通常のFETと相違するのは、絶縁被覆であるSiO□
膜2の形成方法であって、該皮膜はFETを形成した後
、基板の温度を約500℃に上げ、CVD法によって約
1μmの厚さに被着形成される。これは既述したように
、熱歪による電流変化を有効に発生させるためのもので
あるから、この観点からは形成温度を可能な限り高くし
、より大きな応力を発生させる方が良いことになるが、
形成温度が高すぎるとGaAs基板/ゲート電極界面反
応によるシロットキバリャの破壊や、再拡散によるチャ
ネル領域の不純物の異常増加などの不都合が生ずる。5
00℃という値は、111mのS i Otを堆積する
のに要する約10分間の高温状態で、かかる不都合が生
じない上限の温度に近いものである。
What is different from normal FETs is the insulating coating of SiO□
The method for forming the film 2 is that after forming the FET, the temperature of the substrate is raised to about 500° C., and the film is deposited to a thickness of about 1 μm by CVD. As mentioned above, this is to effectively generate current changes due to thermal strain, so from this point of view it is better to raise the formation temperature as high as possible and generate larger stress. but,
If the formation temperature is too high, disadvantages such as destruction of sirotchivalry due to GaAs substrate/gate electrode interface reaction and abnormal increase of impurities in the channel region due to re-diffusion will occur. 5
The value of 00° C. is close to the upper temperature limit at which such disadvantages do not occur in the high temperature state for about 10 minutes required to deposit 111 m of S i Ot.

本実施例では、GaAs  (100)面基板上にnチ
ャネルMESFETを形成しているが、これをpチャネ
ルとしてドレイン電流方向を(011)方向と平行にし
たり、絶縁膜としてS i N *を用いても同様の効
果を得ることが可能であり、製造方法もセルファライン
型に限るものではない、また、(110)、(111)
面等の基板を用いて同様の効果を有する温度センサを形
成することも可能である。
In this example, an n-channel MESFET is formed on a GaAs (100)-plane substrate, but this can be made into a p-channel with the drain current direction parallel to the (011) direction, or SiN* can be used as an insulating film. It is possible to obtain the same effect with any method, and the manufacturing method is not limited to the Selfaline type.
It is also possible to form a temperature sensor with a similar effect using a substrate such as a surface.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明によって従来装置より高感度
の半導体温度センサが実現することになる。
As explained above, the present invention realizes a semiconductor temperature sensor with higher sensitivity than conventional devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のセンサの構造を示す平面図及び断面図
であって、 図に於いて lはGaAs基板 2は厚いS i Ox膜 3はシッットキバリャFET
FIG. 1 is a plan view and a cross-sectional view showing the structure of a sensor according to the present invention, in which l indicates a GaAs substrate 2 is a thick SiOx film 3 and a Schitt Kibarya FET.

Claims (3)

【特許請求の範囲】[Claims] (1)電界効果トランジスタが形成された化合物半導体
基板面が、該化合物半導体と異なる熱膨張係数を持つ絶
縁材料膜によって被覆されていることを特徴とする半導
体温度センサ。
(1) A semiconductor temperature sensor characterized in that a compound semiconductor substrate surface on which a field effect transistor is formed is covered with an insulating material film having a coefficient of thermal expansion different from that of the compound semiconductor.
(2)前記絶縁膜材料中の残留応力によって前記化合物
半導体基板内に生ずる応力により、前記電界効果トラン
ジスタのチャネル領域の多数キャリヤ濃度を増大させる
極性の圧電分極が誘起される如く形成されていることを
特徴とする特許請求の範囲第1項記載の半導体温度セン
サ。
(2) The structure is formed so that stress generated in the compound semiconductor substrate due to residual stress in the insulating film material induces piezoelectric polarization that increases the majority carrier concentration in the channel region of the field effect transistor. A semiconductor temperature sensor according to claim 1, characterized in that:
(3)前記化合物半導体が砒化ガリウムであることを特
徴とする特許請求の範囲第2項記載の半導体温度センサ
(3) The semiconductor temperature sensor according to claim 2, wherein the compound semiconductor is gallium arsenide.
JP59277542A 1984-12-26 1984-12-26 Semiconductor temperature sensor Pending JPS61154086A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59277542A JPS61154086A (en) 1984-12-26 1984-12-26 Semiconductor temperature sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59277542A JPS61154086A (en) 1984-12-26 1984-12-26 Semiconductor temperature sensor

Publications (1)

Publication Number Publication Date
JPS61154086A true JPS61154086A (en) 1986-07-12

Family

ID=17584995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59277542A Pending JPS61154086A (en) 1984-12-26 1984-12-26 Semiconductor temperature sensor

Country Status (1)

Country Link
JP (1) JPS61154086A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06155323A (en) * 1992-11-19 1994-06-03 Zojirushi Chain Block Kk Lever type wind-up traction machine
JPH06155326A (en) * 1992-11-19 1994-06-03 Zojirushi Chain Block Kk Hoist/traction machine
JP2010266441A (en) * 2009-05-13 2010-11-25 Lsi Corp Electronic pressure sensing device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06155323A (en) * 1992-11-19 1994-06-03 Zojirushi Chain Block Kk Lever type wind-up traction machine
JPH06155326A (en) * 1992-11-19 1994-06-03 Zojirushi Chain Block Kk Hoist/traction machine
JP2010266441A (en) * 2009-05-13 2010-11-25 Lsi Corp Electronic pressure sensing device

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