JPS6115244A - Microprocessor system - Google Patents

Abstract

PURPOSE:To attain detailed mapping in an address space by storing a partial copy of a mapping table of a memory control unit in a gate table register and retrieving said copy by an address on an external bus. CONSTITUTION:When a certain address is sent onto an external address bus 18, an external bus interface part 14 uses this external address to retrieve a table of a gate table register 13. Then the part 14 uses the corresponding output information to decide whether the external address is set within the own port or not and decides the start or inhibition for exchange of information to the outside. With such memory address control, the detailed mapping operation is possible by setting the memory address of the register 13. At the same time, the regsiter 13 can be rewritten at any time by software. The writing actions are carried out simultaneously for both a memory control unit MMU12 and the register 13 with use of the same data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprocessor system connected to an external bus and in which address space is selectively allocated within the system.

[Technical background of the invention and its problems]

Conventionally, in a system in which a plurality of dates each equipped with a microprocessor are connected to an external bus, an address management mechanism as shown in FIG. 2 has been provided.

That is, in Figure 2, 1 to 6 are darts (≠
i), 1 is a microprocessor (μMP), and 2 is an MMU (memory management unit). 3 is the self-board connected to external bus 7.8 (
i) is an address setting switch that determines the address; 4 is an external bus interface unit that matches the internal buses 5, 6 of the microprocessor and external buses 7, 8;

In this configuration, the address of the mate is determined by the address setting switch 'f-3. The address setting switch 3 monitors the upper address of the external bus 8 through the external bus interface 4, and when it is the same as the value set on the switch 3, instructs the external nozzle interface section 4 to open the gate. do.

However, in such a conventional configuration, the address of each gate connected to the external bus 7.8 is fixed, and to change this, the address must be reset by operating a switch. The operation became very complicated and one board could only have one continuous fixed memory space.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and allows address setting,
It is an object of the present invention to provide a microprocessor system in which addresses can be changed easily and with high reliability, and more detailed memory address settings can be made.

[Summary of the Invention] In the present invention, a gate table register has a partial copy of the pin data table A owned by the goose, the table is indexed by an address on an external bus, and the external bus is indexed based on the resulting information. The interface section is configured to selectively prohibit the reception of addresses from the outside, which allows for free and detailed mapping to the address space of the microprocessor. Also, the software can be freely rewritten during operation.

[Embodiments of the invention]

The operation of one embodiment will be described below with reference to FIG. 1st
In the figure, 1 to J6 are components of the board (Φi), and 11 is a microprocessor (
(hereinafter referred to as μ-p), 1 x i"j MMU (memory management unit). This MMU J 2 Vx
, μmpH memory mapping table MT. That is, this mating table MTVC stores information indicating the self-board area in the memory space of the entire system and its usage status. 13 is external bus 1
The gate table register (GT) of the memory structure indexed by the address on the external bus 18 determines whether the self? - It is used to judge whether or not the access is to a domain, and the mapping table M of MMU 12
Part of the information of T is simultaneously written (copied) when writing to the 1i'1llilLT 12 described above. 14
is the external data bus 17 and address bus 18 and μm
pH's internal data bus 15 and address bus 1
This is an external bus interface section that makes adjustments with 6. This external bus interface section 14c external address bus 1
It has a dart function that looks up the table in the gate table register 13 using the address above 8 and determines whether or not the above address can be accepted based on the result.

Here, the operation of one embodiment will be explained. External address bus 1
8, the external bus interface section J4 uses this external address to look up the table in the gate table register 13, and based on the corresponding output information, determines whether the external address is It is determined whether the internal address is 6 or not, and it is determined whether to start or prohibit information exchange with the outside.

By carrying out such memory address management control, detailed mapping is possible by setting the memory address of the gate table register 13, and the gate table register 13 can be rewritten at any time by software. Furthermore, since the MMU 12 and the gate table register 13 are written at the same time using the same data, the conventional problem of setting the address setting switch incorrectly is eliminated, and reliability can be improved.

〔Effect of the invention〕

As described in detail above, according to the microprocessor system of the present invention, the gate table register has a partial copy of the mapping table of the card, and the table is indexed by the address on the external bus, and the result is By configuring the external interface section to selectively prohibit reception of addresses from the outside based on the information, it becomes possible to freely and precisely map the address space of the microprocessor.

Also, it can be freely rewritten using software during operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional configuration. 11... Microprocessor (μmp), 12...
Memory management unit (MMU), 13... Gate table register (GT), 14... External bus interface section, 15.16... Internal bus, 17°J8...
・External bus, MT...mapping table.

Claims (1)

[Claims] A microprocessor, an external bus interface section,
an internal functional circuit used by the microprocessor and external bus interface unit in a time-sharing manner; a memory mapping table indexed by addresses from the microprocessor and external bus interface unit; and a portion within this memory mapping table. The gate table has address management information and is indexed by the address input via the external bus, and the gate table is indexed by the address input via the external bus. A microprocessor system characterized in that an internal functional circuit is prohibited from being accessed by the external bus interface unit.