JPS61152137A - Synchronizing system - Google Patents

Abstract

PURPOSE:To set reception and transmission clocks to a constact phase relation even when a clock is not received and to shorten the time required for synchroni zation by measuring a phase difference between the reception clock received by the 1st station and the 1st transmission clock. CONSTITUTION:Stations A and B are provided with the same constitution, and comprise the digital signal transmission system of a simplex system. A counter 19 at the station A side outputs the transmission clock TCLKA, which controls an A/D converter, and a transmitter 4 transmits a digital signal to the station B. A receiver 7 receives the signal from the station B, and a clock reproducing circuit 13 generates a clock RCLKA synchronous with the reception signal. A measuring circuit 16 measures the phase relation between the RCLKA and the TCLKA at the transmission side, and on the basis of this measured result a control part 15 decides the phase of the output TCLKA' of a variable delay circuit 14. The phase of the output TCLKA' is equal to that of the received digital signal, thereby shortening the time necessary for synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for establishing synchronization when transmitting denotal signals using the simplex method.

[Prior Art and Problems to be Solved by the Invention] Conventionally, digital signal reception using the simplex method generally involves a method in which the signals are in an asynchronous state at the start of reception, and then synchronization is established after a certain period of time has elapsed. That is,
The phase of the reception clock or reception frame synchronization signal before starting reception was at a position completely unrelated to the phase of the digital signal at the time of reception. Therefore, a large amount of time is required for synchronization, which poses a practical problem.

For example, digital signal transmission of 10 Kpps to 30 Kbps takes several tens of m5ec to several hundred msec until synchronization is established.
EC level was required, and during that time it was not possible to receive signals. For example, when transmitting a data signal of several hundred bits, it is necessary to transmit dummy information for a long time in order to establish synchronization, which may extremely degrade the transmission efficiency. As.

This may cause the beginning of one call to be cut off when two parties make multiple calls using digital audio signals.Especially, if the other party returns immediately after you end the call, the content may not be clear. There were drawbacks such as inability to distinguish.

Therefore, an object of the present invention is to provide a means for overcoming the above-mentioned drawbacks of the conventional system.

In particular, it is an object of the present invention to provide a synchronization method that can reduce the time required to establish synchronization of digital signals returned from the other party immediately after transmitting the digital signals to a practically negligible range.

[Means and effects for solving the problem] In the present invention, when the second station receives a digital signal from the first station, not only the receiving clock but also the transmitting clock is synchronized with the received data. , the second station transmits a digital signal using the transmission clock.

Also.

The first station is provided with means for measuring the phase difference between the reception clock and the transmission clock of the first station regarding the received digital signal, and the reception clock of the first station is kept constant with the transmission clock even when not receiving data. The configuration is such that a phase relationship is maintained.

The above is about clock synchronization, but the same applies to frame synchronization signals. Namely.

At the second station, the transmission frame synchronization signal is frame synchronized with the digital signal at the time of reception, and is further transmitted in accordance with the transmission frame synchronization signal.

When the first station receives this, it measures the phase difference between the received frame synchronization signal and the transmitted frame synchronization signal, and measures the phase difference between the received frame synchronization signal and the transmitted frame synchronization signal of the first station. The structure is designed to maintain a relationship.

In this way, in the present invention, the first station transmits a signal,
When the response is received by the second station in a short time, the phase of the digital signal has a certain phase relationship with respect to the transmission clock or the transmission frame synchronization signal.
This phase relationship is measured in advance, and the phase of the digital signal to be received primarily is predicted by keeping the reception clock or reception frame synchronization signal of the first station at a constant phase even when no reception is being received.

〔Example〕

FIG. 1 shows a first embodiment of the present invention, and shows a synchronization method for clocks.

As an example, Shinzolex transmission and reception of digital audio is shown. Regarding station A, 1 is a transmitter, and 3 is an analog-to-digital converter that converts analog voice into a digital signal. The output of the analog-to-digital converter 3 is sent to the transmitter 4
is input to. Here, 18 is an oscillator, and 19 is a counter. The counter 19 outputs a transmission clock TCLKA. The analog-to-digital converter 3 operates in accordance with the transmission clock TCLKA, and outputs a digital signal synchronized with TCLKA. 2 is a press switch 5, which starts up the transmitter 4 when turned on. The state of the press switch 2 is also monitored by the control section 15. Now, when press switch 2 is turned on.

In response to this, the control unit 15 turns the antenna switch 5t to the transmitting side, and transmits the signal through the antenna 6 as a smudge wave.

When the press switch 2 is OFF, the control section 15.

The antenna switch 5 is turned to the receiving side. At this time,
The radio waves received at the A station are received by the receiver 7 and further converted into a digital to analog signal by the digital to analog converter 8. Further, the squelch circuit 11 detects reception by the receiver 7, turns off the squelch signal, and opens the switch 9. Then, the output of the digital-to-analog converter 8 is output as voice from the receiver 10 through the switch 9.

The changeover switch 12 receives the response from the squelch circuit 11, and
During signal reception, the output of the receiver 7 is passed to the clock recovery circuit 13. The clock regeneration circuit 13.

During reception, a synchronized clock RCLKA is obtained for the output of the receiver 7. Output R of clock regeneration circuit 13
The digital-to-analog converter 8 operates according to CLKA. 17 is an AND circuit, which operates after a certain period of time τC has elapsed since it started receiving digital signals.

The receive clock RCLKA is allowed to elapse, the 2 frequency divider 19 is reset, and the transmit clock TCLKA is synchronized.

Now, in the case of the second invention, it takes 2 hours τ from the start of reception.

Within this time, the phase relationship between RCLKA and TCLKA is measured by the measuring circuit 16. Based on this measurement result.

The control section 15 determines the phase of the output TCLKA' of the variable delay circuit 14. That is, in the variable delay circuit 14, T
CLK and the received digital signal are selected so that they are in exactly the same phase.

As described above, the configuration of the A station is exactly the same for the B station.

That is, the units 101 to 119 of the B station correspond to the units 1 to 19 of the A station, respectively, and basically operate in exactly the same way.

Next, the establishment of clock synchronization between the A station and the B station will be described below. First, suppose that station A sends a call to station 9B. At this time, assuming that the phase of the transmission clock T CLKA of the A station is θ0, regarding the reception of the B station with respect to the A station transmission, that is, from the analog-to-digital converter 3 of the A station's transmission system to the transmitter 4. Antenna switch5. and the antenna 106 in the receiving system of the B station. Antenna switch 105. Receiver 107. Changeover switch 112. and is transmitted to the clock recovery circuit 113, and by the time the phase synchronization of the transmission clock TCLKII of the B station is finally performed, the fixed phase θAll is shifted by a certain fixed phase θ010. It has become.

Next, when station B is in a non-receiving state, the AND circuit 117
is disconnected, and the transmission clock TCLKB enters a free-running state. This value θ. 10 Regarding All, after receiving station B
If the time TB until the start of station transmission is sufficiently short, it can be considered that the phase of the transmission clock TCLKB will not shift. For example, TB Yu 300m5ec, data rate 10Kbpp
, the stability of the oscillator 118 is 10 x 10-6.
The phase shift Δθ during this time is dθ=0.3X10X10 Xl0XIOX360=1
It is 0.8 dsg, and this deviation Δθ is practically ignored.

Next, within a short period of several hundred m5ec to 1 sec.

Assuming that there is a response from station B to station A, at this time, the transmitter 1 is sent from the analog-digital converter 103 of the transmission system of the B station.
04. Antenna switch 105 and antenna 106
Then, the antenna 6 in the receiving system of station A,
Antenna switch5. Receiver 7. Changeover switch 12. Until it is transmitted to the clock recovery circuit 13, the phase of the received clock RCLKA of the A station is further shifted by θ.

θ0+θmu3+θBA tonal. Here, time τ. The deviation from the transmission clock TCLKA within θAB + θ
Ayu = θ.

The value of is measured by the circuit 16 and set in the variable delay circuit 14.

Next, the switch 12 selects the variable delay circuit 14 while the B station transmission is completed and the A station is transmitting again, that is, when the A station is not receiving. Therefore, during this period, the phase of the receive clock RCLK A is the phase of the transmit clock TCLK.
It always deviates from A by θ, = θAB + θ, A.

Therefore, when the A station sends a transmission to the B station again and a response is returned from the B station to the pA station in a short time, the synchronization with respect to the reception clock of the A station is θ. Since it starts from phase 10, synchronization is established from the very beginning.

The above has described synchronization of the reception clock of station A, but
The same can be said about the establishment of synchronization for the station, since it has a completely symmetrical configuration to that of station A.

Regarding the establishment of synchronization as described above, once the setting of the variable delay circuit 14 is performed, the reception clock RCLKA is always changed to the transmission clock TCL when transmitting and receiving calls are repeated.
It is possible to maintain a phase difference of θ with respect to KA. This also applies to the variable delay circuit 114 of the B station.

Therefore, when stations A and B enter a simple communication state and repeat sending and receiving calls to each other in a short period of time, synchronization is established from the beginning of each call, so the beginning of the two calls is interrupted. There is no problem, and therefore problems such as the content not being recognized do not occur.

Next, an embodiment of the tube 2 of the present invention will be described with reference to FIG.

FIG. 2 specifically shows the case where the frame synchronization method is used for single-lenox transmission and reception of digital audio. Regarding station 0, 201 is a transmitter, and 203 is an analog-to-digital converter that converts analog audio into a digital signal. The output of the analog-to-digital converter 203 is synthesized with a frame synchronization pattern by a synthesis circuit 220 and output to the transmitter 204. Here, 218 is an oscillator, and 219 is a frequency divider. The frequency divider 219 outputs a transmission clock TCLKC. Furthermore, by frequency-dividing the transmission clock by the circuit 222, a transmission frame synchronization signal T5YNCC is generated.
get. The analog-to-digital converter 203 operates frequently based on the transmission clock TCLKC.

Outputs a digital signal synchronized with TCLKC. Also.

The frame synchronization signal included in the output of synthesis circuit 220 is synchronized to the transmit frame synchronization signal T5YNCC. 202 is a press switch tearshi.

When turned ON, the transmitter 204 is activated. The state of the press switch 202 is also monitored by the control unit 215. Now, when the press switch 202 is turned on, the control unit 15 receives it, turns the antenna switch 205 to the transmitting side, and transmits the signal through the antenna 206 as a smudge wave.

When the press switch 202 is OFF, the control unit 215
The antenna switch 205 is turned to the receiving side. At this time, the radio wave received at station 0 is received by the receiver 207, and after extracting only audio information by the 2-separation circuit 224, it is converted into an analog signal by the digital-to-analog converter 208. Also, the squelch circuit 211 detects reception from the receiver 207 and turns off the squelch.
Open switch 209. Then, the output of the digital-to-analog converter 208 is transmitted through the switch 209 to the receiver 210.
It is output as a plain voice.

In response to the response from the squelch circuit 211, the selector switch 12 passes the output of the receiver 207 to the reproducing circuit 213 and the frame synchronization signal detecting circuit 223 during signal reception.

The clock recovery 0 circuit 213 controls the receiver 20 during reception.
A synchronized clock RCLKC is obtained for the output of 7.

Further, the frame synchronization signal detection circuit 223
A received frame synchronization signal R5YNCC is obtained by detecting the frame synchronization/arm turn included in the output of the signal R5YNCC. Here, by the output RCLKC of the clock recovery circuit 213.

The digital-to-analog converter 208 is operated, and the output R5YNCC of the frame synchronization signal detection circuit 223 is used to perform processing excluding frame synchronization and lean in the two-separation circuit 224 to extract only audio information. 217
is an AND circuit, and after a certain period of time τ8 has passed since the start of receiving the digital signal.

The receive frame synchronization signal R5YNCC is passed through, the 1 frequency dividers 219 and 222 are reset, and the transmit clock TC is
LKC and transmission frame synchronization signal T5YNCC are synchronized.

Now, in the case of the present invention, within 1 hour τ8 after starting reception,
The phase relationship between RCLKC and TCLKC is measured by the measurement circuit 216.
It is measured by Based on this measurement result, the control unit 215
determines the output TSYNCC' of variable delay circuit 214. That is, in the variable delay circuit 214, T 5YNCC'
phase and frame synchronization for the received digital signal.
9 turns are selected so that they are in exactly the same phase.

As described above, the configuration of the 0th station is exactly the same for the D station.

That is, each section 301 to 324 of station D corresponds to 201 to 224 of station 0, and basically operates in exactly the same way.

Next, the establishment of frame synchronization between station 0 and station D will be described below.

First, suppose that station 0 sends a call to station 9D. At this time, the phase of the transmission frame synchronization signal T5YNCC of station 0 is ψ. Then, regarding the reception of station D for transmission by station 0,
That is, from the frame synchronization pattern synthesis circuit 220 of the transmitting system of the 0th station, the transmitter 2o4° antenna switch 205
．． and the antenna 206, and further to the antenna 306, antenna switch 305, etc. in the receiving system of the D station. Receiver 3o7° changeover switch 312. and is transmitted to the frame synchronization signal detection circuit 323, until finally performing phase synchronization of the transmission frame synchronization signal T5YNCD of station D.

It is shifted by a certain fixed phase ψCD, resulting in ψ0+ψCD.

Next, when station D is in a non-receiving state, AND circuit 31
7 is disconnected, the transmission frame synchronization signal T 5YNCD
enters self-propelled state. This value ψ. Regarding +ψCD, if the time TD from the end of station D reception to the start of station transmission is sufficiently small, it can be considered that the phase of the transmission frame synchronization signal T5YNCC will not shift for the reason explained with reference to FIG.

Next, if there is a response from station D to station 0 within a short period of time, in this case, the frame synchronization pattern synthesis circuit 320 of the transmission system of station D will transmit @304 antenna switch 305. And through the antenna 306, the antenna 206 and antenna switch 20 in the reception system of station 0
5. Receiver 207 changeover switch 212. Furthermore, the phase of the received frame synchronization signal R5YNCC of station 0 until it is transmitted to the frame synchronization signal detection circuit 223 is ψ
It shifts by DC, resulting in ψ0+ψ, D+ψDC. Here, within 1 hour τ8, the transmission frame synchronization signal T 5YNC
The amount of deviation from C is ψCD + ψDc; ψ. The value of circuit 2
16 and set in the variable delay circuit 214.

Next, when the D station transmission is finished and the 0 station transmission is being performed again, that is, when the 0 station is not receiving, the switch 212 selects the variable delay circuit 214. Therefore, during this period, the phase of the received frame synchronization signal R5YNCC is always ψ with respect to the transmission frame synchronization signal. There is a deviation of = ψCD + ψDC.

Therefore, again, station 0, transmission is being made to station 90, and 1
Next, when a response is returned from station D to station 90 in a short time, the synchronization regarding the received frame synchronization signal of station 0 is ψ. +ψ
. Since the phase starts from the phase of , synchronization is established from the very beginning.

The above has described the establishment of synchronization of the received frame synchronization signals of station 0, but the same can be said for the synchronization of station D, since the configuration of station D is completely symmetrical to that of station 0.

Regarding the establishment of synchronization as described above, once the setting of the variable delay circuit 214 is performed, when transmitting and receiving calls are repeated, the reception frame synchronization signal R5YNCC is always ψ with respect to the transmission frame synchronization signal T5YNCC. It is possible to maintain the phase difference of This is due to the variable delay circuit 31 of the D station.
The same applies to 4.

Therefore, in the case of frame synchronization, as in the case of clock synchronization already explained, when transmitting and receiving calls from each other in a short period of time, synchronization is established for each call from the beginning. 2 There is no problem of cutting off the beginning of a call.

When the present invention is applied to a digital audio transmission system based on the simplex system, it is particularly effective for frame synchronization. This is because it takes a very long time for each station to distinguish frame synchronization and mother turns from other mother turns and detect them without error from among the received digital signals.

If this is done every time a call is made, it will be very difficult to hear and will cause an unpleasant feeling.

Furthermore, the present invention can be applied to extremely high signal efficiency when information with a short data length is transmitted and received in a short period of time, such as in a telemeter system. In the conventional method, 2
For example, when applying the present invention, whether or not the same time synchronization pattern is transmitted for 100 pits of information.

This type of synchronous t4 turn can be chosen to be extremely short.

〔Effect of the invention〕

As explained above using the embodiments, according to the present invention,
Immediately after transmitting a digital signal, the time required to establish synchronization of the digital signal returned from the other party can be reduced to a virtually negligible range.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the invention, and FIG. 2 is an explanatory diagram of a second embodiment of the invention. 1.101,201,301...Telephone, 4,104
204.304...Transmitter, 10,110,210°310...Handset, 7,107,207,307...
- Receiver, 15, 115, 215, 315...control unit. Agent Yosuke Goto, patent attorney

Claims (1)

[Claims] (1) In a synchronization method of a digital signal transmission system using a simplex method, a first station transmits a first digital signal using a first transmission clock or a transmission frame synchronization signal, and a second station transmits a first digital signal using a first transmission clock or a transmission frame synchronization signal. When receiving a digital signal, synchronization of a second reception clock or reception frame synchronization signal is established, and a second transmission clock or transmission frame synchronization signal is also established with respect to the first digital signal at least by the end of reception. sync, then second
When the station transmits, it transmits a second digital signal using the second transmission clock or frame synchronization signal, and
When the station receives the second digital signal,
means for establishing synchronization of a first reception clock or reception frame synchronization signal and measuring a phase difference between the first reception clock or reception frame synchronization signal and the first transmission clock or transmission frame synchronization signal; A synchronization system characterized by comprising means for holding the phase of the first reception clock or reception frame synchronization signal so as to keep the measured phase relationship constant during standby or transmission.