JPH04319827A - Signal detecting circuit - Google Patents

Abstract

PURPOSE:To prevent detection signals in synchronized state from being transmitted when a tone signal is fixed at an H level. CONSTITUTION:A signal detecting circuit contains a phase synchronizing means 1 which generates a reproduced digital signal with use of an inputted digital signal and a synchronization detecting means 2 which detects the synchronous/ asynchronous state between the reproduced digital signal received from the means 1 and a digital signal and transmits the corresponding information. Furthermore an information transmission control means 3 is added to transmit the information received from the means 2 after turning it into the asynchronous information if the next changing point cannot be detected within a period set after the first chaning point of the digital signal is detected.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal detection circuit used, for example, in detecting tone signals for mobile communication systems.

[0002] In mobile communication systems, in order to make effective use of frequencies, the wireless zone covered by base stations is made smaller.
A method is used in which the same frequency is repeatedly used between relatively close points, but this method may cause interference between the same frequencies and deteriorate the call quality.

[0003] Therefore, as one method to prevent this interference, monitoring audio tone signals (hereinafter abbreviated as tone signals) of different frequencies are provided in radio zones of the same frequency.
The base station allocates this information in advance to mobile devices within the corresponding wireless zone.

[0004] The mobile device internally generates a tone signal of the notified frequency, detects whether the tone signal extracted from the received signal matches the generated tone signal, and when it matches, transmits the desired wave. It sends out a synchronous state detection signal to indicate that it has been received, and an asynchronous state detection signal when there is a mismatch.

[0005] At this time, it is necessary to prevent the synchronization state detection signal from being sent out when the tone signal is fixed at the H level.

[0006]

[Prior Art] FIG. 4 is a block diagram of a conventional example, and FIG. 5 is a block diagram of a conventional example.
An example of a block diagram of the phase synchronization means in FIG. 6 is an explanatory diagram of the operation of FIG. FIG. 6 is a diagram showing a mutual relationship with a reproduced tone signal when the tone signal is fixed in the H state.

Here, the symbols on the left side of FIG. 6 indicate the waveforms of the portions with the same symbols in FIG. The operation of FIG. 4 will be described below with reference to FIGS. 5 and 6. First, the mobile device sends a tone signal extracted from the received signal and digitized to the phase comparator 11 in the phase comparator 1 .

[0008] Also, since a tone frequency specification notification of, for example, 6 KHz is input from the base station, the output of the oscillator of frequency f2 is sent to the variable frequency divider 13 via the switch SW switched as shown by the dotted line. The variable frequency divider 13 divides the frequency of the oscillator output by 4, for example, and then sends it to the fixed frequency divider 14.Then, the variable frequency divider 13 divides the frequency of the oscillator output, for example, by 4, and then sends it to the fixed frequency divider 14.The frequency is further divided by M to generate a reproduced tone signal of about 6 kHz, which is also sent to the phase comparator. At the same time, it is also sent to the synchronization detection means 2. Here, M is a positive integer.

[0009] Therefore, the phase comparator compares the phases of the two signals, and if the phase of the reproduced tone signal is ahead of the phase of the tone signal, the H level is set, and if it is behind, the L level is set as an up/down counter. Send on 12th.

[0010] The up/down counter increases the count value when it is at the H level, and decreases it when it is at the L level, and changes the division ratio of the variable frequency divider when the count value deviates from a predetermined threshold. Switch to 5 or 3. However, the frequency division ratio will not be switched unless it deviates from the threshold value. Note that even if the tone signal is not input to the phase synchronization means 1,
A reproduced tone signal of about 6 kHz, which is the frequency-divided output of the internal oscillator, is sent to the synchronization detection means.

Now, the synchronization detection means 2 is composed of, for example, a counter, and uses the reproduced tone signal as a clock.
As shown in FIG. 6A, the H level portion of the tone signal is sampled, and the number of times the tone signal is H level is counted.

If the count value for a predetermined time exceeds a set count value, it is determined that the device is in a synchronous state and an H level is sent out, but if it does not exceed the set value, it is determined that the device is in an asynchronous state and an L level is sent out.

[0013]

[Problems to be Solved by the Invention] Normally, a tone signal of, for example, 6 kHz is input to the tone signal detection circuit, but if it is fixed at the H level for some reason, the signal shown in (B) of FIG. As shown in (2)-2, the phase synchronization means is in a free-running state and sends out a reproduced tone signal, so the sampling result is always at H level.

[0014] This poses a problem in that a synchronized state detection signal is sent even though no tone signal is input. In the present invention, when the tone signal is fixed at H level,
The purpose is to prevent a synchronization state detection signal from being sent.

[0015]

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure, 1 is a phase synchronization means that generates a reproduced digital signal using an input digital signal.
Reference numeral 2 denotes synchronization detection means for detecting the synchronization/asynchronous state of the reproduced digital signal sent from the phase synchronization means and the digital signal and sending out corresponding information.

Further, 3 is information for transmitting information from the synchronization detection means as asynchronous information when the next change point cannot be detected within a set time from the time when the change point of the digital signal is detected. This is a sending control means.

[0017]

[Operation] The present invention detects the change point of the tone signal inputted by the information transmission control means 3, but if the next change point detection is not performed within a set time, the tone signal is input during that time. If the synchronization detection means has not been detected, the passage of information from the synchronization detection means is blocked, and asynchronous information is sent out.

That is, when the tone signal is fixed at the H level, synchronization information is sent to the synchronization detection means as described above, but since the change point is not detected within the set time,
The passage of synchronous information is blocked and asynchronous information is sent out.

[0019]

Embodiment FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. Note that the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG. Here, edge detection part 31, free-running timer 32, AND gate 3
3 shows the constituent parts of the information sending control means 3. Below, Figure 3
The operation of FIG. 2 will be explained with reference to FIG. 2. The information transmission control means, which is a part of the present invention, will be explained in detail, and other parts will be explained briefly since they have already been explained in detail.

First, as shown on the left side of point A in ■ in FIG. 3, when a normal tone signal is input, the edge detector 31 detects a rising point as shown in ■ in FIG. L
The level rising point detection pulse is used as a reset pulse.
For example, it is sent to a self-running timer 32 composed of a counter.

Since the free-running timer is designed so that a reset pulse is applied before it overflows, it returns to the initial state and repeats free-running. Incidentally, as shown on the left side of ◯ in FIG. 3, this timer sends an H level signal to the AND gate 33 until it overflows, so this gate is in an on state.

On the other hand, as explained in detail in the conventional example, the synchronization detection means 2 receives the reproduced tone signal of the phase synchronization means 1 as shown in (■) in FIG. 3 and the tone signal shown on the left side of (■) in FIG. Therefore, H level information (
(indicating a synchronous state) is sent out through the AND gate 33 which is in the on state (see the left side of ■ in FIG. 3).

Next, it is assumed that the tone signal is cut off at point A in (2) in FIG. 3 and is fixed at the H level. The free-running timer is reset at point A and starts free-running from the initial state, but since the reset signal is not applied to the timer, an overflow state occurs (point B in ■ in Figure 3), stopping the timer operation and starting free-running. L level is sent from the timer.

Therefore, since the AND gate 33 is turned off, the H level information sent out from the synchronization detection means 2 is blocked by this gate 33, and the L level information (indicating an asynchronous state) is sent out to the outside. (■ in Figure 3)
reference).

That is, when the tone signal is fixed at H level, asynchronous information is sent out and no synchronization detection signal is sent out.

[0026]

As described in detail above, the present invention has the advantage that when the tone signal is fixed at the H level, no synchronization detection signal is sent out.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram of an embodiment of the invention.

FIG. 3 is an explanatory diagram of the operation in FIG. 2;

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is an example of a block diagram of the phase synchronization means in FIG. 4;

6 is an explanatory diagram of the operation in FIG. 4; (A) is a diagram showing the mutual relationship when the tone signal and the reproduced tone signal are in a synchronized state;
(B) is a diagram showing the correlation with the reproduced tone signal when the tone signal is fixed in the H state.

[Explanation of symbols]

1 Phase synchronization means
2 Synchronization detection means 3 Information transmission control means

Claims (1)

[Claims] [Claim 1] Phase synchronization means (1) for generating a reproduced digital signal using an input digital signal;
In a signal detection circuit having a synchronization detection means (2) for detecting a synchronization state between a reproduced digital signal sent out from a phase synchronization means and the digital signal and sending out corresponding synchronization information, a change point of the digital signal is detected. The present invention is characterized by the provision of information transmission control means (3) for transmitting the synchronization information from the synchronization detection means as asynchronous information when the next change point cannot be detected within a set time from the time of detection. signal detection circuit.