JPS61150408A - Digital filter - Google Patents

Digital filter

Info

Publication number
JPS61150408A
JPS61150408A JP27247884A JP27247884A JPS61150408A JP S61150408 A JPS61150408 A JP S61150408A JP 27247884 A JP27247884 A JP 27247884A JP 27247884 A JP27247884 A JP 27247884A JP S61150408 A JPS61150408 A JP S61150408A
Authority
JP
Japan
Prior art keywords
signal
digital
output
outputs
band
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27247884A
Other languages
Japanese (ja)
Inventor
Sunao Ishizaki
直 石崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27247884A priority Critical patent/JPS61150408A/en
Publication of JPS61150408A publication Critical patent/JPS61150408A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain two outputs in a small circuit scale by securing the partial share between a low band-pass filter and a band-pass filter. CONSTITUTION:An input signal is converted into a digital signal by an A/D converter 1. A delay element 5a receives the delay of a single unit time by the signal of a sampling signal generator 6 and is used as the input of a delay element 5b after undergoing the four rules of arithmetic. The inputs of both elements 5a and 5b are turned as they are into outputs and delivered through D/A converters 2a and 2b synchronously with the signal of the generator 6. These outputs of converters 2a(D/A1) and 2b(D/A2) are used as the outputs of a low band-pass filter and a band-pass filter respectively. Thus four multipliers and three addition/subtraction units are used. This decreases greatly the number of subtractors and simplifies the circuit constitution with high economical properties.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、入力信号をディジタル信号に変換して実時間
論理処理によりその通過域特性を定めるディジタルフィ
ルタに関する。特に、状態変数法に基づいて構成された
、二次形の低域通過および帯域通過フィルタに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter that converts an input signal into a digital signal and determines its passband characteristics through real-time logic processing. In particular, it relates to quadratic low-pass and band-pass filters constructed based on state variable methods.

本発明は通信装置に利用される。INDUSTRIAL APPLICATION This invention is utilized for a communication device.

〔概要〕〔overview〕

実時間論理処理を行い、その出力をアナログ信号に変換
して出力するディジタルフィルタにおいて、 低域通過フィルタおよび帯域通過フィルタの回路一部具
用して設けることにより、 二つの出力を小さい回路規模で実現するものである。
In a digital filter that performs real-time logic processing, converts the output into an analog signal, and outputs it, two outputs can be generated in a small circuit scale by providing a low-pass filter and a band-pass filter as part of the circuit. It is something that will be realized.

〔従来の技術〕[Conventional technology]

状態変数法に基づ(二次形のフィルタは、一般に実施例
の項に添付した第1式で表わされる。周波数選択フィル
タをディジタルフィルタで構成する場合に、一般に用い
られる方法はアナログ系のフィルタの伝達関数に適当な
S−Z変換(例えば、双線形変換、整合2変換等)を施
すことによりディジタルフィルタの伝達関数を得、この
伝達関数に対応する状態変数法によるフィルタ表現とし
て前記第1式の形式を得る。
Based on the state variable method (a quadratic filter is generally expressed by the first equation attached to the example section). The transfer function of the digital filter is obtained by applying an appropriate S-Z transformation (e.g., bilinear transformation, matching 2 transformation, etc.) to the transfer function of Get the form of the expression.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし上記の従来の方法によっては、低域通過および帯
域通過の両特性をもつ2出力を得ようとする場合には、
前記第1式において、行列CおよびDがそれぞれ単位行
列・専行列になるとは限らない。したがって、演算に必
要な乗算器、加減算器の数は上記第1式を処理する場合
、従来例である第2図に示すように多数の乗算器12個
、加減算器4個が必要となってしまい回路構成の複雑さ
、経済性に問題があった。
However, when trying to obtain two outputs with both low-pass and band-pass characteristics using the conventional method described above,
In the first equation, matrices C and D are not necessarily unit matrices and dedicated matrices, respectively. Therefore, when processing the first equation above, the number of multipliers and adders/subtractors required for the calculation is as follows: 12 multipliers and 4 adders/subtractors are required as shown in the conventional example shown in FIG. Finally, there were problems with the complexity of the circuit configuration and economic efficiency.

本発明は、前述の問題点を解決するためになされたもの
であり、演算器の乗算器と加減算器の数を大幅に減少し
た低域通過/帯域通過ディジタルフィルタを提供するこ
とを目的とする。
The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide a low-pass/band-pass digital filter in which the number of multipliers and adders/subtractors in an arithmetic unit is significantly reduced. .

〔問題点を解決するための手段〕[Means for solving problems]

本発明の低域通過または帯域通過形のディジタルフィル
タは、特定の周波数の入力信号に対し、実時間での数値
処理により低域通過および帯域通過の特性をもつ2種の
信号を出力することを特徴とする。さらに上記特定周波
数が可聴周波数であることが望ましい。
The low-pass or band-pass type digital filter of the present invention is capable of outputting two types of signals with low-pass and band-pass characteristics through real-time numerical processing in response to an input signal of a specific frequency. Features. Furthermore, it is desirable that the specific frequency is an audible frequency.

〔作用〕[Effect]

本発明は、実施例の項に添付した第1式および第2式に
よって、行列rcJを“単位行列”、行列rDJを“専
行列”にすることにより状態変数x、(n)から低域通
過特性が生じ、x、(n)から帯域通過特性が生ずる。
According to the first and second equations attached to the embodiment section, the present invention makes the matrix rcJ an "identity matrix" and the matrix rDJ a "dedicated matrix," thereby obtaining a low-pass signal from the state variables x, (n). A bandpass characteristic arises from x,(n).

添付第2式により“単位行列”および“専行列”を調整
することにより、行列rBJをきめ、このフィルタのイ
ンデイシャル応答との関連に着目して設けた乗算器と加
減算器数が従来例のものより著しく少数で同等の性能を
示すようになる。
By adjusting the "unit matrix" and "dedicated matrix" using the attached second equation, the matrix rBJ is determined, and the number of multipliers and adders/subtracters provided focusing on the relationship with the initial response of this filter is reduced compared to the conventional example. It will show the same performance with a significantly smaller number.

〔実施例〕〔Example〕

本発明を添付第1図の実施例装置により説明する。入力
信号はアナログディジタル変換器1を介して加減算器4
aおよび4Cに入力する。加減算器4aの出力は遅延素
子5aに入力し、この遅延素子5aの出力は上記加減算
器4aに、乗算器3aを介して入力するとともに、上記
加減算器4Cおよびディジタル・アナログ変換器2aに
人力する。この2a出力は低域通過フィルタ出力#lで
ある。加減算器4Cの出力は乗算器3bを介して加減算
器4bに入力する。加減算器4bの出力は遅延素子5b
に入力する。遅延素子5bの出力はディジタル変換器2
b、乗算器3Cおよび乗算器3dにそれぞれ入力する。
The present invention will be explained with reference to an embodiment of the apparatus shown in FIG. 1 attached hereto. The input signal is sent to an adder/subtractor 4 via an analog-to-digital converter 1.
Enter a and 4C. The output of the adder/subtractor 4a is input to the delay element 5a, and the output of the delay element 5a is input to the adder/subtractor 4a via the multiplier 3a, and is also manually input to the adder/subtractor 4C and the digital/analog converter 2a. . This 2a output is a low-pass filter output #l. The output of the adder/subtractor 4C is input to the adder/subtracter 4b via the multiplier 3b. The output of the adder/subtractor 4b is sent to the delay element 5b.
Enter. The output of the delay element 5b is sent to the digital converter 2.
b, are input to multiplier 3C and multiplier 3d, respectively.

乗算器3Cの出力は前記加減算器4aに入力する。また
乗算器3dの出力は上記加減算器4bに入力する。上記
ディジタルアナログ変換器2bの出力は帯域通過フィル
タの出力#2である。標本化信号発生器6の出力は、前
記アナログディジタル変換器1およびディジタルアナロ
グ変換器2aと2bならびに遅延素子5aと5bにそれ
ぞれ入力する。
The output of the multiplier 3C is input to the adder/subtracter 4a. The output of the multiplier 3d is input to the adder/subtracter 4b. The output of the digital-to-analog converter 2b is the output #2 of the bandpass filter. The output of the sampling signal generator 6 is input to the analog-to-digital converter 1 and the digital-to-analog converters 2a and 2b and delay elements 5a and 5b, respectively.

次に本発明装置の動作について述べる。入力信号は、ア
ナログディジタル変換器1により、ディジタル信号に変
換される。遅延素子5aは標本化信号発生器6の信号に
より二車位時間の遅延を施し、加減乗算処理されたのち
、遅延素子5bの人    ・力となる。本発明では遅
延素子5a、5bの入力はそのまま出力となり、標本化
信号発生器6の信号と同期してディジタルアナログ変換
器2a、2bを通して出力される。ディジタルアナログ
変換器2a、2bのうち、2a(D/Al)は、低域通
過フィルタ、2b (D/A2)は帯域通過フィルタの
出力である。
Next, the operation of the device of the present invention will be described. The input signal is converted into a digital signal by an analog-to-digital converter 1. The delay element 5a applies a two-cycle delay to the signal from the sampling signal generator 6, and after being subjected to addition, subtraction, and multiplication processing, becomes the force of the delay element 5b. In the present invention, the inputs of the delay elements 5a and 5b become outputs as they are, and are outputted through the digital-to-analog converters 2a and 2b in synchronization with the signal from the sampling signal generator 6. Of the digital-to-analog converters 2a and 2b, 2a (D/Al) is the output of a low-pass filter, and 2b (D/A2) is the output of the band-pass filter.

本発明はつぎに示す第1式および第2式によって“単位
行列”および“専行列”を調整することにより、乗算器
と加減算器の大幅削減が可能となったものである。第1
式は状態変数法に基づくディジタルフィルタの一般式、
第2式は本発明による低域通過または帯域通過フィルタ
の状態変数表現である。
In the present invention, the number of multipliers and adders/subtractors can be significantly reduced by adjusting the "unit matrix" and "dedicated matrix" using the first and second equations shown below. 1st
The formula is a general formula for a digital filter based on the state variable method,
The second equation is a state variable representation of a low-pass or band-pass filter according to the invention.

第1式; ここに、u (n)は時刻nの人力、V+(n)、y2
(n)は出力;x+(n)、x−<n)は状態変数、”
ij、C1js b、、di (i、j=1.2)はそ
れぞれy+(n)、yz(n)が低域通過、帯域通過特
性をもつように決定された定数。
First equation; Here, u (n) is the human power at time n, V + (n), y2
(n) is the output; x+(n), x-<n) is the state variable,"
ij, C1js b,, di (i, j=1.2) are constants determined so that y+(n) and yz(n) have low-pass and band-pass characteristics, respectively.

第2式; ここにu (n)は時刻nの入力、Xl (n) 、’
xz(n)は状態変数であり、xl(n)は低域通過、
x2(n)は帯域通過特性をもつフィルタの出力である
Second equation; Here u (n) is the input at time n, Xl (n),'
xz(n) is the state variable, xl(n) is the low pass,
x2(n) is the output of a filter with bandpass characteristics.

r cosθ、r sinθは定数であり、フィルタの
遮断周波数fo、クォリティファクタQならびに標本化
間隔Tとは r=e xp (−πf、T/Q) θ=JT=〒フ4Q”  2πfoT なる関係がある。
r cos θ and r sin θ are constants, and the filter cutoff frequency fo, quality factor Q, and sampling interval T have the following relationship: r = e xp (-πf, T/Q) θ = JT = be.

〔発明の効果〕〔Effect of the invention〕

本発明を従来装置と比べると、従来装置では12個の乗
算器と4個の加減算器を必要とするのに対し、本発明に
よれば、4個の乗算器と3個の加減算器で構成され、演
算器の数が大幅に減少され、回路構成の簡明化と経済性
に役立つ効果がある。
Comparing the present invention with a conventional device, the conventional device requires 12 multipliers and 4 adders/subtractors, whereas the present invention consists of 4 multipliers and 3 adders/subtractors. The number of arithmetic units is greatly reduced, which has the effect of simplifying the circuit configuration and improving economy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例装置のブロック構成図。 第2図は従来例装置のブロック構成図。 1・・・アナログ・ディジタル変換器、2a、2b・・
・ディジタル・アナログ変換器、3a〜31・・・乗算
器、4a〜4d・・・加減算器、5a、5b・・・遅延
素子、6・・・標本化信号発生器。
FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional device. 1...Analog-digital converter, 2a, 2b...
- Digital-analog converter, 3a to 31... Multiplier, 4a to 4d... Addition/subtraction device, 5a, 5b... Delay element, 6... Sampling signal generator.

Claims (2)

【特許請求の範囲】[Claims] (1)入力信号をディジタル信号に変換するアナログ・
ディジタル変換器と、 このディジタル信号を実時間で論理処理する回路手段と
、 この回路手段の出力をアナログ信号に変換するディジタ
ル・アナログ変換器と、 このディジタル・アナログ変換器の出力が接続された出
力端子と を備えたディジタルフィルタにおいて、 上記回路手段は、特性周波数域の入力信号に対して、低
域通過特性を有する第一の出力信号と、帯域通過特性を
有する第二の出力信号とを出力する構成であり、 上記ディジタル・アナログ変換器および上記出力端子は
、上記第一の出力信号および上記第二の出力信号に介し
て各別に設けられた ことを特徴とするディジタルフィルタ。
(1) Analog converting input signal to digital signal
a digital converter; circuit means for logically processing this digital signal in real time; a digital-to-analog converter for converting the output of this circuit means into an analog signal; and an output to which the output of this digital-to-analog converter is connected. In the digital filter having a terminal, the circuit means outputs a first output signal having a low-pass characteristic and a second output signal having a band-pass characteristic in response to an input signal in a characteristic frequency range. A digital filter, characterized in that the digital-to-analog converter and the output terminal are provided separately via the first output signal and the second output signal.
(2)特定周波数域は可聴周波数域である特許請求の範
囲第(1)項に記載のディジタルフィルタ。
(2) The digital filter according to claim (1), wherein the specific frequency range is an audible frequency range.
JP27247884A 1984-12-24 1984-12-24 Digital filter Pending JPS61150408A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27247884A JPS61150408A (en) 1984-12-24 1984-12-24 Digital filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27247884A JPS61150408A (en) 1984-12-24 1984-12-24 Digital filter

Publications (1)

Publication Number Publication Date
JPS61150408A true JPS61150408A (en) 1986-07-09

Family

ID=17514482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27247884A Pending JPS61150408A (en) 1984-12-24 1984-12-24 Digital filter

Country Status (1)

Country Link
JP (1) JPS61150408A (en)

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