JPS61192113A - Rate conversion digital filter - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to lower the manufacture cost by connecting plural stages of low magnification rate conversion digital filters in cascade to obtain the desired final magnification. CONSTITUTION:It is supposed that, for example, an A/D converting circuit is arranged on the pre-stage of a quadruple rate conversion digital filter. Delay circuits 11, 12 having a delay of (Ts/2) being a half of the sampling period of the A/D converting circuit are connected in cascade in the double rate conversion digital filter and the input signal, and the signals subjected to delay of Ts/2 and Ts are synthesized by adder circuits 13, 14 and factor circuits 15, 16. In the double rate conversion digital filter 20 of the poststage, delay circuits 21, 22 having a delay of Ts/4 are connected in cascade, and the input signal from the pre-stage and the signals delayed by Ts/4 and Ts/2 are synthesized similarly as above. Thus, a few number of stages are enough for the delay circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a rate conversion digital filter used in a digital processing circuit for image signals.

Conventional rate conversion digital filters have the function of passing only harmonic components that are a predetermined number of times the fundamental wave out of an input signal consisting of a fundamental wave and its harmonics, and are used in image signal digital processing circuits, etc. used in

For example, N (integer) placed after the A/D conversion circuit
The rate-doubling digital filter consists of a transversal filter equipped with a group of delay circuits having a delay amount of 1/N of the sampling period. The structure is such that only harmonics existing around N multiples of the fundamental wave are allowed to pass through.

In the case of the quadruple rate conversion digital filter, as illustrated in FIG. The signals delayed by a predetermined amount are synthesized by a predetermined algorithm using 1 to 4 in an adder circuit al-a7 and a coefficient circuit, and output to an output terminal OU.
It is configured to output to T.

That is, as shown in FIG. 4(A), when a signal containing frequency components distributed around the sampling frequency fs and its harmonics is supplied to the input terminal IN, the signal as shown in FIG. 4(B) is supplied to the input terminal IN.
), only frequency components distributed around harmonics of orders that are multiples of 4 (4, 8, 12, . . . ) are output from the output terminal OUT.

Problems to be Solved by the Invention In the conventional rate conversion digital filter described above, in order to improve the performance in terms of the allowable amount of ripple in the band, the desired amount of attenuation out of the band, the desired steepness of the attenuation characteristic at the band edge, etc., the delay circuit is used. There is a problem that the required number of stages increases, the circuit becomes large-scale, and the manufacturing cost increases.

Structure of the Invention Means for Solving the Problems The rate conversion digital filter of the present invention which solves the problems of the prior art described above has a structure in which a plurality of low magnification rate conversion digital filters are connected in series to obtain a desired final magnification. By obtaining this, the circuit size is reduced and the manufacturing cost is reduced.

Hereinafter, the effects of the present invention will be explained in detail by way of examples.

Embodiment FIG. 1 is a circuit diagram showing the configuration of a quadruple rate conversion digital filter according to an embodiment of the present invention.

This 4x rate conversion digital filter is constructed by connecting the 2x rate conversion digital filter 10 and 20 in series.

In this 4x rate conversion digital filter,
A delay circuit with the minimum number of stages necessary to achieve filtering characteristics equivalent to the conventional quadruple rate conversion digital filter illustrated in FIG. 3 is used.

In the front stage of this 4x rate conversion digital filter,
It is assumed that appropriate means for generating harmonic components, such as an A/D conversion circuit, is provided.

In the double rate conversion digital filter 10 in the previous stage, half the sampling period (Ts
Delay circuits 11 and 12 having a delay amount of
Adder circuits 13 and 14 are delayed by s/2 and Ts.
and are synthesized by coefficient circuits 15 and 16 using a predetermined algorithm.

In the second rate converting digital filter 20 at the subsequent stage, a delay circuit 21 .
22 are connected in series, and the input signal from the previous stage and this are transmitted to each of the above delay circuits at Ts/4 and Ts/4, respectively.
The signals delayed by 2 are combined by adder circuits 23 and 24 and coefficient circuits 25 and 26 using a predetermined algorithm.

The digital signal supplied to the double rate conversion digital filter 10 in the previous stage is the one obtained by sampling the corresponding analog signal at the sampling frequency fs and digitizing it in the A/D conversion circuit in the previous stage. As exemplified by the frequency spectrum (A) in the figure, the frequency spectrum includes frequency components distributed around the sampling frequency fs and its respective harmonics. However, in order to prevent aliasing, f
Since high frequency components of s/2 or higher are removed,
The signal bandwidth that exists around each harmonic is limited to f3 and does not overlap.

As shown in FIG. 2(B), among the harmonics of the fundamental wave rs, those having an order that is a multiple of 2 (2f s).

Only the frequency components around 4fs, 5fs, etc.) pass through the double rate conversion digital filter 10 in the previous stage,
The signal is supplied to the double rate conversion digital filter 20 at the subsequent stage.

The signal (B) supplied to the subsequent double rate conversion digital filter 20 has been rate converted to include the fundamental wave 2fs and its harmonic components.

Among the harmonics of the fundamental wave 2fs, as shown in Figure 2 (C), those having orders that are multiples of 2 (2, 4, 6...) (4fs, 8fs, 12fs...) Only the surrounding frequency components pass through the subsequent double rate conversion digital filter 20.

In this way, the double rate conversion digital filter lO
and 20 are connected in series, rate conversion with a final magnification of 4 is realized.

As mentioned above, the quadruple rate conversion digital
The filter is configured to achieve filtering characteristics equivalent to the conventional quadruple rate conversion digital filter illustrated in FIG. That is, the coefficient values α, β, T, and δ of coefficient circuits 15, 16, 25, and 26 in the quadruple rate conversion digital filter of this embodiment, and the coefficients in the quadruple rate conversion digital filter of FIG. Coefficients of 1 to 4 in the circuit (LEA, B, C, D are A-βδ, B=βδ+
The following relationships hold: βγ, C−αδ+βγ+βδ, and D−αδ+αγ+βδ.

The 4x rate conversion digital filter in Figure 1 is
Compared to the conventional quadruple rate conversion digital filter shown in the figure, the number of delay circuits and adder circuits is reduced by three each, and the circuit scale is reduced accordingly, resulting in lower cost.

In order to realize advanced characteristics, the more the number of columns of delay circuits increases, the more remarkable the effect of circuit scale reduction according to the present invention becomes.

Furthermore, since the operating speed of the filter 10 at the front stage is half the operating speed of the filter 20 at the rear stage, inexpensive low-speed elements can be used.

The case of 4x rate conversion was illustrated above, but the 2x rate conversion digital filter and the 3x rate conversion digital filter
6x rate conversion digital converter with filters connected in cascade
3 filters and 2x rate conversion digital filters.
Digital filters of other suitable magnifications can also be implemented, such as cascaded 8x rate converting digital filters.

Effects of the Invention As explained in detail above, the rate conversion digital filter of the present invention has a configuration in which a plurality of low magnification rate conversion digital filters are connected in series to obtain a desired final magnification, so that the circuit size can be reduced. This reduces manufacturing costs.

Furthermore, since the operation speed of the previous stage is reduced, it is possible to use low-cost, low-speed elements, thereby facilitating the design.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a quadruple rate conversion digital filter according to an embodiment of the present invention, FIG. 2 is a frequency spectrum for explaining the operation of the filter in FIG. 1, and FIG.
The figure is a circuit diagram showing the configuration of a conventional quadruple rate conversion digital filter, and FIG. 4 is a frequency spectrum for explaining the operation of the filter of FIG. 3. 10.20...2x rate conversion digital filter,
11,12,21.22...delay circuit, 13.14,2
3.24...addition circuit, 15,16.25.26...coefficient circuit.

Claims (1)

[Claims] A rate conversion digital filter characterized in that a plurality of rate conversion digital filters with a magnification lower than a desired final magnification are connected in series to achieve a desired final magnification.