JPH0453307A - Sampling frequency converter - Google Patents

Abstract

PURPOSE:To reduce the operation time for one sample of an output data by providing a buffer storing input data by a 1st natural number and a buffer storing output data by a 2nd natural number and applying filter operation to an output data value after interleaving by the 2nd number of times only. CONSTITUTION:The converter is provided with input/output terminal 1, 5, an interpolation device 2, a low pass filter 3, an interleave device 4, an input buffer 6 and an output buffer 7. Then the processing period by a digital processor is selected to be a prescribed common multiple such as least common multiple between the processing period of the input buffer 6 and the processing period of the output buffer 7, and input data by 1st natural number are stored in the input buffer 6 and output data by 2nd natural number are stored in the output buffer 7 to apply the filter operation to M sets of the output data after interleaving only. Thus, the operation time per one sample of output data is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a sampling frequency converter that reduces calculation processing time such as filter calculation when converting the sampling frequency using a digital processor. be.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional sampling frequency converter disclosed, for example, in Japanese Patent Publication No. 64-2243. In the figure, 1 is an input terminal from which a signal of sampling frequency f1 is input. be done.

2 is an interpolator that inserts M-1 zero value signals at equal time intervals between two consecutive input signals, and sets the sampling frequency Mf.
1 signal. 3 is a low-pass filter that receives the output signal of the interpolator 2 and removes high-frequency components to prevent aliasing noise from being mixed into the thinned-out signal. A decimator 4 decimates the output signal of the low-pass filter 3 to output a signal having a sampling frequency f2.

Let me briefly explain the operation. First, the sampling frequency f□
If the smaller value of the sampling frequencies f2 and f2 after sampling frequency conversion is expressed as fl, and the cutoff frequency of the low-pass filter 3 is fo, then fo is expressed by the following equation.

f0≦f, in/2 −(1) As the low-pass filter 3, a filter called a transversal filter having a linear phase characteristic is generally widely used. FIG. 4 is a block diagram of this type of double-tap transversal filter, in which 21 is an input terminal of the transversal filter, 22□ to 22. , is a delay memory that holds data, 23. 23.1 is a multiplier that holds a filter coefficient value, and 24 is a multiplier 23.1. ~23゜1
An adder 25 is an output terminal of a transversal filter. 1-If the input of the Lanceversal filter is Xo and the output is Yn, then Yll = Σ
ar"X11-(... (2) where a is the coefficient value of the transversal filter. The input signal X of this transversal filter
. is a signal with zero values inserted by interpolator 2, so
Among the product-sum calculations shown in equation (2), the product-sum calculation for zero-value input signals can be omitted. The number of non-zero output signals from the interpolator 2 is every M, and every M filter coefficient values are required to be used in the actual calculation of the transversal filter.

FIG. 5 is an explanatory diagram showing the input and output signals of each part of the sampling frequency converter when L=5 (indicating that the thinner 4 samples and extracts every L=5) and M=4. , and n represents a sampling point with a time interval of T1/4.

Assuming that the number of taps of the transversal filter is 30,
The output signal Y at time n is obtained by omitting the product-sum operation for zero-value input signals, Yゎ = Σ a4s・Xゎ-, 3... (
3) More required. Similarly, Y n+ I HY n +
2, Y,,+2 is y n+1 = Σ
a 4j + 4 ° X n -4j...
(4) Ym+2=Σ a 4j+x°X n −4
J... (5) Y i+, =: Σ a 4J43 ” Xl
+-4J... (6) Obtained from the following. Next output signal Y. +4 can be obtained using the same filter coefficient value (a<x l j=o~7) as in equation (3). From now on, by cyclically using the four filter coefficient values of equations (3) to (4),
The following output signal is required. Therefore, f□: f2=L:
When M, the filter coefficient value is divided into M ways and used cyclically.

The output signal of the low-pass filter 3 is extracted once every L times in the decimator 4, and the sampling frequency f2 is
is output as a signal.

When executing the above sampling frequency converter algorithm on a digital processor, the general method is to convert the processing period of the digital processor to the sampling period T1/M after interpolation.
There is a method of processing as (=T2/L).

FIG. 6 is a flowchart when such a conventional sampling frequency converter algorithm is executed on a digital processor. To explain this, step 5TII
~Step STI 3 is the process at the time of initialization, first,
The delay memory, which is used for calculation of the low-pass filter 3 composed of a transversal filter and holds past input data, is cleared (step 5T11), and then the table set of filter coefficient values and the crowd data are cleared. The data input/output counter used to determine the presence/absence is cleared (step 5TI2.13). Next, the presence or absence of input data is determined based on the input counter value (step ST14-), and if there is input data, processing is performed to shift the contents of the delay memory to the next address by one address, Next, a process is performed to write input data to the delay memory of the empty start address (step 5T15). Filter coefficient values used in the calculation of the low-pass filter 3 are cyclically selected based on the input counter value (step 5T16). Next, a transversal filter with low-pass characteristics is operated using the selected filter coefficient value, and output data is calculated.Step 5T17), sampling frequency Lf2 (=Mf
Since the output data of the low-pass filter 3 in 1) needs to be thinned out once every L times, it is necessary to judge whether or not to output the data based on the output counter value.Step 5T
I8), if output is required, output the data converted to the sampling frequency f2 (step 5TI9). Next, T1/
Step 5T20) + If there is an interrupt, determine whether there is an interrupt with a period of M (= T 2 / r-).
After incrementing the input counter value by 1, the process returns to the processing block again (step 5T21).

Thereafter, the processes from step 5T14 onwards are repeatedly executed.

In the conventional example described above, the calculations that require the longest processing time are the delay memory shift processing in step 5T15 and the 1-Herrance versatile filter calculation in step 5T17. If the number of taps of the filter is K, then (3
) to (5), the maximum number of product-sum calculations required for transversal filter calculations is (
[K/M co+1). Here, the symbol [a] is a function that gives an integer value obtained by truncating the fractional part of a.

Therefore, the amount of computation required for the processing period T□/M is [K/M] for the shift 1 to number of times of the delay memory, and [K/M]+1 for the number of product-sum operations of the transversal filter. Converting this to the processing cycle T2 per sample of output data, the number of shifts of the delay memory is L・[K/M], and the number of product-sum calculations of the transversal filter is L・([K/M] +1).

[Problem to be solved by the invention]

Conventional sampling frequency converters using digital processors are configured as described above, so they perform filter calculations even when no data is output, and perform complex operations such as determining the presence or absence of input/output data and selecting filter coefficient values. This invention was made to solve the above problems, and can reduce the amount of calculations. Another object of the present invention is to obtain a sampling frequency converter that can perform sampling frequency conversion using an algorithm that does not require complicated processing.

[Means to solve the problem]

In the sampling frequency converter according to the present invention, the ratio of the sampling frequency of the second sampling frequency to the second sampling frequency is a first natural number and a second sampling frequency.
When expressed as a ratio to a natural number, the processing period for frequency conversion is a common multiple of the processing period of each node 1 and the second processing period for the first sampling frequency and the second sampling frequency, Between an input buffer that stores input signals for the first natural number and two consecutive input signals input to the input buffer sofa, zero-value signals of a number one less than the second natural number are sent at equal time intervals. an interpolator to be inserted; a low-pass filter for removing aliasing noise included in the output signal of the interpolator; and a second sampling frequency for extracting the output signal of the low-pass filter every first natural number. and a decimator, the output signal of the nuclear decimator is stored in an output buffer for the second natural number, and a signal of the second sampling frequency is output every second processing cycle. It is something.

[Effect]

The sampling frequency converter according to the present invention stores the input data in the first natural number in the manual buffer, with the processing period of the digital processor being set as a predetermined common multiple such as the least common multiple of the processing period of the input buffer and the processing period of the output buffer. Then, the output data is stored in the output buffer for the second natural number, and the filter operation is performed only for M pieces of the output data value after thinning, and it is also possible to determine the presence or absence of input/output data. It does not require selection of filter values, and functions to significantly reduce the calculation time per sample of output data.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of the sampling frequency converter when the processing period is LTl. In the figure, 1 is the input terminal, and the signal of the first sampling frequency f□ input from this is input to the input buffer 6. is stored in Here, input buffer 6
When L pieces of input data (L is a first natural number) are stored in , the L pieces of data are collectively input to the interpolator 2 . The interpolator 2 receives the sampling frequency f from the input buffer 6,
By inserting a zero value signal between each signal, the sampling frequency Lf
Thereafter, the low-pass filter 32 decimator 4 operates in the same manner as before, and the second sampling frequency f2 is converted to the second sampling frequency f2.
M signals (M is a second natural number) are output. The M output signals are accumulated in the output buffer 7 and are sequentially output from the output buffer 7 in T2 periods.

FIG. 2 is a flowchart when the processing of the sampling frequency converter shown in FIG. 1 is executed by a digital processor. In FIG. 2, steps STI, ST2
is an initialization process, first clearing the input delay memory that holds input data (step 5TI),
Next, a table of filter coefficient values is set (step 5T2). Next, L pieces of input data are collectively written from the input buffer 6 to the delay memory, and past input data necessary for calculation of the low-pass filter 3 is shifted (step 5T3). Further, calculations of a transversal filter having low-pass characteristics are performed at once on M pieces of data output after thinning (step 5T4). The M pieces of output data are output to the output buffer 12-A7 in step ST3 (step 5T5). Next, it is determined whether there is an interrupt in the LT1 cycle (T□ is the first processing cycle) which informs the processing cycle of the digital processor, and if there is an interrupt, the process returns to step ST3. Thereafter, the processes from step ST3 to step ST6 are repeatedly executed.

In this embodiment, the calculations that require the most processing time are the delay memory shift processing in step ST3 and the transversal filter calculation in step ST4, as in the conventional case. Therefore, the amount of calculation required during the processing period LT1 is the number of shifts of the delay memory L・[K/M]
, the number of product-sum operations of the transversal filter is M・(
[K/M]+1). Converting this to the processing cycle T2 per sample of output data, the number of shifts of the delay memory is L/M・[K/M], and the number of product-sum operations of the 1-lance universal filter is [K/M]+1. Become.

Comparing the amount of calculation required during the second processing period T2 between the conventional example and the example, the amount of calculation in the example is reduced to 1/M by the number of shifts of the delay memory, and the amount of calculation required for the sum-of-products calculation of the I-ransversal filter is It can be seen that the number of times is reduced to 1/L.

In the above embodiment, a transversal filter is used as the low-pass filter 3, but other filters having low-pass characteristics, such as a comb filter, may be used.

Further, in the above embodiment, the processing cycle of the digital processor is set to the least common multiple N of T□ and T2, but it may be a common multiple of T1 and T2.

〔Effect of the invention〕

As described above, according to the present invention, the processing cycle of the digital processor is set to a common multiple N of T
Since the filter operation is performed only on the second natural number of output data values after thinning, it is easy to determine the presence or absence of input/output data and select filter values. The present invention has the effect that the computation time per sample of output data can be significantly reduced compared to the conventional method without requiring the following.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a sampling frequency converter according to an embodiment of the present invention, FIG. 2 is a flowchart showing the procedure of sampling frequency conversion processing according to the present invention, and FIG. 3 is a conventional sampling frequency converter. 4 is a block diagram showing the 1-rance versal filter used in FIG. 3, FIG. 5 is an explanatory diagram showing input and output signals of each part of the sampling frequency converter shown in FIG. 3, FIG. 6 is a flowchart showing the procedure of conventional sampling frequency conversion processing. 2 is an interpolator, 3 is a low-pass filter, 4 is a decimator, 6
is the input buffer, and 7 is the output buffer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A sampling frequency converter that converts an input signal sampled at a first sampling frequency to an output signal sampled at a second sampling frequency, the first sampling frequency and the second sampling frequency. can be expressed as the ratio of the first natural number and the second natural number, then the processing cycle for frequency conversion is expressed as
an input buffer that stores the first natural number of input signals as a common multiple of each first processing period and second processing period with respect to the sampling frequency and the second sampling frequency;
an interpolator that inserts zero-value signals, the number of which is one less than the second natural number, at equal time intervals between two consecutive input signals that are input to the input buffer; and a loop included in the output signal of the interpolator. a low-pass filter for removing noise; a decimator for extracting the output signal of the low-pass filter at intervals of the first natural number to obtain a second sampling frequency; 1. A sampling frequency converter comprising: an output buffer that stores a natural number of 2 sampling frequencies and outputs a signal of the second sampling frequency every second processing cycle.