JPS61150325A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61150325A
JPS61150325A JP27602384A JP27602384A JPS61150325A JP S61150325 A JPS61150325 A JP S61150325A JP 27602384 A JP27602384 A JP 27602384A JP 27602384 A JP27602384 A JP 27602384A JP S61150325 A JPS61150325 A JP S61150325A
Authority
JP
Japan
Prior art keywords
layer
substrate
layers
susceptor
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27602384A
Other languages
Japanese (ja)
Inventor
Minoru Ikeda
稔 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27602384A priority Critical patent/JPS61150325A/en
Publication of JPS61150325A publication Critical patent/JPS61150325A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To heat an irradiated object to a high temperature in a short period for preventing metal layers from being polycrystallized, by successively vapor depositing Ti and Pt layers in amorphous state on a substrate, adhering an Au layer thereon and then holding the substrate with a carbon susceptor for lamp annealing it. CONSTITUTION:After finishing the wafering process for forming a laser diode, an InP substrate 11 is provided with Ti and Pt layers by vapor depositing Ti and Pt as anode electrode metals successively in that order in amorphous state, and an Au layer is adhered thereon. The substrate 11 is hold by a carbon susceptor 12a on a quartz jig 13. All these elements are received in the atmosphere of nitrogen within a quartz tube 15 and heated by a lamp heating unit 10. The temperature of the susceptor 12 is measured by a thermocouple 14. In this manner, the heat treating time can be reduced so that gold is prevented from projecting through the Pt and Ti layers during the heat treatment and that the metal layers are prevented from being polycrystallized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置にオーミックコンタクトを形成する
方法に関わり、特に赤外線レーザ装置の化合物半導体材
料にオーミックコンタクトを形成する方法に関わるもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of forming an ohmic contact in a semiconductor device, and particularly to a method of forming an ohmic contact in a compound semiconductor material of an infrared laser device.

I n + −X G a * A S + −y″p
、四元化合物を活性領域とする赤外線レーザは、光通信
システムの光源として多用されている。該レーザの一例
として1.3μm V S Bレーザと呼ばれるものの
断面構造が第2図に示されているが、同図の1′はレー
ザダイオ−Vのカソード電極モあって、n−1nP基板
側から順にNi、Ge、Auを積層したものである。
I n + −X G a * A S + −y″p
Infrared lasers with quaternary compounds as active regions are frequently used as light sources in optical communication systems. As an example of such a laser, the cross-sectional structure of what is called a 1.3 μm V SB laser is shown in Fig. 2. In the figure, 1' is the cathode electrode of the laser diode-V, which is connected from the n-1nP substrate side. Ni, Ge, and Au are laminated in this order.

一方、アノード例の電極はp型I n+−xGa、As
1〜。
On the other hand, the electrode of the anode example is p-type I n+-xGa, As
1~.

27層6上にTi層?、Pt層8.Au層9を順次蒸着
し、アニールして形成したものである。
27 Ti layer on layer 6? , Pt layer 8. It is formed by sequentially depositing Au layers 9 and annealing them.

図に示されたその他の部分は、1,3.3’がn−1n
P、2.5がp−InP、4がn−1nGaAsPであ
り、4′は活性層であるn−1nGaAsP層である。
For the other parts shown in the figure, 1,3.3' is n-1n
P and 2.5 are p-InP, 4 is n-1nGaAsP, and 4' is an n-1nGaAsP layer which is an active layer.

6はp−1nGaAsPコンタクト層で、これとTi層
7との間にオーミックコンタクトが形成される。
6 is a p-1nGaAsP contact layer, and an ohmic contact is formed between this and the Ti layer 7.

電極材料である上記金属層を熱処理することによってオ
ーミック化が行われる。通常この熱処理はレーザを形成
した半導体基板を抵抗炉中に挿入することによって実行
されるが、その場合の処理条件は、例えば430℃で3
0分といったものであり、長時間高温に保持される結果
、金が半導体材料中に拡散し、素子特性を劣化させるこ
とがしばしば起こっている。
The metal layer, which is the electrode material, is made ohmic by heat-treating the metal layer. Normally, this heat treatment is performed by inserting the semiconductor substrate on which the laser is formed into a resistance furnace, and the treatment conditions in that case are, for example, 430°C and 30°C.
As a result of being kept at a high temperature for a long time, gold often diffuses into the semiconductor material and deteriorates the device characteristics.

この、半導体材料中への金拡散が特に問題になるのはア
ノード側である。カソード側では電極金属tillから
活性層4′迄の距離がn−1nP基板1の存在によって
大きな値となっているのに対し、アノード側では間に存
在する層は全て薄り、短時間のうちに金がpt層、Ti
層や半導体層を突き抜けて活性層4′に到達する。
This gold diffusion into the semiconductor material is particularly problematic on the anode side. On the cathode side, the distance from the electrode metal till to the active layer 4' becomes a large value due to the presence of the n-1nP substrate 1, while on the anode side, all the layers existing in between become thin and Gold is the PT layer, Ti
It penetrates through the layers and semiconductor layers and reaches the active layer 4'.

このような事情であるから、電極コンタクトを完全にオ
ーミック化し、然も金が活性層まで拡散しない熱処理条
件は極めて厳密なものであり、その制御を困難なものと
している。
Because of these circumstances, the heat treatment conditions for making the electrode contact completely ohmic and preventing gold from diffusing into the active layer are extremely strict, making it difficult to control.

〔従来の技術〕[Conventional technology]

従来は上記の如く、温度及び時間の厳しい条件を満足す
べく制御を行っており、従って歩留まりは十分に高いも
のではなかった。
Conventionally, as described above, control was performed to satisfy strict conditions of temperature and time, and therefore the yield was not sufficiently high.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

オーミック化の熱処理中に金がpt層、Tt層を突き抜
けるのが問題であるから、金層を被着する前にオーミッ
ク化の熱処理を行うことが考えられるが、皮膜形成工程
と熱処理工程を混在させるのは作業効率の点から好まし
いことではない。
Since the problem is that gold penetrates the PT layer and Tt layer during heat treatment for ohmic formation, it is possible to perform heat treatment for ohmic formation before depositing the gold layer, but the film forming process and the heat treatment process may be mixed. It is not desirable from the point of view of work efficiency to do so.

本発明者の知見によれば、金がpt層、Ti層を通過し
て拡散するのは、熱処理によってこれ等の金属層がアモ
ルファス状態から多結晶に変換される故である。即ち、
多結晶化によって生じた結晶粒界を通過して金が拡散す
る速度が速いのであって、アモルファス状態のままであ
れば金の拡散速度は小に抑えられ、レーザダイオードの
特性を劣化させることはない。
According to the findings of the present inventors, the reason why gold diffuses through the PT layer and the Ti layer is because these metal layers are converted from an amorphous state to a polycrystalline state by heat treatment. That is,
Gold diffuses quickly through the grain boundaries created by polycrystallization, and if it remains in an amorphous state, the diffusion rate of gold can be kept low, and the characteristics of the laser diode will not deteriorate. do not have.

従って、これ等の金属層の多結晶化を防止すれば良いこ
とになるが、その為にはオーミック化処理の時間を短縮
することが有効である。
Therefore, it is sufficient to prevent these metal layers from becoming polycrystalline, but for this purpose it is effective to shorten the time for the ohmic processing.

〔問題点を解決するための手段〕[Means for solving problems]

上記の問題点は、特許請求の範囲の項に記された本発明
の方法によって解決されるものであるが、本発明は後出
の実施例に従って要約すると、Ti層、pt層を順次ア
モルファス状態に蒸着し、その上にk u iiを被着
した後、基板をカーボン類のサセプタで保持してランプ
アニールを行うものである。
The above-mentioned problems are solved by the method of the present invention described in the claims, but the present invention can be summarized according to the embodiments described later. After depositing ku ii on it, lamp annealing is performed while holding the substrate with a susceptor made of carbon.

(作用) 本発明、に使用されるランプ加熱は極めて短時間に被照
射物体を高温にするので、処理時間が短縮され、従って
アモルファス層の単結晶化が進行しない。
(Function) Since the lamp heating used in the present invention brings the irradiated object to a high temperature in a very short time, the processing time is shortened, and therefore the amorphous layer does not become single crystallized.

〔実施例〕〔Example〕

第1図は本発明が実施されている状態を示す断面図であ
る。
FIG. 1 is a sectional view showing a state in which the present invention is implemented.

レーザダイオード形成のためのウェファプロセスを終了
し、アノード側電極金属としてTi層。
The wafer process for forming the laser diode is completed, and the Ti layer is used as the anode side electrode metal.

pt層を順次アモルファス状態に蒸着し、その上にAu
層を被着した状態のInP基板11をカーボン類のサセ
プタ12が保持し、これは更に石英治具13によって支
持されている。これ等の全体は窒素雰囲気の石英管15
内に置かれ、ランプ装置10によって加熱される。14
は熱電対で、サセプタの温度を測定することによってI
nP基板の温度を監視するために設けられている。
PT layers are sequentially deposited in an amorphous state, and Au
A carbon-based susceptor 12 holds the InP substrate 11 with the layer deposited thereon, which is further supported by a quartz jig 13 . All of these are quartz tubes 15 in a nitrogen atmosphere.
and heated by the lamp device 10. 14
is a thermocouple, which measures the temperature of the susceptor.
It is provided to monitor the temperature of the nP substrate.

上記各金属層の形成方法及び厚さはつぎ通りである@G
+−1nGaAsPコンタクト層の上に被着されるTi
層は、電子ビーム蒸着装置を用いて、1000人の厚さ
に堆積される。続いてptli)が同じ装置によって1
000人の厚さに堆積される。Au層は電界めっきによ
り3μの厚さに被着される。
The formation method and thickness of each of the above metal layers are as follows @G
+-1nTi deposited on top of the GaAsP contact layer
The layers are deposited to a thickness of 1000 nm using an electron beam evaporator. ptli) is then 1 by the same device.
Deposited to a thickness of 000 people. The Au layer is deposited by electroplating to a thickness of 3μ.

オーミック化処理である熱処理の条件は、例えば450
℃、5分である。ランプ加熱は極めて短時間のうちに被
照射体を高温にするので、この処理でp−InGaAs
P層とTi層の間にオーミックコンタクトが形成される
。このような5分という短い時間ではTi層、pt層の
多結晶化は進行せず、金原子がこれ等のアモルファス層
を通過して拡散することはない。
The conditions for heat treatment, which is ohmic treatment, are, for example, 450
°C for 5 minutes. Lamp heating raises the temperature of the irradiated object in an extremely short period of time, so this process
An ohmic contact is formed between the P layer and the Ti layer. In such a short time of 5 minutes, polycrystallization of the Ti layer and PT layer does not proceed, and gold atoms do not diffuse through these amorphous layers.

この処理を行う際、InP基板はカーボン類のサセプタ
12によって保持される。通常この種の治具はシリコン
製であるが、本実施例の場合[nP基板表面にはAu層
が存在するので、これをシリコン製のサセプタで保持す
ることは出来ず、カーボン類のものを使用している。
During this process, the InP substrate is held by a susceptor 12 made of carbon. Normally, this type of jig is made of silicon, but in this example [there is an Au layer on the surface of the nP substrate, it cannot be held with a silicon susceptor, and a carbon-based jig is used]. I am using it.

この後、カソード側の電極形成を行うが、該工程はNi
、Ge、Auを順次蒸着し380tで1分間ランプ加熱
することによってオーミックコンタクトを形成するもの
である。この加熱時間も十分短いのでTi層、pt層の
多結晶化は進行しない。これらの金属皮膜の厚さはいず
れも2000人である。
After this, the electrode on the cathode side is formed, but this step is performed using Ni.
, Ge, and Au are sequentially deposited and heated with a lamp at 380 t for 1 minute to form an ohmic contact. Since this heating time is also sufficiently short, polycrystallization of the Ti layer and PT layer does not proceed. The thickness of these metal films is 2000 mm.

〔発明の効果〕〔Effect of the invention〕

以上述べた如く、本発明ではオーミック化の熱処理が短
時間に完了するので、アモルファス状の電極金属の多結
晶化が進行せず、金原子が活性領域に拡散侵入すること
がない。そのためレーザダイオードの性能を劣化させる
ことがなくなるので、製造歩留まりが向上する。
As described above, in the present invention, since the heat treatment for ohmic conversion is completed in a short time, polycrystallization of the amorphous electrode metal does not proceed, and gold atoms do not diffuse into the active region. Therefore, the performance of the laser diode is not degraded, so that the manufacturing yield is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明が実施されている状態を示す断面図、 第2図は半導体レーザの構造例を示す断面図であって、 図に於いて 1、3.3’はn−1nP層 1′  はAu−Ge−Ni1in型電極2.5  は
p−1nP層 4   はn−InGaAsP層 4′  は活性層であるn−InGaAsP層6   
はp−InGaAsPコンタクト層7   はTi層 8   はpt層 9   はAu層 10  はランプ加熱装置 11  は電極金属層を有するInP基板12  はカ
ーボン製サセプタ 13  は石英治具 14  は熱電対 15  は石英管である。 $2図
FIG. 1 is a sectional view showing a state in which the present invention is implemented, and FIG. 2 is a sectional view showing an example of the structure of a semiconductor laser. ' is the Au-Ge-Ni1in type electrode 2.5 is the p-1nP layer 4 is the n-InGaAsP layer 4' is the active layer n-InGaAsP layer 6
is a p-InGaAsP contact layer 7 is a Ti layer 8 is a PT layer 9 is an Au layer 10 is a lamp heating device 11 is an InP substrate with an electrode metal layer 12 is a carbon susceptor 13 is a quartz jig 14 is a thermocouple 15 is a quartz tube It is. $2 figure

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板表面の半導体材料層上に、該半導体材
料に対しオーミックコンタクトを形成すべき金属或いは
合金層をアモルファス状に被着し、該アモルファス状の
金属或いは合金層上に金を被着した後、前記半導体基板
を赤外線を透過する材料から成るサセプタによって保持
し、赤外線を照射して熱処理を行う工程を有することを
特徴とする半導体装置の製造方法。
(1) A metal or alloy layer to form an ohmic contact with the semiconductor material is deposited in an amorphous form on the semiconductor material layer on the surface of the semiconductor substrate, and gold is deposited on the amorphous metal or alloy layer. After that, the semiconductor substrate is held by a susceptor made of a material that transmits infrared rays, and heat treatment is performed by irradiating the semiconductor substrate with infrared rays.
(2)前記アモルファス状の金属或いは合金層が被着さ
れる半導体材料はIn_1_−_xGa_xAs_1_
−_yP_y四元化合物半導体であることを特徴とする
特許請求の範囲第1項記載の半導体装置の製造方法。
(2) The semiconductor material on which the amorphous metal or alloy layer is deposited is In_1_-_xGa_xAs_1_
-_yP_y A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a quaternary compound semiconductor.
(3)前記アモルファス状の金属或いは合金層は、チタ
ンと白金を連続して堆積したものであることを特徴とす
る特許請求の範囲第2項記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 2, wherein the amorphous metal or alloy layer is formed by successively depositing titanium and platinum.
(4)前記サセプタの材料はカーボンであることを特徴
とする特許請求の範囲第1項記載の半導体装置の製造方
法。
(4) The method for manufacturing a semiconductor device according to claim 1, wherein the material of the susceptor is carbon.
JP27602384A 1984-12-25 1984-12-25 Manufacture of semiconductor device Pending JPS61150325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27602384A JPS61150325A (en) 1984-12-25 1984-12-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27602384A JPS61150325A (en) 1984-12-25 1984-12-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61150325A true JPS61150325A (en) 1986-07-09

Family

ID=17563713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27602384A Pending JPS61150325A (en) 1984-12-25 1984-12-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61150325A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04320387A (en) * 1991-03-26 1992-11-11 American Teleph & Telegr Co <Att> Manufacture of article having semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04320387A (en) * 1991-03-26 1992-11-11 American Teleph & Telegr Co <Att> Manufacture of article having semiconductor element

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