JPS61150198A - Non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To make a chip size in forming an integrated circuit small by providing one high voltage distributing circuit every plural column selecting lines or lines and disposing a decoder for operating newly a selecting FET. CONSTITUTION:Since high voltage distributing circuits 721-72i are provided in common, respectively, every four pairs of lines R1-R4, R5-R8,...Rm-3-Rm, respectively, the number of this high voltage distributing circuit can be reduced to 1/4 of the conventional device. To the conventional device, it is required that four circuits of decoders 90 are newly added. In an ordinary EPROM, the number of the high voltage distributing circuits is extremely large. Accordingly, by reducing the number of the high voltage distributing circuit, even if the four circuits of the decoders 90 are newly added, the number of elements as a whole can be drastically decreased comparing to the convention.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device using nonvolatile memory cells.

[Technical Preface to the Invention II] Recently, nonvolatile semiconductor memory devices that have a floating gate structure and can electrically erase and write stored information have changed to ultraviolet erasable type devices that have a conventional floating gate structure. Instead, it is becoming popular. Memory cells used in such storage devices (hereinafter referred to as memories) are made of thin oxide films,
For example, electrons are injected into and released from the floating gate through a silicon oxide film with a thickness of about 100 to 200 mm using the Fowler-Nordheim tunnel effect. Therefore, since almost no current is consumed at this time, a voltage booster circuit is provided inside the memory, and information is written or erased as described above using the boosted voltage from this circuit. Therefore, for example, 5
Since it is only necessary to supply a power supply voltage of V, it is very easy for memory users to use.

The structure of a memory cell used for such applications is shown in FIGS. 3(a) to 3(d). Note that FIG. 3(a) is a pattern plan view of this memory cell, FIG. 3(b) is a cross-sectional view taken along line AA' in FIG. 3(a), and FIG. FIG. 3(d) is a cross-sectional view taken along line B-8' in FIG. 3(a), and FIG. 3(d) is a cross-sectional view taken along line C-C' in FIG. 3(a).

In FIG. 3, 101 is a source region, 1o2 is a drain region, 103 is a floating gate electrode made of, for example, polycrystalline silicon and kept in an electrically floating state;
Reference numeral 4 denotes a control gate electrode made of polycrystalline silicon or the like. A relatively thick insulating film 106 such as a silicon oxide film is interposed between the floating gate electrode 1i 103 and the semiconductor substrate 105 and between the floating gate electrode 103 and the control gate electrode ti 104. A relatively thin insulating film 107, such as a silicon oxide film, is interposed between a part of the drain region 103 and a part of the drain region 102.

In a memory cell with such a configuration, the control gate electrode 10
4 to increase the potential of the floating gate electrode 103 due to capacitive coupling with the floating gate electrode 103.
Electrons are injected into the floating gate electrode 103 at the location of the thin insulating film 101 shown in FIG.

On the other hand, when emitting electrons, the thin insulation II! Electrons are emitted from the floating gate electrode 103 to the drain region 102 via a location 107.

When electrons are injected into the floating gate electrode 1 (13), the threshold voltage of the memory cell is equivalently high, so even if a high voltage is applied to the control gate electrode 104, it will not turn on and the electrons will not be turned on. When it is being emitted, it is turned on, thereby storing "0" level and 1" level information.

By the way, memory is constructed by arranging the above-mentioned memory cells in a matrix in the row and column directions, and it is necessary to write information only to selected cells among them.
It is necessary to selectively apply a high voltage to the fsIII gate electrode and the floating gate electrode. However, in a memory provided with a voltage booster circuit inside the memory, it is necessary to boost a high voltage, for example, 20V, from a NIII voltage, for example, 5V.

An example of such a voltage booster circuit is shown in FIG. 4, and pulse signals φ1. The timing chart of φ2 is shown in FIG. This voltage step-up circuit is a well-known circuit composed of a plurality of enhancement-type MOS transistors 201 that act as diodes and a plurality of capacitors 202, and is configured with a pulse signal φ1. By supplying φ2, the power supply voltage Vc of, for example, 5V is boosted to output a high voltage VH of, for example, 20V. The current supply capacity of the high voltage VH of 20V boosted by this voltage booster circuit is very small. Therefore, when this voltage is selectively applied to memory cells as described above, for unselected memory cells, that is, those whose control gate electrodes are at the "OQ level," the current from the voltage booster circuit is It is necessary to eliminate the leakage and apply a boosted voltage to the selected one.For this reason, the configuration of such a write circuit has become complicated and the number of elements has increased.In conventional memory, this Since such a write circuit is provided for each row line or each column line, there is a drawback that the total number of elements increases, and the chip size when integrated into an integrated circuit increases.

Figure 6 shows a conventional EPR using memory cells as described above.
It is a circuit diagram of OM. In the figure, R1 to Rm are row lines, Dl to [)n are column lines, and each intersection of these row lines R1 to Rm and column lines D1 to On is located at the third
Memory cells TM11 to TMIln with the structure shown in the figure
are provided, and these memory cells TMII to TMn+
The control gates of n are connected to the corresponding row lines R1 to Rm, the drains are connected to the corresponding dead lines Dl to [)n, respectively, and all the memory cells T M 11 to TMa+n
The source of is connected to earth potential. The memory cells TM11 to TMmn constitute a memory cell array 1o.

The row lines R1 to Rm are connected to depletion type (hereinafter referred to as D type) transistors TR1 to TRm, which receive information readout and '/I control signals R/W as gate inputs.
The row decoder 2° is connected to the row decoder 2° through each. This row decoder 20 selects one row line in response to a row address signal, and outputs a high level signal from an output terminal corresponding to the selected row line.

The column lines D1 to On are the enhancement type (hereinafter referred to as E type) column line selection Mo in the dead line selection circuit 30.
It is connected to the signal detection node N1 via S transistors TD1 to TDn.

The signal at this node N1 is detected by the sense amplifier 40, and this detection signal is further output to the outside of the memory via the output circuit 50.

The above column line selection MoS transistors TD1 to TDn
Column selection lines C1 to Cn are connected to the gates of D-type MOS transistors TC1 to TCn whose gates receive the signal R/W.
is connected to column decoder 60 via. This column decoder 60 selects one column selection line C in response to a column address signal, and outputs a high level signal from the output terminal corresponding to the selected column selection line.

When writing information to the memory cell TM, the write circuit 70 selects the high voltage V)I for writing information obtained by the voltage booster circuit of FIG. 4 for the row line R and column selection line C. A total of (n+m) boosted voltage distribution circuits 711 to 71 and 721 to 121 are provided corresponding to column selection lines C1 to Cn and row lines R1 to Rm, respectively. There is. Each of these boosted voltage distribution circuits 71 and 72 includes four D-type MOS transistors TWI to TW4 and 1, as exemplified by the boosted voltage distribution circuit 721 connected to the row line R1.
E-type MOS transistor TW5. One end of each of the transistors TW1 and TW2 is connected to a power supply terminal 13 to which the voltage VH is supplied and a power supply terminal 74 to which a normal power supply voltage Vc of, for example, 5V is supplied, and the other ends of each are connected in common. A transistor TW3 is connected between the common connection point 75 and the row mRi.

Both transistors TW1. The gates of TW3 are both connected to the row line R1. Further, the transistor TW4. TW5 is inserted in series, and its series connection point 77 is connected to the gates of the transistors TW2 and TW4.

Note that the gate of the transistor TW5 is connected to the row line R1.

An E-type MOS transistor T1 is connected between the signal detection node N1 and the power supply terminal 78 to which the voltage VH is supplied.
is connected to the gate of the transistor T1, and the signal of the output node N2 of the write information input control circuit 80 is supplied to the gate of the transistor T1.

The write information input control circuit 80 is connected between an internal information generating circuit 81 that receives input information Din and generates internal information din according to the input information Din, and a power supply terminal 82 to which voltage Vc is supplied and a ground potential point. D inserted in series with
type MOS transistor T2 and El' type MOS transistor T3. A Nant gate circuit 83 consisting of T4,
It is composed of D-type transistors TW11 to TW13 and E-type transistor TW14, and a voltage output control circuit 84 that controls the output of voltage VH in accordance with the signal at the output node N3 of the Nant gate circuit 83. In the Nant gate circuit 83, the gate of the transistor T2 is connected to its output node N3, the internal information din is supplied to the gate of the transistor T3, and the gate of the transistor T4 is set to 1 when writing information.
A signal fJ/W is supplied which is set to the ``'' level and set to the 0'' level during reading.

In a conventional EPROM having the above configuration, when reading information, the signal R/W goes to a high level ("1'level"), the signal 17/W goes to a low level ("O" level),
The voltage VH at the N source terminal 13 and the like is set to 5V. When the signal R/W is set to high level, the transistor T
CI to TCn and TR1 to TRm are turned on. Further, when the signal /W is set to a low level, the transistor T4 is turned off, and the signal at the output node N3 of the Nant gate circuit 83 is set to a high level. As a result, the signal at the output node N2 of the output control circuit 84 is set to a low level, and the transistor T1 is turned off.

At this time, among the row lines R1 to Rm and the column selection lines C1 to Cn, the row decoder 20 or the column decoder 60
Only those selected by TM are set to high level, and the memory cells TM in the memory cell array 10 located at this intersection are
is selected. If the threshold voltage of the selected memory cell TM is low, this memory cell is turned on and current flows between the drain and source, and the signal detection node N1
is brought to a low level. On the other hand, if information has been written to the selected memory cell TM in advance and the threshold voltage is in a high state, this memory cell is turned off and the signal detection node N1 is turned off by the load inside the sense amplifier 40. be brought to a high level. Therefore, the signal at node N1 at this time is outputted to the outside of the memory via sense amplifier 40 and output circuit 50.

When writing information, the signal R/w goes to low level and the signal @π
/W is set to high level, and VH is set to +20V.

At this time, for example, row 1! If R1 and column selection line C1 are selected, “
1" level voltage is applied to each of the row line R1 and column selection line C1. Then, the boosted voltage distribution circuit 711 in the write circuit 70 connected to the row line R1 and column selection line C1
, 721 outputs a high voltage V)I, and the above row 1i1
R1 and column selection line C1 are each charged to 20V.

At this time, the corresponding output signals of the row decoder 20 and column decoder 60 on the other row lines R and column selection lines C become low level, and the high voltage VH is not outputted from the boosted voltage distribution circuit 71.12. Further, at this time, if the input information Qin is set to a low level, the internal information din is also set to a low level, and the voltage Vc supplied to the power supply terminal 82 is outputted to the node N3. Therefore, the voltage at the output node N2 of the voltage output control circuit 84 is set to VH, and the transistor T1 is turned on. Then, the transistor TD1 controlled by the selected column selection line C1 is turned on, and the column line D1 is charged to a high voltage. Therefore, a high voltage is applied to the control gate of the memory cell TM11 selected by the row line R1 and the column line D1, and a high voltage is also applied to the drain. Information is written by injecting electrons through the Fowler-Nordheim tunnel effect. If the input information Din is at a high level, the transistor T1 is cut off, so a high voltage is not applied to the drain of the memory cell TM11, and no information is written.

Further, once information has been written in a memory cell, the information continues to be stored unless it is erased, so the storage state of the information becomes non-volatile.

[Problems with the Background Art] In the conventional EPROM, the write circuit 70 includes a circuit boost voltage distribution circuit 71 corresponding to each row line and column line.
Or it is necessary to provide 72. For this reason, there is a drawback that the total number of elements increases, and the chip size when integrated into a circuit increases.

[Object of the Invention] This invention has been made in consideration of the above circumstances, and its purpose is to provide a non-volatile semiconductor memory device that can be integrated into a smaller chip size than before. It is about providing.

[Summary of the Invention M] In order to achieve the above object, in the nonvolatile semiconductor memory device of the present invention, a plurality of row lines and column lines are provided to intersect with each other, and the means for retaining charges is formed by a gate. A memory cell array is constructed by arranging nonvolatile memory cells provided in an insulating film at each intersection of the plurality of row lines and column lines, each of the plurality of column lines is selected by a plurality of column selection lines, and the a plurality of write high voltages for selecting one or both of the row line and column selection line with a first decoder and generating write high voltages used when writing information to each of the plurality of memory cells; A generation circuit is provided, one end of each of the plurality of selection elements is commonly connected to a corresponding one of the plurality of write high voltage generation circuits, and the other end is connected to a corresponding one of the row line and column selection line. and a portion of the address signal supplied to the first decoder is supplied to a second decoder to selectively operate the plurality of selection elements based on the output signal of the second decoder. I have to.

According to such a configuration, the number of high voltage generation circuits for writing can be reduced compared to the conventional one, and thereby the chip size can be made smaller than the conventional one.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a nonvolatile semiconductor memory device of the present invention implemented in an EPROM in the same manner as in the prior art. Note that in this embodiment circuit, the memory cell array 1
0, column line selection circuit 30, sense amplifier 40, output circuit 5
Although the 01 column decoder 60, write information input control circuit 80, transistor T1, etc. are omitted, these are provided in the same way as the conventional circuit shown in FIG.

The memory of this embodiment differs from the conventional one in that the boosted voltage distribution circuits 71 or 72 are not provided in the number of column selection lines C or row lines R, but are provided for each of a plurality of column selection lines C or row lines R. One step-up voltage distribution circuit is provided, and four new decoders 901 to 904 are provided.

In the write circuit 70, there are provided i boosted voltage distribution circuits 721 to 721, each configured in the same manner as the conventional one. And R1 among m row lines R1 to Rm
or R4 is an E-type MOS transistor TWR for selection.
The row lines R5 to R8 are connected in common to the one boosted voltage distribution circuit 721 via the respective E-type MOS transistors TWR21 for selection.
or TWR 24 respectively, and the four row lines R are connected in common to the one boosted voltage distribution circuit 722 through each of the four selection E-type MOS transistors TWR. rows IIRm-3 to Rm are E-type MOS transistors TWRi1 to TWRi4 for selection.
The one step-up voltage distribution circuit 721 via each
are commonly connected.

The above transistors TWR11, TWR21,...TW
The signal H1 output from the decoder 901 is input to the gate of Rll, and the signal H2 output from the decoder 902 is input to the gates of the transistors TWR12, TWR22,...TWRi2. Tora>Jisu9TWR13,TWR23,...TWR
The gate of i3 receives the signal H output from the decoder 903.
3 is the transistor TWR14, TWR24, . . .
- The signal H4 output from the decoder 904 is input in parallel to the gate of TWRi4.

The four decoders 901 to 904 have the same circuit configuration, and as illustrated in the decoder 904, the source and drain are inserted between the power supply terminal 91 to which the voltage Vc is applied and the node N11. A D-type MOS for load whose gate is connected to the above node N11.
The transistor T11 is inserted in series between the node N11 and the ground potential, and each gate receives a row address signal R.
A1. RA2. Signal 'f2/W which is set to "0" level when reading information and set to "1" level when writing information
E-type MoS transistors T12 each supplied with
．． A Nant gate circuit 92 consisting of T13°T14,
A voltage output 1IJf11 circuit 93 configured similarly to the voltage output control circuit 84, consisting of D-type transistors TW11 to TW13 and E-type transistor TW14.
It is made up of. The voltage output control circuit 93 is supplied with a signal from a node N11 which is the output node of the NAND gate circuit 92.

The other decoders 902 to 904 also use the decoder 901.
However, the decoder 903 receives the address signals RAl and RA2 instead of the address signals RAI and RA2.
However, the decoder 902 receives the address signal RA1. R.A.
The decoder 901 receives RAl and RA2 instead of address signals RA1 and RA2.
``2 are each supplied.

Note that, for example, when the row decoder 20 is configured with a NAND type circuit, the row address signals RA1 and RA2 are the same as the address signals used when the row decoder 20 selects the row lines R1, R5, and '.Rm-3. Yes, RAl, RA2 are the same as the address signals when the row decoder 20 selects the row lines R2, R6-1...Rm-2, and RAl, RA2
is the same as the address signal when the row decoder 20 selects the row lines R3, R7, . . . Rm-1, and RAl, R
A2 is the same as the address signal used when the row decoder 20 selects the row lines R4, R8, . . . Rm. If the row decoder 20 is constituted by a NOR gate type circuit, the input address signals may all be of opposite phase.

That is, the address signals for selecting the row lines RM, Rs, . . . Rm-3 are RAl and RA2.

In such a configuration, when reading information, the signal 17
Since /W is set to “On level,” each decoder 90
All of the transistors T14 from 1 to 904 are turned off, and the node N11 is set to the "1" level. As a result, each transistor TW14 in the voltage output control circuit 93 of each decoder 901 to 904 is turned on, and the signal H1 is turned on.
or H4 becomes the "0'° level. Then, the selection transistors TWR11 to TWR14, TWR21 to TWR24, . . . TWRll to TWRi
4 are all off, row lines R1 to Rm are row decoder 2
It is selectively driven according to the output of 0.

Since the signal 17/W is at the "1" level when writing information, all transistors T14 in each of the decoders 901 to 904 are turned on. If, for example, one row line R4 is selected by the output of the row decoder 20 at this time, the same row address signal RA1. In the decoder 904 to which RA2 is supplied, transistors T12 and T13 are both turned on. As a result, only the signal at the output node N11 of the Nant gate circuit 92 in the decoder 904 is brought to the "O" level.

Then, the subsequent transistor TW12 in the voltage output control circuit 93 is turned on, and the signal H4 is first set to the "1" level. Furthermore, the gate of the transistor TW11 is approximately O.
Therefore, if the absolute value of the threshold voltage of this transistor TW11 is smaller than Vc, this transistor T
W11/ is turned off, and transistor TW12. is connected to the output node N12. A high voltage (■) is outputted via the TW13. At this time, in other decoders 90 to 903, transistors T12. Since one of the transistors T13 is cut off and the signal at the output node N11 of the Nant gate circuit 92 is set to the "1" level, the transistor TW14 is turned on and the signals H1 to H3 are all set to the "0" level. Also, at this time, high voltage VH is applied to transistor TW12 in decoders 901 to 903;
The fundductance Q1 of the transistor TW11 is TW13.
If it is made sufficiently larger than the transistor 9. TWll
The common connection node N13 of and TW12 has a voltage of approximately Vc. Here, the gate of transistor TW12 is approximately OV
Therefore, if the threshold voltage of the D-type transistor is lower than Vc, the D-type transistor is turned off, and in these decoders 901 to 903, the voltage output control circuit 9
3, there is no current outflow from the high voltage VH.

Therefore, when the signal H4 is made high voltage, the selection transistor TWR whose gate is supplied with this signal
14, TWR24, . . . TWRi4 are respectively turned on.

Here, in the row lines R1 to R4, the row lines R1 to R
3, the selection transistors TWR11 to TWR13, each of which is connected at one end, are turned off and disconnected from the boosted voltage distribution circuit 721. and row line R4
Only the boosted voltage distribution circuit 72 . connected to. This boost voltage distribution circuit 72
1, the transistor TW5 is turned on by the 1" level signal on the row line R4, which causes the gate of the transistor TW2 to be set to the "0" level, and at the same time, the transistor TW is turned on.
1 is turned on, the transistor TW2 is turned off, and the node N20 to which the gate of the transistor TW5 is connected is turned on.
is a transistor TW1. High voltage Vo is supplied via TW3. Therefore, after this, row line R4 is charged to high voltage VH.

Here, for the other four row lines, for example R5 to R8, R
The row line R8 is separated from the boosted voltage distribution circuit 722 by the selection transistors TWR21 to TWR23, which are turned off, and only the row line R8 is connected to the boosted voltage distribution circuit 722 via the transistor TWR24.
Connected to 2. However, this row line R8 is the row decoder 2.
Since it is not selected by 0, this row line R8 is “0”.
” level, and this row 1 is output from the boost voltage distribution circuit 722.
No high voltage is supplied to IR8. Note that the same applies to each of the other four sets of row lines. Therefore, no current flows out from the high voltage in the boosted voltage distribution circuits 722 to 72L.

Therefore, after this, information is written into the memory cell located at the intersection of the selected column line (not shown) and the row line R4 to which the high voltage VH is selectively supplied.

In this way, in the above embodiment, one boosted voltage distribution circuit is commonly provided for each of the four row lines R1 to R4, R5 to R8, and Rm-3 to Rm, so that the boosted voltage The number of distribution circuits is reduced to 1/4 of the conventional one.
can be reduced to By the way, in the apparatus of this embodiment, it is necessary to add four new circuits of decoders 90 compared to the conventional apparatus. However, in a typical EPROM, the number of row lines R is extremely large, and correspondingly, the number of boosted voltage distribution circuits is also extremely large. Therefore, by reducing the number of boosted voltage distribution circuits, even if four new decoders 90 are added, the overall number of elements is significantly reduced compared to the conventional one. Therefore, when this memory is integrated into an integrated circuit, the chip size can be made smaller than before.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, the 2-pit row address signal RA1. R.A.
2 is supplied to each decoder 90, every four row lines R are grouped together into a set, and a boost voltage distribution circuit is provided in common for each row line of each set. The row line R is set to 8 using the pit row address signal.
Each book may be combined into a set, and a boosted voltage power distribution may be provided in common for each set of row lines.

Further, in the above embodiment, the case where the boosted voltage distribution circuit to which the row IR is connected is provided in common for a plurality of row lines has been described, but this can be similarly implemented for the column selection line. It may be implemented for both row lines and column selection lines.

FIG. 2 is a circuit diagram showing the configuration of a modified example of the invention.

In the above embodiment, a boosted voltage distribution circuit 72 as shown in the figure was used, but in place of the circuit 72, an E-type transistor 301. 302 and a capacitor 3G3, one voltage booster circuit 304 is provided for each of the four row lines,
The output of the oscillation circuit 400 may be supplied to each end of the capacitor 303 via an inverter 305 to which the high voltage Vp is supplied.

In such a configuration, the output signal from the oscillation circuit 400 is converted into a high voltage Vp signal φ by the inverter 305, and is supplied to one end of the capacitor 303 in the voltage boosting circuit 304. In the voltage boosting circuit 304, the voltage Vp supplied via the transistor 301 is boosted by capacitive coupling of the capacitor 303, and this boosted voltage is rectified by the transistor 302 and supplied to one row line R.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can be integrated into a smaller chip size than before.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
3 is a sectional view showing the structure of a memory cell, FIG. 4 is a circuit diagram showing an example of a voltage boosting circuit, and FIG. 5 is a circuit diagram showing a configuration according to a modified example of the present invention. FIG. 6 is a timing chart of signals that control the operation, and is a circuit diagram showing the configuration of a conventional EPROM. 10...Memory cell array, 20...Row decoder,
30... Column line selection circuit, 40... Sense amplifier, 5
0... Output circuit, 60... Column decoder, 70...
Write circuit, 72... Boost voltage distribution circuit, 80...
・Write information input control circuit, 90... decoder, 92
... Nant gate circuit, 93... Boost voltage distribution circuit, TWR... MOS transistor for selection, R...
Row line, D...column line, C...column selection line. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Part 3 (b)

Claims (3)

[Claims] (1) A plurality of row lines and column lines are provided to intersect with each other, and a nonvolatile memory cell in which a means for retaining charge is provided in a gate insulating film is connected to each of the plurality of row lines and column lines. A memory cell array arranged at the intersection,
a plurality of column selection lines for selecting each of the plurality of column lines; a first decoder for selecting one or both of the row lines and column selection lines; a plurality of write high voltage generation circuits that generate write high voltages used for writing, and one end of which is commonly connected to a corresponding one of the plurality of write high voltage generation circuits;
A plurality of selection elements whose other ends are connected to corresponding ones of the row line and column selection line, and a part of the address signal supplied to the first decoder are supplied, and based on this signal, the A nonvolatile semiconductor memory device comprising: a second decoder that selectively operates a plurality of selection elements. (2) The first decoder is either a row decoder or a column decoder, and the other ends of the plurality of selection elements are connected to either the row line or the column selection line. The nonvolatile semiconductor memory device described in 2. (3) The high voltage generation circuit for writing is constituted by a voltage boosting circuit that outputs the high voltage for writing in accordance with the signals of the corresponding one of the row line and column selection line. The nonvolatile semiconductor memory device described in .