JPH11250682A - Semiconductor memory and semiconductor device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory for enhancing the degree of freedoms of designing a layout capable of driving at a low voltage without using a charge pump for a high voltage decoder. SOLUTION: A row decoder supplies a voltage of a power source voltage or lower to a source line S and a word line WL in response to rewriting, erasing or reading of data for a memory cell of an EEPROM. The one decoder is provided for a line group of two word lines WLO, WL1 and one common source line S1 as one set. A plurality of high voltage decoders 104 for supplying high voltages from a high voltage generator 110 to the line group are provided. The high voltage decoder 104 has a p-type semiconductor switch 120 for connecting an output of the generator 110 to a midway of a supply line to the word line and the common source, and a level shifter 130 for turning ON, OFF the switch 120 based on the output of the row decoder. The shifter 130 has a first n-type semiconductor switch 132, a first p-type semiconductor switch 134 and a second p-type semiconductor switch 136.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device requiring a high voltage when rewriting and erasing data.

[0002]

2. Description of the Related Art As this kind of semiconductor memory device, an EEPROM (Electrically Erasable), which is a flash memory,
Programmable Read-only Memory). FIGS. 8 and 9 show two types of flash memory circuit layouts. In the type shown in FIG. 8, a row decoder 302 and a booster circuit 304 are arranged on one side, for example, the left side of the memory element array region 300. In the type shown in FIG. 9, a row decoder 302 is arranged, for example, on the left side of the memory element array area, and a booster circuit 304 is arranged, for example, on the right side of the memory element array area 300.

The type shown in FIG. 9 has a higher degree of freedom in circuit layout and is easier to design than the type shown in FIG.

Here, as a booster circuit used in the type shown in FIG. 9, a booster circuit disclosed in US Pat. No. 4,511,811 is known, and a circuit diagram thereof is shown in FIG.
In FIG. 10, when the word line 8 is not selected, the potential of the word line 8 is OV, and the node 42 also becomes OV.
The gate of the transistor 44 is connected to the node 42, and its source and drain are connected to the oscillator 38. The output of the oscillator 38 is a rectangular wave having a peak value Vdd. In order to turn on the transistor 44, the voltage at the node 42 is a voltage (Vdd + Vth) obtained by adding the output voltage Vdd of the oscillator 38 to the threshold voltage Vth44 of the transistor 44.
44) Must be at least. Therefore, when the word line 8 is not selected, the transistor 44 does not turn on and the oscillator 38
No coupling occurs between the node and the node 42. In addition, since 0 V is applied to the gate of the transistor 46, the transistor 46 does not turn on and no current flows through the word line 8.

On the other hand, the word line 8 is connected to the row decoder 30 of FIG.
2, the potential becomes almost the power supply voltage Vdd due to the parasitic capacitance CWL of the word line 8. Here, assuming that the output voltage of the high voltage generation circuit 34 is 15 V,
The voltage of the source line 52 of the transistor 50 functioning as a diode becomes 13.5 V due to the drop of the threshold voltage of the transistor 50. This voltage is applied to the drain of transistor 40. Assuming that the power supply voltage Vdd applied to the gate of the transistor 40 is 5 V and the threshold voltage of the transistor 40 is 0.5 V, the potential of the source of the transistor 40, that is, the potential of the node 42 is 4.5.
V.

Here, assuming that the threshold voltage of the transistor 46 is 1 V, when the voltage of the node 42 becomes 6 V (5 V of the word line 8 + 1 V of the threshold of the transistor 46) in the initial state, the transistor 46 is turned on. Then, the word line 8 is boosted. The voltage of the node 42 is determined by the ratio of the capacitance of the transistor 44 to the capacitance of the transistor 46. When the voltage of the peak value Vdd from the oscillator 38 is applied to the transistor 44, the voltage of the node 42 is increased from 4.5V. It is possible to increase to 6V.

Thereafter, as the boosted voltage of the word line 8 is continuously applied to the transistor 40, the voltage of the node 42 is increased while being pumped as shown in FIG. 11, and the potential of the word line 8 is correspondingly increased. Going up.

The increase in the potential of the node 42 and the potential of the word line 8 shown in FIG. 11 will be described in more detail. The transistor 44 functions as a MOS capacitor, and its capacitance becomes effective under the condition that its gate voltage is VG,
The source voltage (equal to the drain voltage VD) is VS,
Assuming that the threshold value is Vth44, VG-VS> Vth44.

The transistor 40 is an intrinsic transistor (normally, the threshold value Vth40 is substantially 0 V). When back-by-ice of about 13.5 V is applied to this transistor 40, its threshold Vt
h40 = about 0.5V. On the other hand, transistors 46,
50 are both enhancement transistors whose thresholds Vth46 and Vth50 are usually 0.5V to 0.5V.
The voltage is 8 V, but becomes about 1.5 V when a back bias of about 15 V is applied.

When the word line 8 is not selected, the transistor 40 does not turn on because the potential of the word line 8 is 0V. On the other hand, when the word line 8 is selected,
Is approximately Vdd, the potential of the node 42 via the transistor 40 becomes Vdd-Vth40. However, at this time, since the back bias to the transistor 40 is substantially 0 V, the threshold value Vth40 of the transistor 40 is substantially 0 V, and the potential of the node 42 is substantially Vdd (see FIG. 11). This state is the initial state of the potential of the node 42, and the clock from the oscillator 38 is low (0 V).
And

Next, when the clock from the oscillator 38 becomes high (Vdd), the potential of the node 42 becomes Vdd + αV
dd (α is the pumping efficiency), and the word line 8
Is supplied with a voltage of approximately Vdd + αVdd−Vth46 (see FIG. 11).

Thereafter, when the clock from the oscillator 38 becomes low, the potential of the node 42 becomes Vdd + αVdd−Vt.
The voltage drops to h46, and the MOS capacitor 44 is charged with this voltage.

Thereafter, when the clock goes high again,
The potential of the node 42 further rises by αVdd, and thereafter, the above operation is repeated by the change of clock high / low. Thus, the potential of the word line 8 is sequentially increased, and the gate potential of the transistor 40 is also increased, so that the transistor 40 easily passes a voltage close to the high voltage Vpp. Finally, the potential of the word line 8 becomes almost equal to Vpp−Vth50−Vth40 + αVdd−Vth
It becomes 46.

[0014] Incidentally, a technology substantially similar to the above is described in the 1983 IEE.
E Internatinal Solid-State Circuits Conferance DIG
EST OF TECNICAL PAPERS, pages 167 and 169.

[0015]

If the booster circuit shown in FIG. 10 is employed to adopt the layout of the type shown in FIG. 9, the following problems occur.

(1) It is necessary to make the breakdown voltage of the element connected to the node 42 in FIG. 10 excessively high.

As described above, the voltage at node 42 gradually increases, and finally the voltage at node 42 becomes Vpp-Vth.
50−Vth40 + αVdd. Therefore, this node 4
2, the drain withstand voltage of the transistor 46 and the MOS capacitor 4
It is necessary to set the gate withstand voltage of No. 4 to a value higher than the maximum voltage of the node potential.

(2) The circuit shown in FIG. 10 cannot be driven at a low voltage.

A back bias of 15 V or more is applied to the n-type transistor 46, and the threshold value of the transistor 46 increases. When the word line 8 is boosted, the transistor 4
Since a drop voltage corresponding to the threshold value of 6 occurs, the voltage of the node 42 must be further increased. Node 42
In order to increase the voltage, the amplitude of the clock from the oscillator 38 must be increased, and as a result, the power supply voltage Vdd needs to be increased.

(3) The circuit shown in FIG. 10 further includes, in addition to the high voltage generating circuit 34 composed of multi-stage charge pumps,
One stage charge pump for pumping is required for each word line 8. Even with the charge pump required for each word line 8, the conversion efficiency α is less than 1, and conversion loss occurs.

(4) In the circuit of FIG. 10, pumping is performed according to a clock, so that it takes time to boost the word line to a high voltage.

(5) Transistor 40 in circuit of FIG.
However, in order to avoid the loss of the boosted voltage, the transistor is an insiclic transistor, which requires an extra ion implantation step in a semiconductor manufacturing process.

(6) Transistor 44 in circuit of FIG.
Since is used as a capacitor, the area is larger than that of other transistors, and as a result, the area occupied by the booster circuit is increased.

As described above, the above-described problem has occurred in the booster circuit for realizing the layout shown in FIG.

It is an object of the present invention to provide a semiconductor memory device which can be driven at a low voltage without using a charge pump for each word line and has a high degree of freedom in layout design, and a semiconductor device using the same. It is in.

It is another object of the present invention to provide a semiconductor memory device having a low element breakdown voltage and easy to manufacture, and a semiconductor device using the same.

Another object of the present invention is to provide a semiconductor memory device which can reduce the area occupied by each high voltage decoder and a semiconductor device using the same.

[0028]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory elements each having a source / drain region, a floating gate, and a control gate. A row decoder selectively supplying a plurality of voltages equal to or lower than a first voltage to a plurality of word lines connected to the control gate and extending in a row direction in accordance with rewriting, erasing, and reading of data to the first memory; A high-voltage input terminal to which a second voltage higher than the second voltage is input, and one high-voltage input terminal arranged for at least one boosted line of the plurality of word lines, and And a plurality of high-voltage decoders for selectively boosting the plurality of boosted lines based on the voltage of the high-voltage input line. A p-type semiconductor switch provided midway the supply line which connects the child at least one of the boosted line, the gate potential of the p-type semiconductor switches,
A level shifter for level-shifting between an on-potential and an off-potential based on the output of the row decoder.

The invention of claim 7 defines the invention in which the boosted line in the invention of claim 1 is used as a source line. The invention of claim 1 includes a semiconductor memory device of a type in which the source line does not extend in the row direction. As this type of semiconductor memory device, there is a type in which all source regions are set to the same potential.

According to the first aspect of the present invention, a p-type semiconductor switch is provided in the supply path between the high voltage input terminal and the boosted line, and its gate potential is turned on by the level shifter based on the output from the row decoder. The potential is switched to the off potential. When a p-type semiconductor switch is used, a voltage drop corresponding to the threshold voltage does not occur in the high voltage supply path, so that it is not necessary to output an excessively high voltage in the high voltage generation circuit. In addition, since the level shifter is driven based on a voltage equal to or lower than the first voltage from the row decoder, low voltage driving is possible. In addition, since each of the plurality of high-voltage decoders does not require a charge pump, it does not require time to boost the boosted line, and no conversion loss occurs. Further, since a transistor used as a capacitor is not required, the area occupied by each high-voltage decoder can be reduced.

According to a second aspect of the present invention, in the first aspect, the plurality of high-voltage decoders include two word lines that are adjacent in the column direction, and are connected to the two word lines in the column direction. One common source line connected to the source region of the adjacent memory element and one common source line are provided for each line group.

According to the second aspect of the present invention, the data erasing operation can be realized by page scanning as described later. In addition, the total number of high voltage decoders can be reduced as compared with the case where a high voltage decoder is provided for each word line. This claim 2 defines a so-called NOR type configuration in which a memory element is connected in parallel to a bit line, but a so-called NAND type or the like in which a memory element is connected in series to a bit line. Needless to say, the present invention can be applied to configurations other than the NOR type.

According to a third aspect of the present invention, in the first or second aspect, the level shifter is provided between the high voltage input terminal and a ground, and based on an output of the row decoder, A first n-type semiconductor switch for supplying the on-potential to a gate, provided between the high-voltage input terminal and the first n-type semiconductor switch, when turned on based on an output of the row decoder; ,
A first p-type semiconductor switch for supplying the off-potential to the gate of the p-type semiconductor switch; and a p-type semiconductor switch provided between the high-voltage input terminal and a gate line of the first p-type semiconductor switch. A second p-type switch, which is turned on and off together with the p-type semiconductor switch, and supplies a potential for turning off the first p-type semiconductor switch to the gate of the first p-type semiconductor switch when the p-type semiconductor switch is on. And a semiconductor switch.

With this configuration, the p-type semiconductor switch can be reliably turned on and off based on the output from the row decoder and the second voltage from the high voltage input terminal. In addition, the element withstand voltage of the first n-type semiconductor switch is required up to the second voltage from the high voltage input terminal, and the element withstand voltage exceeding this is not required. Further, the off state of the first p-type semiconductor switch can be latched by the second p-type semiconductor switch. Therefore, a half-latch type high voltage decoder can be provided.

According to a fourth aspect of the present invention, in the third aspect, the level shifter is provided between a gate line of the first p-type semiconductor switch and ground, and is turned on with the first n-type semiconductor switch. , Further comprising a second n-type semiconductor switch whose off-timing is in opposite phase.

According to the fourth aspect of the present invention, when the second n-type semiconductor switch is turned on, the on-state of the first p-type semiconductor switch can also be latched, thereby providing a complementary high voltage having a full latch function. A decoder can be provided.

The complementary high voltage decoder having the full latch function defined in claim 4 has an advantage that the operation is more stable than the half latch type high voltage decoder defined in claim 3. . In particular, the input voltage from the high-voltage input terminal is 0 V → Vdd → V since the high-voltage generating circuit connected to the high-voltage input terminal is usually constituted by a charge pump.
pp → Vdd → 0V, but even with this voltage change, high stability of the latch state can be ensured.

On the other hand, the half-latch type high voltage decoder defined in claim 3 has the following advantages as compared with the complementary high voltage decoder having the full latch function defined in claim 4.
The number of circuit elements can be reduced, which is advantageous in layout.

According to the fifth and sixth aspects of the present invention, both types of semiconductor memory devices shown in FIGS. 8 and 9 can be realized. In particular, the invention of claim 5 has an effect of increasing the degree of freedom in circuit layout.

According to the present invention, a semiconductor device can be formed by using the semiconductor memory device according to any one of claims 1 to 7.

[0041]

Embodiments of the present invention will be specifically described below with reference to the drawings.

<First Embodiment> First, the first embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS.

(Schematic Description of Semiconductor Memory Device) FIG. 1 shows a semiconductor memory device (EEPROM) according to the first embodiment.
It is a schematic block diagram of. In FIG. 1, for example, a row decoder 102 is arranged on the left side of the memory element array area 100, and a booster circuit 103 is arranged on the right side. The high voltage generating circuit 110 is connected to the boosting circuit 103, and may be provided inside the semiconductor memory device or outside the semiconductor memory device. In any case, the booster circuit 10
3 has a high voltage generating circuit 110 via a high voltage input terminal.
Input a high voltage.

A bit line load circuit 51 and a column gate circuit 50 are provided, for example, below the memory element array area 100. The column gate circuit 50 includes a column decoder 5
2, the bit lines BL0, BL1, B
The connection between L2... And the sense amplifier 56 is switched. The bit line load circuit 51 includes bit lines BL0, B
A plurality of n-type transistors 5 corresponding to L1, BL2,.
1a is provided. The drain of each n-type transistor is connected to a common drain line 60, each gate is connected to each gate line 62 connected to the column decoder 52, and each source is connected to a corresponding bit line BL0, BL1, BL2. ing. The data write timing signal PROG signal is input to the common drain line 60 via the two inverters 64 and 66. The data write timing signal PROG signal becomes, for example, Vdd = 5V at the time of data write (program), and becomes 0V at other times. The input / output circuit 54 outputs the data potential read from any one of the bit lines at the time of data reading, after the data potential is amplified by the sense amplifier 56. The control logic circuit 58 outputs various control signals for controlling the semiconductor memory device based on the chip enable signal CE, the write enable signal WE, the output enable signal 0E, and the like.

(Explanation of Memory Element) In the memory element array area 100 of FIG. 1, the memory elements 10 shown in FIG. 2 are arranged. The memory element 10 is a split gate type (or offset type) semiconductor memory element as shown in FIG. The memory elements 10 are arranged in a large number in the row direction and the column direction in the memory element array area 100 shown in FIG.

The memory element 10 has a source region 12 common to two memory elements adjacent in the column (Y) direction in FIG.
And a drain region 14 and a channel region 16 formed therebetween. On the channel region 16 between the source and the drain, the floating gate 1
8 are formed, and the floating gate 18
The control gate 20 is formed on the upper side via an insulating layer.

The present invention is not limited to the split gate type shown in FIG. 2, but may use a stacked type semiconductor memory device.

As shown in FIG. 3, the control gates 20 of the first cell group, for example, each memory element 10 in the m-th row
Are commonly connected to the word line WLm, and each memory element 1 in the second group, for example, the (m + 1) -th row adjacent to the first cell group
The 0 control gate 20 is commonly connected to the word line WLm + 1. Also, the m-th row (first group) and m +
Source region 12 of each memory element 10 in the first row (second group)
Are commonly connected to a source line Sn. The drain region 14 of each memory element in the column (Y) direction, for example, the memory element 10 in the k-th column is connected to the bit line Bk.

In the present embodiment, all the memory elements 10 belonging to the first and second groups (for example, the word lines WL0, WL0,
WL1, all memory elements 1 connected to common source S1
Scanning for selecting (0) collectively is called page scanning or sector scanning, and the data erasing operation is performed by page scanning (sector scanning).

The operation of writing (programming), erasing, and reading data from and to the memory element 10 will be described below.

Here, for erasing and writing data, 2
There are the following standards, and these are shown below as standards 1 and 2. In each of the standards 1 and 2, the state of the data after data erasure is defined as data "1".

(Standard 1) Erase operation: The state is such that charges are removed from the floating gate 18 shown in FIG.

Write operation for setting data to 0: charge is injected into the floating gate 18.

Write operation for setting data to 1: The charge of the floating gate 18 is kept at the time of erasure.

(Standard 2) Erase operation: a state in which charges are injected into the floating gate 18.

Write operation for setting data to 0: Charge is removed from floating gate 18.

Write operation for setting data to 1: The charge of the floating gate 18 is kept at the time of erasure.

Next, based on the standard 1, the memory device 10
The respective operations of data erasing, writing, and reading will be described. The address of the memory element 10 is indicated by (X, Y), and data is erased by one page scan. However, in the following description, the address (0, 0) and the address (0, 1) adjacent in the Y direction will be described. For the memory element 10 of FIG. In addition, data writing and reading are usually performed, for example, for every 8 bits (for every 8 bit lines), but are performed for 1 bit for convenience of explanation.

In order to carry out the above-described operations, the word line WL0, the word line WL1, the source line S1, the bit line B0
And the voltage of the bit line B1 is as follows.

(1) Data Erase Operation Line Type S1 WL0 BL0 WL1 BL1 Applied Voltage 0V 15V 0V 15V 0V Here, the voltage (0V) of the source line S1 is
2 and the voltages of the word lines WL0 and WL1 (1
5V) is set by the booster circuit 103. The voltages of the bit lines BL0 and BL1 are set as follows. That is, at the time of data erasure, all the n-type transistors 51a in the bit line load circuit 51 of FIG. When data is erased, PR
Since the OG signal is 0 V, each n-type transistor 51a
Has a source potential of 0V. Therefore, the bit lines BL0, BL0,
BL1 becomes OV.

In this case, a high electric field is generated between the control gate 20 and the floating gate 18 shown in FIG. 2, and electrons accumulated in the floating gate 20 escape to the control gate 20 side to erase data.

(2) Data Write Operation (2-1) When Writing Data 0 to Memory Element 10 at Address (0,0) In this case, voltages applied to the bit line BL and the word line WL are as follows. Becomes

Line type S1 WL0 BL0 Other word line Other bit line Applied voltage 12V 2V 0V 0V 4V Here, the voltage (12V) of the source line S1 is
3, the potential (2 V) of the selected word line WL0 and the potential (0 V) of the other word lines are set by the row decoder 102, respectively. In addition, bit line B
The voltages of L0 and BL1 are set as follows. That is, when data 0 is written to the memory element 10 at the address (0, 0), only the n-type transistor 51a connected to the bit line BL0 among the n-type transistors 51a in the bit line load circuit 51 of FIG. Is turned off, and all the other n-type transistors 51a are turned on. The source potential of the other n-type transistor 51a turned on is PRO
Since the G signal is Vdd, Vdd−Vth51a = 4V
Becomes Therefore, the potentials of the other bit lines are 4V. On the other hand, the potential of the bit line BL0 is set as follows. The bit line BL0 is connected to an input / output circuit 54 via a column gate circuit 50 based on an output signal from the column decoder 52.
Connected to. Here, a transistor (not shown) connected to an input / output line to the column gate circuit 50 is arranged in the input / output circuit 54, and the transistor is turned on based on a signal input to the input / output circuit 54. Therefore, bit line B
LO is set to a low level via a transistor in the input / output circuit 50.

In this case, strong capacitive coupling occurs between the floating gate 18 and the source region 12 of the memory element 10 at the address (0, 0), and the potential of the floating gate 18 becomes about 10V. Therefore, a part of the electrons flowing from the drain region 14 to the source region 12 is injected into the floating gate 18 as channel hot electrons, and the writing is performed. Therefore, at the time of subsequent reading, no channel is formed below the floating gate 18 and no current flows from the drain region 14, so that the data becomes 0.

(2-2) When data 0 is not written in the memory element 10 at the address (0, 0) In this case, the voltages applied to the bit line BL and the word line WL are as follows.

Line type S1 WL0 BL0 Other word line Other bit line Applied voltage 12V 2V 4V 0V 4V When data 0 is not written in the memory element 10 of the address (0,0), the case of (2-1) The difference is that all the n-type transistors 51a in the bit line load circuit 51 of FIG. 1 are turned on based on the output from the column decoder 52. Therefore, the potential of the bit line BL0 becomes 4 V as in the other bit lines.

In this case, unlike the case of (2-1),
No electrons are injected into the floating gate 18 of FIG. Therefore, at the time of subsequent reading, a channel is formed below the floating gate 18 and the drain region 1 is formed.
4, a current flows and data 1 can be read.

The signals applied to the transistors arranged in a matrix in the memory element array area 100 are (WL, BL) = (2V, 0V), (0V, 4
V), (2V, 4V), and (0V, 0V). Then, data 0 is written only at (2V, 0V), and (0V, 4V), (2V, 4V),
In the case of (0V, 0V), none of the data remains unchanged at the time of erasure.

(3) Data Read Operation Line Type S1 WL0 BL0 Applied Voltage 0V 4V 2V or 0V In this case, the source line S1 and the word line WL0 are set to the above potentials based on the output of the row decoder 102. Also,
N-type transistor 51 in bit line load circuit 51 of FIG.
a, only the n-type transistor 51a connected to the bit line BL0 is turned off, and the other n-type transistors 51a
a are all turned on. Because the PROG signal is 0V,
The source potential of the other n-type transistor 51a turned on becomes 0V, and the potential of the other bit lines becomes 0V. When reading data from the memory element 10 at the address (0,0), only the bit line BL0 is connected to the sense amplifier 56 via the column gate circuit 50. Therefore, depending on the write state of (2-1) or (2-2), the bit line BL0
Output 0V or 2V. That is, if electrons are not accumulated in the floating gate 18, a channel is formed below the floating gate 18, a current flows from the drain region 14, and data 1 (2V) can be read. Conversely, the floating gate 18
If no electrons are stored in the floating gate 18, no channel is formed below the floating gate 18 and no current flows from the drain region 14, so that data 0 (OV) can be read. This data potential is amplified by the sense amplifier 50 of FIG. 1 and output to the outside via the input / output circuit 54.

(Description of Configuration for Setting Voltage of Word Line and Source Line) As described above, the source line S1 and the word line WL
The set voltages of 0 and WL1 require a voltage equal to or lower than the power supply voltage (for example, 5 V) and voltages higher than 12 V and 15 V. Hereinafter, a configuration for applying a predetermined voltage to the source line and the word line for each of the above operations will be described with reference to FIG.

As shown in FIG. 3, memory element array region 1
For example, a row decoder 102 is provided on the left side with respect to 00, and a booster circuit 103 is provided on the right side. The row decoder 102 applies a voltage lower than a power supply voltage to a source line and a word line according to various operation states. The booster circuit 103
A voltage exceeding a power supply voltage is applied to a source line and a word line according to various operation states. The booster circuit 103 roughly includes one high voltage generation circuit 110 and a plurality of high voltage decoders 104.

Hereinafter, details of the booster circuit 103 having the characteristic configuration of the present embodiment, particularly, the high voltage decoder 104 will be described with reference to FIG.

As shown in FIG. 3, each high voltage decoder 104 has two word line examples adjacent in the column (Y) direction,
A voltage exceeding a power supply voltage is applied to one source line connected to the source region 12 of each memory element 10 connected to the two word lines.

As a structure commonly connected to each high-voltage decoder 104, as shown in FIG.
And a high voltage generation circuit 110 including a regulator 108. As the high voltage Vpp from the regulator 108, a high voltage 12V supplied to the source line S at the time of data writing and a high voltage 15V supplied to the word line WL at the time of data erasing are obtained.

As is well known, the charge pump 106 is configured by arranging unit charge pumps in multiple stages. The charge pump 106 receives the power supply voltage Vdd and the clock CLK, and outputs a high voltage equal to or higher than the high voltage Vpp obtained from the regulator 108.
The regulator 108 receives the output voltage from the charge pump 106, the data write timing signal PROG and the data erase timing signal ERASE, and outputs the two types of high voltages Vpp described above.

Next, details of each high voltage decoder 104 to which the high voltage Vpp from the high voltage generation circuit 110 is input will be described with reference to FIG. Here, since each of the high-voltage decoders 104 has the same configuration, the high-voltage decoder 104 connected to the source lines WL0 and WL1 and the source line S1 will be described below.

The high voltage decoder 104 includes an output line 111 of the high voltage generation circuit 110 and source lines WL0 and WL1.
And a first common line 112 connecting the source line S <b> 1 and a p-type semiconductor switch 120. When the p-type semiconductor switch 120 is turned on, the high voltage generation circuit 110
Is supplied to the source lines WL0 and WL1 and the source line S1.

Particularly, in the present embodiment, in the high-voltage decoder 104, only the p-type semiconductor switch 120 exists in the middle of the path for supplying the high voltage Vpp to the source lines WL0, WL1 and the source line S1. Therefore, FIG.
As compared with the conventional technology having the n-type semiconductor switch 46 in the middle of the supply path as in the prior art of No. 0, a voltage drop by the threshold voltage Vth due to the n-type semiconductor switch 46 does not occur. In particular, a back bias of 10 V or more is applied to the n-type transistor 46 in FIG. 10, the threshold voltage of the transistor 46 increases, and the above-mentioned voltage drop increases. On the other hand, in the embodiment of the present invention, there is no need to generate a higher voltage in consideration of the above-mentioned voltage drop as the high voltage Vpp output from the high voltage generation circuit 110, and low voltage driving becomes possible.

In the middle of the source lines WL0, WL1 and the source line S1, semiconductor switches 122, 124, 126 for selectively supplying the high voltage Vpp are provided, respectively. The voltage wlhv applied to the gates of the semiconductor switches 122 and 124 becomes, for example, 17 V when the data erase timing signal ERASE is high, that is, at the time of data erase, and the semiconductor switches 122 and 124 are turned on. The voltage shv applied to the gate of the semiconductor switch 126 is the data write timing signal PROG
Is high, that is, for example, 14 when writing data.
V, and the semiconductor switch 126 is turned on.

Therefore, at the time of data writing, a high voltage Vpp = 12 V is supplied to the source line S1 via the high voltage generating circuit 110, the p-type semiconductor switch 120 and the semiconductor switch 126. On the other hand, when data is erased, the high voltage generation circuit 110 and the p-type semiconductor switch 12
0 and the high voltage Vpp = 15 V are supplied to the word lines WL0 and WL1 via the semiconductor switches 122 and 124, respectively.

To turn on / off the p-type semiconductor switch 120, a level shifter 130 for changing the level of the voltage applied to its gate is provided.

The level shifter 130 includes a first n-type semiconductor switch 132 for turning on the p-type semiconductor switch 120 at the time of data writing and data erasing, and a first and second type for turning off the p-type semiconductor switch 120 at other times.
It has second p-type semiconductor switches 134 and 136. The first p-type semiconductor switch 134 and the first n-type semiconductor switch 132 are connected to the output line 112 of the high voltage generation circuit 110.
And a line 113 connecting the ground and the ground. Note that an n-type semiconductor switch 138 that is always on is connected to the line 113 between the first p-type semiconductor switch 134 and the first n-type semiconductor switch 132.

The second p-type semiconductor switch 136
Is connected between the output line 111 of the high voltage generation circuit 110 and the gate line 114 of the first p-type semiconductor 134. The common gate line 115 of the p-type semiconductor switch 120 and the second p-type semiconductor switch 136 is
-Type semiconductor switch 134 and second n-type semiconductor switch 1
38 is connected in the middle of the line 113.

Here, according to the present embodiment, the second p
Even if the type semiconductor switch 136 is turned on, the gate line 114
Is Vpp, and the withstand voltage of the n-type semiconductor switch 140 connected to the gate line 114 is Vpp. Thus, unlike the conventional n-type transistors 44 and 46 in FIG. 10, an element withstand voltage higher than Vpp is not required. . First n-type semiconductor switch 132 and n-type semiconductor switch 138
Since the potential of the line 113 is Vpp at the maximum,
No device breakdown voltage exceeding pp is required.

The gate line 114 of the first p-type semiconductor switch 134 is connected to the gate line 116 of the first n-type semiconductor switch 132 through the n-type semiconductor switch 140.
And becomes the common gate line 117. The common gate line 117 is connected to the second source line WL0, WL1 and the source line S1 via the n-type semiconductor switch 142.
, And to ground via an n-type semiconductor switch 144.

Signals of opposite logic are input to the gates of the n-type semiconductor switches 142 and 144, and when one of them is on, the other is off. That is, a NOR circuit 146 to which two data write timing signals PROG and two data erase timing signals ERASE are input;
A first inverter 148 is provided. The output of the inverter 148 is supplied to the n-type semiconductor switch 142 as it is.
Route applied to the gate of the second inverter 15
0 and a route to be applied to the gate of the n-type semiconductor switch 144.

(Steps of Boosting Word Line and Source Line) Next, the operation of boosting the word line and source line to a voltage value exceeding the power supply voltage will be described.

(Word line boosting operation at the time of data erasing) This data erasing operation is performed in units of one page. For example, all memory elements 10 connected to word lines WL0 and WL1 are connected.
Is erased.

At this time, the row decoder 102 shown in FIG.
OV is supplied to the source line S1, and the word lines WL0, W
A voltage (Vdd-Vth) obtained by subtracting the threshold voltage Vth of an n-type semiconductor switch (not shown) in the row decoder 102 from the power supply voltage Vdd (for example, 5 V) is supplied to L1. Further, the data erase timing signal ERASE goes high, and the data write timing signal PROG goes low. Further, the voltage wlhv applied to the gates of the semiconductor switches 122 and 124 in the middle of the word lines WL0 and WL1 becomes 17V.

With the above setting, the high voltage generation circuit 110
Generates Vpp = 15V, which is supplied to the output line 111. In the high-voltage decoder 120, the semiconductor switches 122 connected to the word lines WL0 and WL1,
124 is turned on, and the semiconductor switch 126 connected to the source line S1 is turned off. Further, the n-type semiconductor switch 142 is turned on, and the n-type semiconductor switch 144 is turned off.

Therefore, the voltage (Vdd-Vth) supplied to the word lines WL0 and WL1 is supplied to the first n-type semiconductor via the second common line 118, the common gate line 117 and the gate line 116. 132.

Thus, the first n-type semiconductor switch 1
32 switches from off to on. Note that the gate potential of the first n-type semiconductor switch 132 is equal to the voltage (Vdd
−Vth) or more. Therefore, the first n-type semiconductor switch 132 does not need to have a high breakdown voltage unlike the conventional n-type semiconductor switch 46 shown in FIG.

When the first n-type semiconductor switch 132 is switched from off to on, the potential of the gate line 115 of the p-type semiconductor switch 120 and the second p-type semiconductor switch 136 becomes low level, and these switches 120 and 136
Turns on. Further, the second p-type semiconductor switch 136
Is turned on, the potential of the gate line 114 of the first p-type semiconductor switch 134 becomes Vpp, and the first p-type semiconductor switch 134 is turned off. The off state of the first p-type semiconductor switch 134 is latched when the second p-type semiconductor 136 is turned on and the first n-type semiconductor switch 132 is turned off. On the other hand, the first n-type semiconductor switch 132 and the second p-type semiconductor switch 136 do not contribute to the ON state of the first p-type semiconductor switch 134. In this sense, the high-voltage decoder 104 can be called a half-latch type.

When the p-type semiconductor switch 120 is turned on, the potentials of the word lines WL0 and WL1 are changed via the semiconductor switches 122 and 124 and the first common line 112 to the potential of the output line 111 of the high voltage generating circuit 110. Pulled by 1
The voltage is boosted to 5V.

The above-described data erase operation can be performed by boosting the word lines WL0 and WL1.

(Step-up operation at the time of data writing) This data writing operation is performed for each memory element 10 connected to the word line WL selected by the row decoder 102, for example, for the memory element 10 connected to the word line WL0.
The operation of writing data to the memory will be described.

At this time, the same voltage (Vdd-Vth) as the voltage supplied to the word lines WL0 and WL1 at the time of data erasing is supplied to the source line S1 from the row decoder 102, and 2 V is supplied to the word line WL0. You. Further, the data erase timing signal ERASE goes low and the data write timing signal PROG goes high. Further, the voltage shv applied to the gate of the semiconductor switch 126 in the middle of the source line S1 is set to 14V.

With the above setting, the high voltage generation circuit 110
Generates Vpp = 12V, which is supplied to the output line 111. In the high-voltage decoder 120, the semiconductor switch 126 connected to the source line S1 is turned on,
The semiconductor switches 122 and 124 connected to the word line WL1 and the word line WL0 are turned off. Further, the n-type semiconductor switch 142 is turned on, and the n-type semiconductor switch 1 is turned on.
44 is turned off.

Therefore, the voltage (Vdd-Vth) supplied to the source line S1 is applied to the first n-type semiconductor 132 via the second common line 118 and the gate line 116.

The subsequent operation is the same as the operation at the time of data erasing. When the p-type semiconductor switch 120 is turned on,
The potential of the source line S1 is pulled by the potential of the output line 111 of the high voltage generation circuit 110 via the semiconductor switch 126 and the first common line 112, and is boosted to 12V.

The above-described data write operation can be performed by boosting the source line S1.

(Data Read Operation) This data read operation is performed for each memory element 10 connected to the word line WL selected by the row decoder 102. For example, the data read operation is performed for the memory element 10 connected to the word line WL0.
The operation of reading data from the memory will be described.

At this time, it is not necessary to boost the word line WL0 and the source line S1 by the high voltage generation circuit 110. Therefore, the high voltage V
No pp is generated, and the high voltage decoder 104 does not operate.

When data is read, row decoder 102
Thus, OV is supplied to the source line S1 and the word line WL
0V is supplied with 4V. The data erase timing signal ERASE and the data write timing signal PR
OG goes low. Further, the word lines WL0, WL
1 and the voltage wl applied to the gates of the semiconductor switches 122, 124, 126 connected in the middle of the source line S1.
Both hv and shv become 0V.

At the time of data reading, the word line W
A voltage of Vdd + Vth (Vth is a threshold value of a transistor in the row decoder 102) or the like may be supplied to L0.
In this case, the selection voltage output from the row decoder 102 to the word line is different between reading and writing / erasing.

With the above setting, the high voltage generation circuit 110
In this case, since both the data erase timing signal ERASE and the data write timing signal PROG are non-active, the high voltage Vpp does not occur.

In the high voltage decoder 120, the semiconductor switches 122, 124 and 126 connected to the word lines WL0 and WL1 and the source line S1 are turned off. further,
The n-type semiconductor switch 142 is turned off, and the n-type semiconductor switch 144 is turned on.

Thus, a low-level voltage is applied to the gates of the first p-type semiconductor 134 and the first n-type semiconductor 132 via the common gate line 117 and the gate lines 114 and 116.

As a result, the first p-type semiconductor 134 is turned on, and the first n-type semiconductor 132 is turned off. Therefore, the potential of the gate line 115 of the p-type semiconductor switch 120 and the second p-type semiconductor switch 136 becomes high level, and the switches 120 and 136 are turned off.

By the above operation, word lines WL0, WL
1 and the source line S1 are connected to the high voltage generation circuit 11
It is not boosted by 0.

As described above, according to the present embodiment, since each of the plurality of high-voltage decoders 104 does not require a charge pump, it takes time to boost the word line and the source line to a high voltage. And no conversion loss occurs.

<Second Embodiment> Next, a description will be given of a second embodiment of the present invention in which the configuration of the high-voltage decoder is changed from the first embodiment.

(Configuration of High Voltage Decoder) FIG. 5 is a circuit diagram of a high voltage decoder according to the second embodiment of the present invention.

While the high voltage decoder 1040 of FIG. 4 according to the first embodiment is a half latch type, the high voltage decoder 200 according to the second embodiment has a complementary type having a full latch function. Are included. In FIG. 5, components having the same functions as the members shown in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 5, the configuration of a portion different from that of FIG. 4 will be described. The third and fourth inverters 202 and 202 are provided between the gate line 116 of the first n-type semiconductor switch 132 and the common gate line 117. 204 is provided. The logic level input to the gate of the first n-type semiconductor switch 132 is the same as the logic level of the common gate line 117 itself even if two inverters 202 and 204 are added. Therefore, the operation of the first n-type semiconductor switch 132 is the same as the case of FIG.

On the other hand, the gate line 114 of the first p-type semiconductor switch 134 is grounded via a newly provided second n-type semiconductor switch 210. The output of the third inverter 202 is input to the gate line 212 of the second n-type semiconductor switch 210.

(Operation of High Voltage Decoder During Data Erase and Data Write) In this case, the first n-type semiconductor switch 132 is turned on, and the second n-type semiconductor switch 210 is turned on.
Turns off. Since the first n-type semiconductor switch 132 is turned on, the gate potentials of the p-type semiconductor switch 120 and the second p-type semiconductor switch 136 become low level,
These switches 120 and 136 are turned on. Thereby, the high voltage Vpp from the high voltage generation circuit 110 is supplied to the word lines WL0, WL1 or the source line S1. Also, the second p-type semiconductor switch 136 turns on,
Further, since the second n-type semiconductor switch 210 is off, the gate potential of the first p-type semiconductor switch 134 is maintained at a high level, and the off state of the first p-type semiconductor 134 is latched.

(Operation of High Voltage Decoder During Data Reading) In this case, the first n-type semiconductor switch 132 is turned off, and the second n-type semiconductor switch 210 is turned on. Since the second n-type semiconductor switch 210 is turned on, the gate potential of the first p-type semiconductor switch 134 becomes low level. As a result, the first p-type semiconductor switch 134 is turned on and the first n-type semiconductor switch 132 is turned off, so that the p-type semiconductor switch 120 and the second
Of the p-type semiconductor switch 136 is maintained at a high level. As a result, each of those switches 120,
136 is turned off, and the voltage supply route from the high voltage generation circuit 110 is cut off.

When the second n-type semiconductor switch 210 is turned on and the second p-type semiconductor switch 136 is turned off, the gate potential of the first p-type semiconductor switch 134 is maintained at a low level. The ON state of the first p-type semiconductor switch 134 is latched.

As described above, the first p-type semiconductor switch 1
It is possible to latch both the on and off states of C.

<Third Embodiment> FIG. 6 shows a third embodiment of the present invention in which the circuit arrangement of FIG. 8 is realized by using the high voltage decoder 104 or 120 shown in FIG. 4 or FIG. FIG. 3 is a schematic explanatory diagram of such a semiconductor memory device.

According to the layout of FIG. 6, a row decoder 102 and a booster circuit 103 are arranged at one end in the row direction where word lines and source lines extend in a memory element array region 100 in which a large number of memory elements 10 are arranged. Have been.

In FIG. 6, a high voltage decoder 104 includes first and second word lines connected to two word lines and one source line.
Are connected to the common lines 112 and 118 of FIG. In FIG. 6, the semiconductor switch 1 is also provided on the input stage side of the high-voltage decoder 104 between two word lines.
23 and 125, a semiconductor switch 127 is provided in the middle of one source line. These semiconductor switches 123, 1
25, 127 are turned on and off at the same timing as the corresponding switches 122, 124, 126 on the output stage side of the high voltage decoder 104. However, these switches 12
3, 125, 127 include switches 122, 124, 1
Since a high voltage is not applied as shown in FIG.
On and off operations are performed by the ASE and PROG signals.

Further, by bypassing the high voltage decoder 104, bypass lines 220 and 2 for connecting the output of the row decoder 102 to two word lines and one source line are provided.
22, 224 are provided. Each of the bypass lines 220,
The semiconductor switches 23 that are turned on at a timing opposite to the timing when the corresponding semiconductor switches 123, 125, and 127 are turned on in the middle of 222 and 224, respectively.
0, 232 and 234 are provided. Note that inverters 240 and 242 are provided to set the above-described ON timings of the semiconductor switches 230, 232, and 234.

According to the second embodiment, when writing data, the output from row decoder 102 is supplied to two word lines WL0, WL0 via bypass lines 220, 222.
WL1 and the high voltage decoder 1 is connected to the source line S1.
A high voltage Vpp = 12V from the power supply 04 is supplied. Also,
At the time of data erasure, the output from the row decoder 102 is supplied to the source line S1 via the bypass line 224,
The high voltage Vpp = 15 V from the high voltage decoder 104 is supplied to the word lines WL0 and WL1. When reading data, the output of the row decoder 104 is
1, supplied to word lines WL0 and WL1.

<Fourth Embodiment> Next, a semiconductor device including the semiconductor memory device according to any one of the first to third embodiments will be described with reference to FIG.

The semiconductor device shown in FIG. 7 includes a first semiconductor memory device 250 functioning as a program memory and a second semiconductor memory device 252 functioning as a data memory. These first and second semiconductor memory devices 25
Both 0 and 252 are the same as in any of the first to third embodiments, and are configured as an EEPROM. The first and second semiconductor storage devices 250 and 252
Need not have the input / output circuit 54 shown in FIG. That is, the data potential read from the memory element 10 may be amplified by the sense amplifier 56 of FIG. 1 and then directly input to another block.

The semiconductor device is further provided with a CPU 254 for controlling the semiconductor device, and a first and a second semiconductor memory devices 250 and 252 are connected to a bus line of the CPU 254.
In addition, the following various circuits are connected. RAM256
Is for temporarily storing data, and the oscillator 258 outputs a reference clock or the like. The input / output circuit 260 inputs and outputs data and control signals, and the power supply circuit 262 supplies necessary power to each unit.

In the present semiconductor device, the first and second semiconductor storage devices 250 and 252 can be driven at a low voltage and have a low element breakdown voltage, so that a semiconductor device which can be easily manufactured can be provided. . In particular, if the first and second semiconductor memory devices 250 and 252 have the layout shown in FIG. 9, there are advantages that the degree of freedom of the chip layout as a whole of the semiconductor device is increased and the design becomes easier.

While the embodiments of the present invention have been described above, the present invention is not limited to the above-described first to fourth embodiments, and various modifications may be made within the scope of the present invention. Is possible. For example, the various potentials used in the description of the above embodiments are merely examples, and it goes without saying that the present invention can be applied to other potential settings. In short, the present invention can be applied to any semiconductor memory device that needs to boost a word line or a source line.

[0131]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a semiconductor memory device of the present invention.

FIG. 2 is a schematic sectional view showing an example of a memory element used in the semiconductor memory device of the present invention.

FIG. 3 is a schematic explanatory view showing an example of a layout of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing details of a high-voltage decoder shown in FIG. 3;

FIG. 5 is a circuit diagram showing a high-voltage decoder used in a second embodiment of the present invention.

FIG. 6 is a schematic explanatory diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a block diagram of a semiconductor device using the semiconductor memory device of the present invention.

FIG. 8 is a schematic explanatory view showing a conventional layout example of a semiconductor memory device.

FIG. 9 is a schematic explanatory view showing another conventional layout example of a semiconductor memory device.

FIG. 10 is a circuit diagram showing an example of a conventional high voltage decoder.

11 is a timing chart illustrating a pumping operation of the high-voltage decoder shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Memory element 12 Source region 14 Drain region 16 Channel region 18 Floating gate 20 Control gate 100 Memory element array region 102 Row decoder 103 Boosting circuit 104, 120 High voltage decoder 110 High voltage generating circuit 120 P-type semiconductor switch 130 Level shifter 132 First N-type semiconductor switch 134 First p-type semiconductor switch 136 Second p-type semiconductor switch 210 Second n-type semiconductor switch WL0, WL1 Word line S1 Source line

Claims (8)

[Claims] 1. A semiconductor memory device comprising a large number of memory elements having source / drain regions, floating gates, and control gates, wherein each memory element is rewritten, erased, or read in response to data. A row decoder that selectively supplies a plurality of voltages equal to or less than a first voltage to a plurality of word lines connected to the control gate and extending in a row direction, wherein a second voltage higher than the first voltage is applied. A high-voltage input terminal to be input, and one high-voltage input terminal, one of which is arranged for at least one boosted line of the plurality of word lines, based on the second voltage from the high-voltage input terminal. A plurality of high-voltage decoders for selectively boosting boosting lines, respectively, wherein each of the high-voltage decoders includes the high-voltage input terminal and the at least one boosted line. A p-type semiconductor switch provided in the middle of a supply line connecting the voltage line, and a level shifter for shifting a gate potential of the p-type semiconductor switch between an on-potential and an off-potential based on an output of the row decoder. And a semiconductor storage device comprising: 2. The memory device according to claim 1, wherein the plurality of high-voltage decoders include two word lines adjacent in a column direction and the memory element connected to the two word lines and adjacent in a column direction. Connected to the source region of
A semiconductor memory device, wherein one semiconductor memory device is provided for each of a group of lines including one common source line. 3. The p-type semiconductor switch according to claim 1, wherein the level shifter is provided between the high-voltage input terminal and a ground, and the on-potential is applied to a gate of the p-type semiconductor switch based on an output of the row decoder. A first n-type semiconductor switch that supplies a voltage between the high-voltage input terminal and the first n-type semiconductor switch, the p-type semiconductor switch being turned on based on an output of the row decoder. A first p-type semiconductor switch for supplying the off-potential to the gate of the switch; a first p-type semiconductor switch provided between the high-voltage input terminal and a gate line of the first p-type semiconductor switch; The first p-type semiconductor switch is turned on and off, and supplies a potential for turning off the first p-type semiconductor switch to the gate of the first p-type semiconductor switch when the p-type semiconductor switch is on. The semiconductor memory device characterized by having a p-type semiconductor switches, a. 4. The level shifter according to claim 3, wherein the level shifter is provided between a gate line of the first p-type semiconductor switch and ground, and has an on / off timing opposite to that of the first n-type semiconductor switch. A semiconductor memory device further comprising a second n-type semiconductor switch serving as a phase. 5. The row decoder according to claim 1, wherein the row decoder is disposed at one end in a row direction in which the word lines and the source lines extend in a memory element array region in which a large number of the memory elements are arranged. And a plurality of high-voltage decoders are arranged at the other end. 6. The row decoder and the row decoder at one end in a row direction in which the word lines and the source lines extend in a memory element array region in which a large number of the memory elements are arranged. A semiconductor memory device comprising a plurality of high voltage decoders. 7. A semiconductor memory device having a large number of memory elements having source / drain regions, floating gates and control gates, wherein each memory element is rewritten, erased, or read in response to data. A row decoder that selectively supplies a plurality of voltages equal to or lower than a first voltage to a plurality of source lines connected to the source region and extending in a row direction, wherein a second voltage higher than the first voltage is applied to a plurality of source lines. A high-voltage input terminal to be input, and one at least one boosted line of the plurality of source lines, one of the plurality of source lines being arranged based on the second voltage from the high-voltage input terminal. And a plurality of high-voltage decoders for selectively boosting boosted lines, respectively, wherein each of the high-voltage decoders connects the high-voltage input terminal and the at least one boosted line. A p-type semiconductor switch provided in the middle of a supply line to be connected; and a level shifter for shifting a gate potential of the p-type semiconductor switch between an on-potential and an off-potential based on an output of the row decoder. A semiconductor memory device characterized by the above-mentioned. 8. A semiconductor memory device according to claim 1, a central processing unit; a power supply circuit for supplying power to said semiconductor memory device and said central processing unit; And a spring output circuit for inputting and outputting data to and from the central processing unit.