JP3103457B2 - Nonvolatile semiconductor memory device, and its writing method and reading method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device to which information can be electrically written, a writing method and a reading method thereof.

[0002]

2. Description of the Related Art One type of nonvolatile semiconductor memory device is EPR.
OM (Erasable and Programma)
ble Read Only Memory).
This EPROM is a read-only memory (ROM) capable of erasing stored information by irradiating ultraviolet rays and electrically writing information repeatedly.
It is.

FIG. 3 shows the electrical connection of a typical EPROM for four memory cells.

Each of the memory cells 10 to 13 has a floating gate 110 to 113 having no electrode.
The word line 100 is connected to the control gates of the memory cells 10 and 11, and the word line 101 is connected to the control gates of the memory cells 12 and 13, respectively. However, in practice, each word line and each control gate are integrally formed of, for example, polysilicon, and the word line itself forms the control gate in the region of each memory cell. On the other hand, memory cells 10 and 1
The bit line 102 is connected to each of the drains 2, and the bit line 103 is connected to each of the drains of the memory cells 11 and 13. Further, the sources of the memory cells 10 to 13 are connected to a common source line 104.

In the EPROM thus configured, conventionally, for example, when writing to the memory cell 10, the potential of the word line 100 is set to, for example, 12V, the potential of the other word lines is set to 0V, and the bit line 102 is set. Is set to, for example, 5 V, the potentials of the other bit lines are set to 0 V, and the potential of the source line 104 is set to 0 V.

At this time, assuming that the capacitance coupling coefficient (coupling ratio) between the control gate and the floating gate in each memory cell is 0.6, a potential of about 7 V is induced in the floating gate 110 of the memory cell 10. . As a result, a channel is formed between the drain and the source of the memory cell 10, and high-energy electrons (hot electrons) are generated in the vicinity of the drain due to the high gate voltage and the drain voltage. Is injected into the floating gate 110 over a potential barrier (for electrons, for example, 3.2 eV) between the gate electrode and the gate oxide film.

[0007] The electrons injected in this manner remain in the floating gate 110 even after releasing the voltage of the word line 100 and the bit line 102 because the floating gate 110 is surrounded by an oxide film having a very low conductivity. Gate 110
, And the stored state is maintained. This storage state is defined as data “0”. On the other hand, in a memory cell in which no voltage is applied to either the word line or the bit line, no electrons are injected into the floating gate, and the storage state becomes data "1".

When data is read from the memory cell 10, the potential of the word line 100 is set to, for example, 5V.
And the potentials of the other word lines are set to 0 V, the potential of the bit line 102 is set to 1 V, for example, and the potentials of the other bit lines are set to 0 V.
04 is set to 0V.

When the storage state of the memory cell 10 is "0" and its threshold voltage is high (for example, 6 to 8 V), no current flows between the drain and source of the memory cell 10, but the storage state is Is "1" and the threshold voltage is low (for example, 2 to 3 V), a current flows between the drain and source of the memory cell. Then, by comparing this difference in current with the current value of the dummy cell, the storage state of the memory cell 10 is detected, and data is read.

[0010]

In the conventional EPROM, as described above, only two storage states "0" and "1" are given to one memory cell. That is,
The unit memory cell is used only for storing 1-bit (binary) data. Therefore, there is a disadvantage that the amount of information stored in the entire memory cell array is small.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device capable of increasing its storage capacity without increasing the number of memory cells, and a write method and a read method thereof.

[0012]

A nonvolatile semiconductor memory device according to the present invention comprises a memory cell having a double gate structure of a control gate and a floating gate. In a nonvolatile semiconductor memory device that changes a value voltage and uses the changed state of the threshold voltage for storing information, a nonvolatile memory device connected to a word line connected to the control gate and a drain formed in the memory cell. A write voltage generating circuit for applying a voltage that changes to at least three levels to the word line;
A write pulse generating circuit for applying a pulsed voltage to the bit line at a predetermined timing.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, the write voltage generating circuit includes 2 ⁿ (n
.Gtoreq.2) Generates a voltage that changes stepwise to the level of the step.

In the writing method of the nonvolatile semiconductor memory device according to the present invention, at least three steps are performed on a selected word line among a plurality of word lines constituting a column line or a row line of a matrix including a plurality of memory cells. And applying a write voltage that changes to the level of the selected word line, and when a write voltage of a desired level is applied to the selected word line, among the plurality of bit lines that constitute a row line or a column line of the matrix, A pulse-like voltage is applied to the selected bit line, whereby the pulse is applied to the selected word line and the floating gate of the memory cell selected by the selected bit line, and to the selected bit line. A predetermined amount of electric charge corresponding to the level of the write voltage applied to the selected word line is injected when a constant voltage is applied. , In the selected memory cell, and stores the information corresponding to the level of the write voltage.

In one embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention, a voltage stepwise changing to a level of 2 ⁿ (n ≧ 2) is applied to the selected word line.

A nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device capable of selectively storing at least one of at least three different data, comprising a control gate, a floating gate, a drain, and a source. A memory array including a plurality of memory cells having a plurality of memory cells; a means for generating a step-like voltage that changes stepwise to a number of different levels corresponding to the number of data to be stored; a predetermined voltage level and a predetermined pulse width. Means for generating a pulse voltage having: a means for selecting one of the plurality of memory cells; and applying the step voltage and the pulse voltage to a control gate and a drain of the selected memory cell, respectively. The control gate depends on which of at least three different data is to be stored in the selected memory cell. And means for controlling the relative timing of the application of the pulse voltage to the drain for timing of application of the stepwise voltage to bets.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, a pulse width of the pulse voltage is shorter than a duration of the step voltage.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, the pulse width of the pulse voltage is longer than the shortest duration of the duration of each level of the stepped voltage. There is no pulse width.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, the at least three different data stored in each memory cell respectively correspond to at least three different levels of the threshold voltage of the memory cell. The different levels of the step voltage are determined by the different threshold voltage levels.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, the means for controlling the relative timing includes:
When the voltage level of the step-like voltage applied to the control gate is at a level corresponding to one of the at least three different data to be stored in the selected memory cell, the pulse voltage is applied to the drain. The application timing of the step-down voltage to the control gate and the application timing of the pulse voltage to the drain are controlled so as to be applied.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, the number of different data to be stored is 2 ⁿ (a positive integer of n ≧ 2), and the step-like voltage is 2 ⁿ different. Has a level.

A nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device capable of selectively storing at least one of at least three different data, and includes a control gate, a floating gate, a drain, and a source. A memory array including a plurality of memory cells, a means for selecting one of the plurality of memory cells, a write mode for writing one of the different data to the selected memory cell; Means for switching the operation of the nonvolatile semiconductor memory device between a read mode, which is a mode for reading data stored in the memory cell, and when the nonvolatile semiconductor memory device is set to the write mode, A first staircase voltage stepwise changing to a number of different levels corresponding to the number of data to be stored And when the nonvolatile semiconductor memory device is set to the read mode, generates a second step-like voltage that changes stepwise to a number of different levels corresponding to the number of data to be stored. Means,
When the nonvolatile semiconductor memory device is set to the write mode, a first pulse voltage having a predetermined pulse width and a predetermined voltage level is generated, and the nonvolatile semiconductor memory device is set to the read mode. Means for generating a second pulse voltage of a constant voltage having a predetermined pulse width when the non-volatile semiconductor memory device is set to the write mode, and the control gate of the selected memory cell. Applying the first step voltage and the first pulse voltage to the drain, respectively, and applying the first step voltage to the control gate in accordance with data to be stored in the selected memory cell; Controlling the relative timing of the application of the first pulse voltage to the drain with respect to the timing of the voltage application; When the device is set to the read mode, applying the second step voltage and the second pulse voltage to the control gate and the drain of the selected memory cell, respectively, At least as long as the step voltage is applied to the control gate, at least the timing of the application of the second step voltage to the control gate is such that the second pulse voltage is applied to the drain. Means for controlling the relative timing of application of the second pulse voltage to the drain, and the second voltage applied to the control gate when the nonvolatile semiconductor memory device is set to the read mode. The current flowing through the drain-source circuit of the selected memory cell at each level of And a means.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, a pulse width of the first pulse voltage is shorter than a duration of the first step voltage.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, a pulse width of the second pulse voltage is shorter than a duration of the second step voltage.

In one embodiment of the nonvolatile semiconductor memory device according to the present invention, the pulse width of the first pulse voltage is the shortest of the durations of the voltages at the respective levels at which the first step-like voltage is generated. A pulse width that is no longer than a short duration.

The writing method of the nonvolatile semiconductor memory device according to the present invention comprises a control gate, a floating gate,
A method for selectively writing at least one of at least three different data to a nonvolatile semiconductor memory device including a memory array including a plurality of memory cells having a drain and a source, the method comprising: Selecting and writing one of the at least three different data to the selected memory cell, generating a step-like voltage that changes stepwise to a number of different levels corresponding to the number of the different data. Applying a pulse voltage having a predetermined pulse width and a predetermined voltage level to the gate electrode of the selected memory cell, and applying the pulse voltage to the drain of the selected memory cell; Of the application of the step-like voltage to the control gate depends on which of the following is to be written to the selected memory cell. For, controlling the relative timing of the application of the pulse voltage to the drain.

In one embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention, a pulse width of the pulse voltage is shorter than a duration of the step voltage.

In one embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention, the pulse width of the pulse voltage is the shortest one of the durations of the voltages of the respective levels in which the step-like voltage is generated. Shorter pulse width.

In one embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention, the at least three different data correspond to different levels set for the threshold voltage of each memory cell.

In one embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention, the different levels of the step-like voltages are determined based on the different levels of the threshold voltages of the respective memory cells.

In one embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention, the number of the different data is 2 ⁿ (n is a positive integer of 2) and the stepped voltage is a different 2 ⁿ level. With.

The reading method of the nonvolatile semiconductor memory device according to the present invention comprises a control gate, a floating gate,
A method for reading one of at least three different data written in a nonvolatile semiconductor memory device including a memory array including a plurality of memory cells having a drain and a source, wherein one of the plurality of memory cells to be read is read. Selecting one, generating a step-like voltage that changes stepwise to a number of different levels corresponding to the number of different data, and applying the step-like voltage to the control gate of the selected memory cell;
A pulse voltage having a predetermined pulse width and a constant voltage is generated and applied to the drain of the selected memory cell,
At each level of the step-like voltage applied to the control gate of the selected memory cell, a drain-source current of the selected memory cell is detected.

In one embodiment of the reading method of the nonvolatile semiconductor memory device according to the present invention, the pulse width of the pulse voltage is not shorter than the duration of the step-like voltage.

In one embodiment of the method for reading a nonvolatile semiconductor memory device according to the present invention, a plurality of reference cells each having the same configuration and electrical characteristics as a memory cell are provided, and a drain of the selected memory cell is provided. -After detecting the source current, the drain-source current of the selected memory cell is sequentially compared with the drain-source current of each reference cell to determine the data written in the selected memory cell.

[0035]

According to the present invention, when data is written to a unit memory cell using three or more values of data, for example, a write voltage that changes to a level of 2 ⁿ (n ≧ 2) steps, n
Since bit (2n value) data can be stored, the storage capacity of the entire device can be increased without increasing the number of memory cells.

[0036]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1A shows an EPRO to which the present invention is applied.
The main configuration of M is shown.

In the figure, the configuration of each memory cell constituting the memory cell array 1 and the connection between them and the word line, bit line and source line are the same as those described in FIG. The word line connected to the control gate of each memory cell is connected to the column decoder 2, while the bit line connected to the drain of each memory cell is connected to the row decoder 3 via the row selector 4. .

An address signal input via the address buffer 5 is sent to these decoders 2 and 3, and the decoders 2 and 3 respectively provide column lines (word lines).
And a row line (bit line) is selected.

A variable voltage generating circuit 6 for generating a voltage whose level changes stepwise is connected to each word line of the memory cell array 1 via the column decoder 2, and generates a pulse-like voltage. A circuit 7 is connected to each bit line of the memory cell array 1 via the row selector 4. In the figure, reference numeral 8 denotes a reading circuit.

Next, the write operation of the EPROM of this embodiment will be described with reference to FIGS. 1 (a) and 1 (b) and FIG.

Now, when writing to the memory cell 10 shown in FIG. 3, as shown in FIG.
A stepped voltage whose level changes stepwise at 10 V, 11 V, and 12 V every time is generated by a variable voltage generation circuit 6 built in a semiconductor chip, and the stepped voltage is applied to the column decoder 2.
Is applied to the selected word line 100, and the potentials of the other word lines are all set to 0V.

Then, for example, 11V is applied to the word line 100.
, A voltage of, for example, 8.5 V is applied to the bit line 102 selected by the row decoder 3 from the pulse generation circuit 7 for 0.8 ms, and the potentials of the other bit lines are All are set to 0V. This application time can be set to an appropriate value between 0.5 and 1 ms. The potential of the common source 104 is set to 0V.

As a result, a channel is formed between the drain and the source of the memory cell 10, and hot electrons generated near the drain due to the high gate voltage and the drain voltage cross the potential barrier between the silicon and the gate oxide film. Information is written by being injected into the floating gate 110. As a result, the threshold voltage of the memory cell 10 becomes about 4 V, and this state is set to the “10” state.

Similarly, the bit line 1 is synchronized with the timing when a voltage of 10 V is applied to the word line 100.
When a pulse voltage of 8.5 V is applied to the memory cell 02, the threshold voltage of the memory cell 10 becomes about 3 V.
1 "state.

Further, when a pulse-like voltage of 8.5 V is applied to the bit line 102 in synchronization with the timing at which a voltage of 12 V is applied to the word line 100, the memory cell 10
Becomes about 5 V, and this state is referred to as an "11" state.

Then, a state in which writing is not performed on the memory cell 10 is set to a “00” state. The threshold voltage of the memory cell 10 in this state is about 2V.

As described above, the programming method uses the channel hot electron injection method and utilizes the characteristic that the threshold voltage (V _th ) after programming changes according to the voltage (V _CG ) applied to the control gate. . FIG. 4 shows the relationship between the writing time and the threshold voltage after writing when the voltage applied to the control gate is changed. By applying a step-like voltage generated from a built-in circuit to a selected word line and controlling the timing of a pulse applied to a bit line, four types of threshold voltages (V _th ) after programming can be set. Become. As for the set value of the threshold voltage, one state is set for a state in which writing is not performed, and the other states are set every 3 [V] to 1 [V].

Next, the read operation of the EPROM of this embodiment will be described.

Now, when reading data from the memory cell 10, 2.5 V, 3.5 V, 4.5 every 1 ms from 0 V.
A variable voltage generating circuit 6 generates a step-like voltage whose level changes in a step-like manner with V.
And the potentials of all other word lines are set to 0V.
Further, the potential of the bit line 102 is set to, for example, 1 V, the potentials of all other bit lines are set to 0 V, and the potential of the common source 104 is set to 0 V.

When a current flows between the drain and the source of the memory cell 10 when a voltage of 2.5 V is applied to the word line 100, the read circuit 8 outputs "0".
0 "data is output to the word line 100.
If a current does not flow between the drain and the source when a voltage of 5 V is applied, and if a current flows when a voltage of 3.5 V is applied, the read circuit 8 outputs data of “01”. Further, when a current does not flow between the drain and the source even when a voltage of 3.5 V is applied to the word line 100 and a current flows for the first time when a voltage of 4.5 V is applied, the read circuit 8 Outputs data "10". When the current does not flow even when the voltage of 4.5 V is applied, the read circuit 8 sets “1”.
1 "data is output.

As described above, the EPR of this embodiment is
In the OM, four “00” to “11” are stored in one memory cell.
A value, that is, 2-bit data, can be stored and read.

It is to be noted that the erasing of the stored state is carried out for all the memory cells at once by irradiating the well-known ultraviolet rays.

Although specific voltage values have been shown in the above embodiments, these voltage values correspond to the structure of the memory cell,
In particular, it should be appropriately changed depending on the capacitance of the gate oxide film and the interlayer insulating film and the value of the capacitance coupling coefficient (coupling ratio).

Next, with reference to the equivalent circuit of the memory cell shown in FIG. 2, the principle that the threshold voltage after writing changes by the voltage applied to the control gate will be described.

[0056] Now, a control gate, a floating gate, a drain, source and substrate potential of each _{V CG,} and _{V FG,} V _D, V _S and _{Vs UB,} between the control gate and the floating gate, between the floating gate and the substrate , The capacitance between the floating gate and the drain and the capacitance between the floating gate and the source are C ₂ , C ₁ , C ₄ and C ₃ , respectively.

Then, assuming that the amount of charge stored in the floating gate is Q, according to the law of conservation of charge, Q = C ₂ (V _FG −V _CG ) + C ₁ (V _FG −V _SUB ) + C ₃ (V _FG) −V _S ) + C ₄ (V _FG −V _D ) (1)

Here, if V _S = V _SUB = 0, V _FG = (C ₂ · V _CG + C ₄ · V _D + Q) / C _T (2) where C _T = C ₁ + C ₂ + C ₃ + the _{C 4.}

[0059] Then, when the threshold voltage of the transistor, as viewed from the control gate and floating gate and each _{V T} and _{V FT,} when Q = 0 _{is, V FT = (C 2 ·} V T + C 4 · V D) / C _T (3) When Q = ΔQ, V _FT ′ = (C ₂ ＶV _T ′ + C ₄ ＶV _D + ΔQ) / C _T (4) holds.

Here, since the threshold voltage of the transistor viewed from the floating gate is constant regardless of the value of Q, V _FT = V _FT '.

[0061] Therefore, (4) - the equation _{(3), C 2 (V T '-V} T) / C T = ΔQ / C T ... (5).

[0062] _Depending, if the _{V T -V T '= ΔV T} , the _{C 2 · ΔV T = -ΔQ ...} (6).

By the way, V_CGBy a small amount
V_CG+ ΔV_CGThen, Q also becomes Q + ΔQ,
Equation (2) is_FG+ ΔV_FG= ｛C₂(V_CG+ ΔV_CG) + C₄・ V_D  + (Q + ΔQ)｝ / C_T ... (7)

Therefore, from the equation (7)-(2), ΔV _FG = (C ₂ · ΔV _CG + ΔQ) / C _T (8)

By substituting equation (6) into equation (8), ΔV _FG = C ₂ (ΔV _CG −ΔV _T ) / C _T (9)

Here, ΔV _FG = 0 after a sufficient time has elapsed for injecting charges into the floating gate.

Therefore, ΔV _CG = ΔV _T (10)

Thus, it can be seen that the threshold voltage after writing changes depending on the voltage applied to the control gate.

[0069]

According to the present invention, a unit memory cell of a nonvolatile semiconductor memory device such as an EPROM has three or more values, for example, n or more.
Since (n ≧ 2) bits of data can be stored, a large storage capacity can be obtained without increasing the number of memory cells.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a main part configuration of an EPROM according to an embodiment of the present invention, and a timing chart showing applied voltages at the time of writing.

FIG. 2 is an equivalent circuit diagram of a unit memory cell of an EPROM.

FIG. 3 is an electrical connection diagram of four memory cells of the EPROM.

FIG. 4 is a characteristic diagram showing a relationship between a writing time and a threshold voltage after writing when a voltage applied to a control gate is changed.

[Explanation of symbols]

Reference Signs List 1 memory cell array 2 column decoder 3 row decoder 6 variable voltage generator 7 pulse generator 8 readout circuit 10, 11, 12, 13 memory cell 100, 101 word line (control gate) 102, 103 bit line 104 source line 110, 111 , 112,113 Floating gate

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasuo Sato 5-10-1 Fuchinobe, Sagamihara-shi Nippon Steel Corporation Electronics Research Laboratory (72) Inventor Yuichi Egawa 5-10-1 Fuchinobe, Sagamihara-shi Nippon Steel (56) References JP-A-3-237692 (JP, A) JP-A-62-6493 (JP, A) JP-A-62-257699 (JP, A) (58) Fields investigated ( Int.Cl. ⁷ , DB name) G11C 16/02

Claims (19)

(57) [Claims] 1. A nonvolatile semiconductor memory device capable of selectively storing one of at least three different data, comprising: a control gate, a floating gate, a drain,
A memory array including a plurality of memory cells having a source; a means for generating a step-like voltage that changes stepwise to a number of different levels corresponding to the number of data to be stored; a predetermined voltage level and a predetermined pulse Means for generating a pulse voltage having a width, means for selecting one of the plurality of memory cells, and applying the step voltage and the pulse voltage to a control gate and a drain of the selected memory cell, respectively. The relative timing of applying the pulse voltage to the drain with respect to the timing of applying the staircase voltage to the control gate depends on which of the at least three different data is to be stored in the selected memory cell. Controlling means for controlling the non-volatile semiconductor memory device. 2. A pulse width of the pulse voltage is shorter than a duration of the step voltage.
3. The nonvolatile semiconductor memory device according to 1. 3. The pulse width of the pulse voltage is not longer than the shortest duration of the duration of the voltage of each level in which the stepped voltage is generated. 2. The nonvolatile semiconductor memory device according to 1. 4. The at least three different data stored in each memory cell respectively correspond to at least three different levels of a threshold voltage of the memory cell,
4. The nonvolatile semiconductor memory device according to claim 1, wherein different levels of the step-like voltage are determined by the different threshold voltage levels. 5. 5. The means for controlling the relative timing, wherein a voltage level of a step-like voltage applied to the control gate is one of the at least three different data to be stored in the selected memory cell. Controlling the application timing of the step-down voltage to the control gate and the timing of application of the pulse voltage to the drain so that the pulse voltage is applied to the drain when the level is at a level corresponding to The nonvolatile semiconductor memory device according to claim 1, wherein: 6. The method according to claim 1, wherein the number of different data to be stored is 2 ⁿ (a positive integer of n ≧ 2), and the step-like voltage has 2 ⁿ different levels. 7. The non-volatile semiconductor storage device according to claim 1. 7. A nonvolatile semiconductor memory device capable of selectively storing one of at least three different data, comprising: a control gate, a floating gate, a drain,
A memory array including a plurality of memory cells having a source; a unit for selecting one of the plurality of memory cells; a write mode for writing one of the different data to the selected memory cell; Means for switching the operation of the nonvolatile semiconductor memory device between a read mode, which is a mode for reading data stored in the selected memory cell, and when the nonvolatile semiconductor memory device is set to the write mode Generating a first stepwise voltage that changes stepwise to a number of different levels corresponding to the number of data to be stored, and when the nonvolatile semiconductor memory device is set to the read mode, Means for generating a second step-like voltage that changes stepwise to a number of different levels corresponding to the number of data to be obtained; When the volatile semiconductor memory device is set to the write mode, a first pulse voltage having a predetermined pulse width and a predetermined voltage level is generated, and the nonvolatile semiconductor memory device is set to the read mode. Means for generating a second pulse voltage of a constant voltage having a predetermined pulse width; and when the nonvolatile semiconductor memory device is set to the write mode, the control gate of the selected memory cell; Applying the first step voltage and the first pulse voltage to a drain, respectively, and applying the first step voltage to the control gate in accordance with data to be stored in the selected memory cell Controlling the relative timing of the application of the first pulse voltage to the drain with respect to the application timing of the nonvolatile semiconductor memory device. Is set to the read mode, the control gate and the drain of the selected memory cell are connected to the second step voltage and the second
And while the second step voltage is applied to the control gate, at least as long as the second pulse voltage is applied to the drain. Means for controlling the relative timing of the application of the second pulse voltage to the drain with respect to the timing of the application of the second staircase voltage, wherein the nonvolatile semiconductor memory device is set to the read mode. Means for detecting a current flowing through a drain-source circuit of the selected memory cell at each level of the second step-like voltage applied to the control gate. Semiconductor memory device. 8. The non-volatile semiconductor memory device according to claim 7, wherein a pulse width of said first pulse voltage is shorter than a duration of said first step voltage. 9. The nonvolatile semiconductor memory device according to claim 7, wherein a pulse width of said second pulse voltage is shorter than a duration of said second step-like voltage. 10. The pulse width of the first pulse voltage is:
8. The non-volatile semiconductor memory device according to claim 7, wherein the pulse width is not longer than the shortest duration among the durations of the voltages of the respective levels at which the first stepped voltage is generated. 11. A method for selectively writing one of at least three different data to a nonvolatile semiconductor memory device including a memory array including a plurality of memory cells having a control gate, a floating gate, a drain, and a source. And selecting one of the plurality of memory cells, and writing one of the at least three different data to the selected memory cell, the number of different levels corresponding to the number of different data Generating a step voltage that changes in a step-like manner and applying the voltage to the gate electrode of the selected memory cell to generate a pulse voltage having a predetermined pulse width and a predetermined voltage level. Depending on which of the at least three different data is to be written to the selected memory cell For timing of application of the stepped voltage to the control gate, the writing method of the nonvolatile semiconductor memory device characterized by controlling the relative timing of the application of the pulse voltage of the Doreinhe. 12. The method according to claim 11, wherein a pulse width of the pulse voltage is shorter than a duration of the step-like voltage. 13. The pulse width of the pulse voltage is shorter than the shortest duration of the duration of the voltage of each level in which the stepped voltage is generated. 3. The writing method for a nonvolatile semiconductor memory device according to item 1. 14. The memory device according to claim 11, wherein said at least three different data correspond to different levels of threshold voltages of said memory cells.
The method for writing data in a nonvolatile semiconductor memory device according to any one of the above items. 15. The nonvolatile memory according to claim 11, wherein the different levels of the step-like voltages are determined based on the different levels of the threshold voltages of the respective memory cells. Writing method for nonvolatile semiconductor memory device. 16. The number of different data is 2 ⁿ (n ≧ 2)
16. The method according to claim 11, wherein the step voltage has 2 ⁿ different levels.
13. The writing method for the nonvolatile semiconductor memory device according to item 9. 17. A method for reading one of at least three different data written in a nonvolatile semiconductor memory device having a memory array including a plurality of memory cells having a control gate, a floating gate, a drain, and a source. Selecting one of the plurality of memory cells to be read, generating a step-like voltage that changes stepwise to a number of different levels corresponding to the number of different data, and generating a step-like voltage of the selected memory cell. Applying to the control gate, generating a pulse voltage of a predetermined voltage having a predetermined pulse width, applying the pulse voltage to the drain of the selected memory cell, and applying the pulse voltage to the control gate of the selected memory cell Detecting the drain-source current of the selected memory cell at each level of the step voltage. The method of reading a nonvolatile semiconductor memory device according to. 18. The method according to claim 17, wherein a pulse width of the pulse voltage is not shorter than a duration of the step-like voltage. 19. A method comprising: providing a plurality of reference cells each having the same configuration and electrical characteristics as a memory cell; detecting a drain-source current of the selected memory cell; and detecting a drain-source current of the selected memory cell. 18. The method according to claim 17, wherein a source current is sequentially compared with a drain-source current of each reference cell to determine data written in the selected memory cell.
19. A method for reading a nonvolatile semiconductor memory device according to item 18.