JPS61150190A - Refresh control circuit - Google Patents

Abstract

PURPOSE:To simplify peripheral circuits concerning with a timing control by exchanging a RAS and a CAS generated at a timing during reading/writing only in the case of a refresh operation and supplying it to a DRAM. CONSTITUTION:In case of a request signal RQ, a strobe exchanging command EX is high, while in case of a refresh activating signal RS, the command EX is low, and timing signals Sa and Sb are exchanged with in the case of the signal RQ and supplied to RAS, CAS terminals of a DRAM20. The DRAM20 detects that the refresh is designated considering a reverse in terms of the timing of the RAS and the CAS, performs the refresh with respect to a line by a line address held to a address counter and progresses little by little. In this manner the refresh of the RAS system before the CAS is executed. Particularly, in the case of the DRAM operating at a nibble mode, a timing system becomes further simpler.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a DRAM glueless L control circuit.

Conventional technology dynamic RAM (DRAM) has refresh,
It has a built-in row address counter for i, and each time a corresponding command is received at the refresh command terminal.

71 for the line specified by the contents of the built-in line counter above.
There is a method in which the contents of the counter are incremented in preparation for the 9th NoriFrere 1 while executing the J refresh.

Furthermore, as a countermeasure for the case where the refresh command terminal cannot be secured, there is a CAs-before-RAS-Fr1 control system in which refresh is commanded by making the timing relationship between RAS and CAS different from that in the case of a read/write command.

In other words, during normal read/write operations, RAS is
When CAS falls, the row address is latched, and when CAS falls, the column address is latched.However, in the CAS-before-RλS refresh control method, the DRAM command to refresh.

Problems to be Solved by the Invention The above-mentioned conventional CAS-before-RAS method has the advantage of saving refresh command terminals, but on the other hand, since the timing relationship of the strobe signal is different from that during normal read/write operations, the timing relationship of the strobe signal is There is a problem that two timing control systems are required and one peripheral circuit becomes complicated.

In particular, r) I that performs nibble mode glue read/write control.
? AM has a problem in that timing control becomes complicated.

Configuration of the Invention Means for Solving the Problems Section E A refresh control circuit of the present invention that solves the problems of the prior art performs RA at read/write timing based on both read/write commands or refresh commands.
A strobe signal generation circuit that generates S and CAS, and RAS and CA generated by this strobe signal generation circuit.
By providing a strobe signal switching circuit that switches S and supplies it to the DRAM only in the case of a refresh operation.

It is configured to simplify peripheral circuits related to timing control.

Hereinafter, the effects of the present invention will be explained in detail with reference to nine examples.

FIG. 1 shows a refresh control circuit (9) according to an embodiment of the present invention.
10) together with a DRAM (20) to be controlled. FIG.

This refresh demand control circuit 10 has a refresh counter 11 . Refresh startup time Ill 2° OR gate 13. A strobe signal generation circuit 14 and a strobe signal switching circuit 15 are provided.

The refresh counter 11 counts up at a predetermined speed and refreshes the count contents with the start circuit 12.
supply to. When the count value of the refresh counter 11 reaches a predetermined value, the refresh activation circuit 12 outputs a refresh activation signal R3 and resets the refresh counter 11 with a reset signal R3T. The refresh activation signal R3 output from the refresh activation circuit 12 is supplied to the strobe signal generation circuit 14 via the OR gate 13. At the same time, the refresh/1 start circuit 12 starts the strobe signal change circuit 15.
The strobe signal exchange command EX is issued.

On the other hand, during normal read/write I for the DRAM 20, a request signal RQ regarding memory access for read/write is supplied to the strobe signal generation circuit 14 via the OR gate 13.

The strobe signal generation circuit 14 generates a timing signal Sa having a predetermined correlation, regardless of whether the signal received via the OR gate 13 is a refresh activation signal R8 or a request signal RQ regarding normal read/write operations. and Sb are generated. These timing signals Sa and sb are RAS during normal read/write operations, respectively.
and has a timing relationship corresponding to CAS.

That is, as illustrated in the timing chart of FIG. 2, even in the case (A) where the request signal RQ falls in connection with the normal read/write operation, the refresh activation signal R5 falls (R). Even in the case of 1, the timing signal Sa corresponding to RAS during normal read/write falls first, and the same (timing signal sb corresponding to CAS) falls.

The strobe signal switching circuit 15 receives the request signal RQ.
When the timing signals Sa and Sb are generated based on the above, as shown in FIG. 2(A).

Since the strobe signal exchange commands F and X remain high, set the timing signal Sa to RAS.

Also, by using the timing signal sb as CAS, the DRAM
20 corresponding input terminals.

On the other hand, when the timing signals Sa and sb are generated based on the refresh start signal R3, the strobe signal switching circuit 15 causes the strobe signal switching commands P and X to go low as shown in FIG. 2(R). Therefore, the timing signals Sa and Sb are supplied to the RAS input terminal and the CAS input terminal of the DRAM 20, with the timing signals Sa and Sb switched from those used during normal read/write. As a result, the timing signal Sa that falls first is CAS,! : L, the timing signal Sb is supplied to the CAS input terminal of the DRAM 20 and falls with a delay.
is supplied to the RAS input terminal of the DRAM 20 as RAS.

The DRAM 20 detects that Frere 1 is being commanded due to the reversal of the timing relationship between RAS and CAS, and applies refresh, - to the row specified by the row address held in the built-in address counter. At the same time, the address counter is incremented. In this way, the CAS Bifusara RAS method Norifurere 1 is executed.

FIG. 3 shows a DR in which the DRAM 20 operates in nibble mode.
It is a timing chart of refresh in the case of AM.

The strobe signal generation circuit 14 determines whether the signal received via the OR gate 13 is the refresh activation signal R8.
Il! Timing signals Sa and Sb corresponding to RAS and CAS in the nibble mode are generated at the timing of normal read/write regardless of whether the request signal RQ is based on a normal read/write command.

In other words, as illustrated in the timing chart of FIG.
Even in the case where RQ falls (A) or when the refresh activation signal R3 falls (R), the timing signal S corresponding to RAS during normal read/write is applied.
The signal a first falls, and then the timing signal Sb corresponding to CAS falls a predetermined number of times (four times in this example).

The strobe signal switching circuit 15 receives the request signal RQ.
When the timing signals Sa and Sb are generated based on the above, as shown in FIG. 3(A).

Since the strobe signal exchange commands F and X remain high, set the timing signal Sa to RAS.

Also, assuming the timing signal sb is CAS, each DR
Supplied to the corresponding input terminal of AM20. As a result, nibble mode read/write is performed.

On the other hand, the strobe signal switching circuit 15
When the timing signals Sa and Sb are generated based on the activation signal R3, the strobe signal exchange command EX falls to low level as shown in FIG. 2(R), so the timing signals Sa and Sb are set to normal. I'? of DRAM 20 is swapped when reading/writing. Supplied to the AS input terminal and CAS input terminal. As a result, the timing signal Sa that falls first is supplied as CAS to the CAS input terminal of the RAM 20, and the timing signal Sb that falls four times after a delay.
is supplied to the RAS input terminal of the TDRAM 20.

The DRAM 20 detects that the timing relationship between RAS and CAS is reversed, and that a command of 1 is being issued.
Refreshes the row address held in the built-in address counter.

Increments the address counter. In this case, after CAS falls, each time RAS falls, the row address is shifted to Frere 1 and the address counter is moved. In other words, refresh activation signal R3I! Each time l<1 occurs, four consecutive lines are sequentially refreshed.

Effects of the Invention As explained in detail above, the refresh control circuit of the present invention has a configuration in which the normal read/write RAS and CAS are simply switched and supplied to the DRAM during refresh, so that two independent systems can be used. This has the advantage that the circuit configuration is extremely simple compared to a conventional circuit provided with a timing control system.

In particular, in response to read/write operations in nibble mode, a predetermined number of rows can be refreshed and 1'd at the same time with a single refresh command.

The timing system becomes even simpler.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a refresh control circuit according to an embodiment of the present invention together with a DRAM, and FIGS. 2 and 3 are timing charts for explaining the operation of the circuit shown in FIG. 1. 11: Refresh counter, 12: Refresh start signal, 13: OR gate, 14: Strobe signal generation circuit, 15: Strobe signal switching circuit.

Claims (1)

[Claims] In a DRAM refresh control circuit capable of CAS-before-RAS refresh, RAS and CAS are refreshed at read/write timing based on both a read/write command or a refresh command.
A strobe signal generation circuit that generates RAS and CA generated by the strobe signal generation circuit.
What is claimed is: 1. A refresh control circuit comprising: a strobe signal switching circuit that switches S only in a refresh operation and supplies the strobe signal to a DRAM.